projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 5cbad0eb JW |
1 | /* |
| 2 | * ARM KGDB support | |
| 3 | * | |
| 4 | * Author: Deepak Saxena <dsaxena@mvista.com> | |
| 5 | * | |
| 6 | * Copyright (C) 2002 MontaVista Software Inc. | |
| 7 | * | |
| 8 | */ | |
| 9 | ||
| 10 | #ifndef __ARM_KGDB_H__ | |
| 11 | #define __ARM_KGDB_H__ | |
| 12 | ||
| 13 | #include <linux/ptrace.h> | |
| 5a8b93fc | 14 | #include <asm/opcodes.h> |
| 5cbad0eb JW |
15 | |
| 16 | /* | |
| 17 | * GDB assumes that we're a user process being debugged, so | |
| 18 | * it will send us an SWI command to write into memory as the | |
| 19 | * debug trap. When an SWI occurs, the next instruction addr is | |
| 20 | * placed into R14_svc before jumping to the vector trap. | |
| 21 | * This doesn't work for kernel debugging as we are already in SVC | |
| 22 | * we would loose the kernel's LR, which is a bad thing. This | |
| 23 | * is bad thing. | |
| 24 | * | |
| 25 | * By doing this as an undefined instruction trap, we force a mode | |
| 26 | * switch from SVC to UND mode, allowing us to save full kernel state. | |
| 27 | * | |
| 28 | * We also define a KGDB_COMPILED_BREAK which can be used to compile | |
| 29 | * in breakpoints. This is important for things like sysrq-G and for | |
| 30 | * the initial breakpoint from trap_init(). | |
| 31 | * | |
| 32 | * Note to ARM HW designers: Add real trap support like SH && PPC to | |
| 33 | * make our lives much much simpler. :) | |
| 34 | */ | |
| 35 | #define BREAK_INSTR_SIZE 4 | |
| 36 | #define GDB_BREAKINST 0xef9f0001 | |
| 37 | #define KGDB_BREAKINST 0xe7ffdefe | |
| 38 | #define KGDB_COMPILED_BREAK 0xe7ffdeff | |
| 39 | #define CACHE_FLUSH_IS_SAFE 1 | |
| 40 | ||
| 41 | #ifndef __ASSEMBLY__ | |
| 42 | ||
| 43 | static inline void arch_kgdb_breakpoint(void) | |
| 44 | { | |
| 5a8b93fc | 45 | asm(__inst_arm(0xe7ffdeff)); |
| 5cbad0eb JW |
46 | } |
| 47 | ||
| 48 | extern void kgdb_handle_bus_error(void); | |
| 49 | extern int kgdb_fault_expected; | |
| 50 | ||
| 51 | #endif /* !__ASSEMBLY__ */ | |
| 52 | ||
| 53 | /* | |
| 54 | * From Kevin Hilman: | |
| 55 | * | |
| 56 | * gdb is expecting the following registers layout. | |
| 57 | * | |
| 58 | * r0-r15: 1 long word each | |
| 59 | * f0-f7: unused, 3 long words each !! | |
| 60 | * fps: unused, 1 long word | |
| 61 | * cpsr: 1 long word | |
| 62 | * | |
| 63 | * Even though f0-f7 and fps are not used, they need to be | |
| 64 | * present in the registers sent for correct processing in | |
| 65 | * the host-side gdb. | |
| 66 | * | |
| 67 | * In particular, it is crucial that CPSR is in the right place, | |
| 68 | * otherwise gdb will not be able to correctly interpret stepping over | |
| 69 | * conditional branches. | |
| 70 | */ | |
| 71 | #define _GP_REGS 16 | |
| 72 | #define _FP_REGS 8 | |
| 73 | #define _EXTRA_REGS 2 | |
| 834b2964 RV |
74 | #define GDB_MAX_REGS (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS) |
| 75 | #define DBG_MAX_REG_NUM (_GP_REGS + _FP_REGS + _EXTRA_REGS) | |
| 5cbad0eb JW |
76 | |
| 77 | #define KGDB_MAX_NO_CPUS 1 | |
| 78 | #define BUFMAX 400 | |
| 22eeef4b | 79 | #define NUMREGBYTES (DBG_MAX_REG_NUM << 2) |
| 5cbad0eb JW |
80 | #define NUMCRITREGBYTES (32 << 2) |
| 81 | ||
| 82 | #define _R0 0 | |
| 83 | #define _R1 1 | |
| 84 | #define _R2 2 | |
| 85 | #define _R3 3 | |
| 86 | #define _R4 4 | |
| 87 | #define _R5 5 | |
| 88 | #define _R6 6 | |
| 89 | #define _R7 7 | |
| 90 | #define _R8 8 | |
| 91 | #define _R9 9 | |
| 92 | #define _R10 10 | |
| 93 | #define _FP 11 | |
| 94 | #define _IP 12 | |
| 95 | #define _SPT 13 | |
| 96 | #define _LR 14 | |
| 97 | #define _PC 15 | |
| 834b2964 | 98 | #define _CPSR (GDB_MAX_REGS - 1) |
| 5cbad0eb JW |
99 | |
| 100 | /* | |
| 101 | * So that we can denote the end of a frame for tracing, | |
| 102 | * in the simple case: | |
| 103 | */ | |
| 104 | #define CFI_END_FRAME(func) __CFI_END_FRAME(_PC, _SPT, func) | |
| 105 | ||
| 106 | #endif /* __ASM_KGDB_H__ */ |