[deliverable/linux.git] / arch / arm / include / asm / pmu.h

/*
 *  linux/arch/arm/include/asm/pmu.h
 *
 *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef __ARM_PMU_H__
#define __ARM_PMU_H__

#include <linux/interrupt.h>
#include <linux/perf_event.h>

#include <asm/cputype.h>

/*
 * struct arm_pmu_platdata - ARM PMU platform data
 *
 * @handle_irq: an optional handler which will be called from the
 *	interrupt and passed the address of the low level handler,
 *	and can be used to implement any platform specific handling
 *	before or after calling it.
 * @runtime_resume: an optional handler which will be called by the
 *	runtime PM framework following a call to pm_runtime_get().
 *	Note that if pm_runtime_get() is called more than once in
 *	succession this handler will only be called once.
 * @runtime_suspend: an optional handler which will be called by the
 *	runtime PM framework following a call to pm_runtime_put().
 *	Note that if pm_runtime_get() is called more than once in
 *	succession this handler will only be called following the
 *	final call to pm_runtime_put() that actually disables the
 *	hardware.
 */
struct arm_pmu_platdata {
	irqreturn_t (*handle_irq)(int irq, void *dev,
				  irq_handler_t pmu_handler);
	int (*runtime_resume)(struct device *dev);
	int (*runtime_suspend)(struct device *dev);
};

#ifdef CONFIG_HW_PERF_EVENTS

/*
 * The ARMv7 CPU PMU supports up to 32 event counters.
 */
#define ARMPMU_MAX_HWEVENTS		32

#define HW_OP_UNSUPPORTED		0xFFFF
#define C(_x)				PERF_COUNT_HW_CACHE_##_x
#define CACHE_OP_UNSUPPORTED		0xFFFF

#define PERF_MAP_ALL_UNSUPPORTED					\
	[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED

#define PERF_CACHE_MAP_ALL_UNSUPPORTED					\
[0 ... C(MAX) - 1] = {							\
	[0 ... C(OP_MAX) - 1] = {					\
		[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED,	\
	},								\
}

/* The events for a given PMU register set. */
struct pmu_hw_events {
	/*
	 * The events that are active on the PMU for the given index.
	 */
	struct perf_event	*events[ARMPMU_MAX_HWEVENTS];

	/*
	 * A 1 bit for an index indicates that the counter is being used for
	 * an event. A 0 means that the counter can be used.
	 */
	DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);

	/*
	 * Hardware lock to serialize accesses to PMU registers. Needed for the
	 * read/modify/write sequences.
	 */
	raw_spinlock_t		pmu_lock;

	/*
	 * When using percpu IRQs, we need a percpu dev_id. Place it here as we
	 * already have to allocate this struct per cpu.
	 */
	struct arm_pmu		*percpu_pmu;
};

struct arm_pmu {
	struct pmu	pmu;
	cpumask_t	active_irqs;
	char		*name;
	irqreturn_t	(*handle_irq)(int irq_num, void *dev);
	void		(*enable)(struct perf_event *event);
	void		(*disable)(struct perf_event *event);
	int		(*get_event_idx)(struct pmu_hw_events *hw_events,
					 struct perf_event *event);
	void		(*clear_event_idx)(struct pmu_hw_events *hw_events,
					 struct perf_event *event);
	int		(*set_event_filter)(struct hw_perf_event *evt,
					    struct perf_event_attr *attr);
	u32		(*read_counter)(struct perf_event *event);
	void		(*write_counter)(struct perf_event *event, u32 val);
	void		(*start)(struct arm_pmu *);
	void		(*stop)(struct arm_pmu *);
	void		(*reset)(void *);
	int		(*request_irq)(struct arm_pmu *, irq_handler_t handler);
	void		(*free_irq)(struct arm_pmu *);
	int		(*map_event)(struct perf_event *event);
	int		num_events;
	atomic_t	active_events;
	struct mutex	reserve_mutex;
	u64		max_period;
	struct platform_device	*plat_device;
	struct pmu_hw_events	__percpu *hw_events;
	struct notifier_block	hotplug_nb;
};

#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))

extern const struct dev_pm_ops armpmu_dev_pm_ops;

int armpmu_register(struct arm_pmu *armpmu, int type);

u64 armpmu_event_update(struct perf_event *event);

int armpmu_event_set_period(struct perf_event *event);

int armpmu_map_event(struct perf_event *event,
		     const unsigned (*event_map)[PERF_COUNT_HW_MAX],
		     const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
						[PERF_COUNT_HW_CACHE_OP_MAX]
						[PERF_COUNT_HW_CACHE_RESULT_MAX],
		     u32 raw_event_mask);

struct pmu_probe_info {
	unsigned int cpuid;
	unsigned int mask;
	int (*init)(struct arm_pmu *);
};

#define PMU_PROBE(_cpuid, _mask, _fn)	\
{					\
	.cpuid = (_cpuid),		\
	.mask = (_mask),		\
	.init = (_fn),			\
}

#define ARM_PMU_PROBE(_cpuid, _fn) \
	PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)

#define ARM_PMU_XSCALE_MASK	((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK)

#define XSCALE_PMU_PROBE(_version, _fn) \
	PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn)

#endif /* CONFIG_HW_PERF_EVENTS */

#endif /* __ARM_PMU_H__ */
Commit	Line	Data
0f4f0672 JI	1	/*
	2	* linux/arch/arm/include/asm/pmu.h
	3	*
	4	* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	*/
	11
	12	#ifndef __ARM_PMU_H__
	13	#define __ARM_PMU_H__
	14
0e25a5c9	15	#include <linux/interrupt.h>
0ce47080	16	#include <linux/perf_event.h>
0e25a5c9	17
548a86ca MR	18	#include <asm/cputype.h>
548a86ca MR	19
0e25a5c9 RV	20	/*
	21	* struct arm_pmu_platdata - ARM PMU platform data
	22	*
e0516a64 ML	23	* @handle_irq: an optional handler which will be called from the
	24	* interrupt and passed the address of the low level handler,
	25	* and can be used to implement any platform specific handling
	26	* before or after calling it.
7be2958e JH	27	* @runtime_resume: an optional handler which will be called by the
	28	* runtime PM framework following a call to pm_runtime_get().
	29	* Note that if pm_runtime_get() is called more than once in
	30	* succession this handler will only be called once.
	31	* @runtime_suspend: an optional handler which will be called by the
	32	* runtime PM framework following a call to pm_runtime_put().
	33	* Note that if pm_runtime_get() is called more than once in
	34	* succession this handler will only be called following the
	35	* final call to pm_runtime_put() that actually disables the
	36	* hardware.
0e25a5c9 RV	37	*/
	38	struct arm_pmu_platdata {
	39	irqreturn_t (handle_irq)(int irq, void dev,
	40	irq_handler_t pmu_handler);
7be2958e JH	41	int (runtime_resume)(struct device dev);
7be2958e JH	42	int (runtime_suspend)(struct device dev);
0e25a5c9 RV	43	};
0e25a5c9 RV	44
0ce47080 MR	45	#ifdef CONFIG_HW_PERF_EVENTS
0ce47080 MR	46
ac8674dc MR	47	/*
	48	* The ARMv7 CPU PMU supports up to 32 event counters.
	49	*/
	50	#define ARMPMU_MAX_HWEVENTS 32
	51
	52	#define HW_OP_UNSUPPORTED 0xFFFF
	53	#define C(_x) PERF_COUNT_HW_CACHE_##_x
	54	#define CACHE_OP_UNSUPPORTED 0xFFFF
	55
1113ff98 MR	56	#define PERF_MAP_ALL_UNSUPPORTED \
	57	[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
	58
	59	#define PERF_CACHE_MAP_ALL_UNSUPPORTED \
	60	[0 ... C(MAX) - 1] = { \
	61	[0 ... C(OP_MAX) - 1] = { \
	62	[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
	63	}, \
	64	}
	65
0ce47080 MR	66	/* The events for a given PMU register set. */
	67	struct pmu_hw_events {
	68	/*
	69	* The events that are active on the PMU for the given index.
	70	*/
a4560846	71	struct perf_event *events[ARMPMU_MAX_HWEVENTS];
0ce47080 MR	72
	73	/*
	74	* A 1 bit for an index indicates that the counter is being used for
	75	* an event. A 0 means that the counter can be used.
	76	*/
a4560846	77	DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);
0ce47080 MR	78
	79	/*
	80	* Hardware lock to serialize accesses to PMU registers. Needed for the
	81	* read/modify/write sequences.
	82	*/
	83	raw_spinlock_t pmu_lock;
5ebd9200 MR	84
	85	/*
	86	* When using percpu IRQs, we need a percpu dev_id. Place it here as we
	87	* already have to allocate this struct per cpu.
	88	*/
	89	struct arm_pmu *percpu_pmu;
0ce47080 MR	90	};
	91
	92	struct arm_pmu {
	93	struct pmu pmu;
0ce47080	94	cpumask_t active_irqs;
4295b898	95	char *name;
0ce47080	96	irqreturn_t (handle_irq)(int irq_num, void dev);
ed6f2a52 SK	97	void (enable)(struct perf_event event);
ed6f2a52 SK	98	void (disable)(struct perf_event event);
0ce47080	99	int (get_event_idx)(struct pmu_hw_events hw_events,
ed6f2a52	100	struct perf_event *event);
eab443ef SB	101	void (clear_event_idx)(struct pmu_hw_events hw_events,
eab443ef SB	102	struct perf_event *event);
0ce47080 MR	103	int (set_event_filter)(struct hw_perf_event evt,
0ce47080 MR	104	struct perf_event_attr *attr);
ed6f2a52 SK	105	u32 (read_counter)(struct perf_event event);
	106	void (write_counter)(struct perf_event event, u32 val);
	107	void (start)(struct arm_pmu );
	108	void (stop)(struct arm_pmu );
0ce47080	109	void (reset)(void );
ed6f2a52 SK	110	int (request_irq)(struct arm_pmu , irq_handler_t handler);
ed6f2a52 SK	111	void (free_irq)(struct arm_pmu );
0ce47080 MR	112	int (map_event)(struct perf_event event);
	113	int num_events;
	114	atomic_t active_events;
	115	struct mutex reserve_mutex;
	116	u64 max_period;
	117	struct platform_device *plat_device;
11679250	118	struct pmu_hw_events __percpu *hw_events;
af66abfe	119	struct notifier_block hotplug_nb;
0ce47080 MR	120	};
	121
	122	#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
	123
6dbc0029 WD	124	extern const struct dev_pm_ops armpmu_dev_pm_ops;
6dbc0029 WD	125
0305230a	126	int armpmu_register(struct arm_pmu *armpmu, int type);
0ce47080	127
ed6f2a52	128	u64 armpmu_event_update(struct perf_event *event);
0ce47080	129
ed6f2a52	130	int armpmu_event_set_period(struct perf_event *event);
0ce47080	131
6dbc0029 WD	132	int armpmu_map_event(struct perf_event *event,
	133	const unsigned (*event_map)[PERF_COUNT_HW_MAX],
	134	const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
	135	[PERF_COUNT_HW_CACHE_OP_MAX]
	136	[PERF_COUNT_HW_CACHE_RESULT_MAX],
	137	u32 raw_event_mask);
	138
548a86ca MR	139	struct pmu_probe_info {
	140	unsigned int cpuid;
	141	unsigned int mask;
	142	int (init)(struct arm_pmu );
	143	};
	144
	145	#define PMU_PROBE(_cpuid, _mask, _fn) \
	146	{ \
	147	.cpuid = (_cpuid), \
	148	.mask = (_mask), \
	149	.init = (_fn), \
	150	}
	151
	152	#define ARM_PMU_PROBE(_cpuid, _fn) \
	153	PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)
	154
	155	#define ARM_PMU_XSCALE_MASK ((0xff << 24) \| ARM_CPU_XSCALE_ARCH_MASK)
	156
	157	#define XSCALE_PMU_PROBE(_version, _fn) \
	158	PMU_PROBE(ARM_CPU_IMP_INTEL << 24 \| _version, ARM_PMU_XSCALE_MASK, _fn)
	159
0ce47080 MR	160	#endif /* CONFIG_HW_PERF_EVENTS */
0ce47080 MR	161
0f4f0672	162	#endif /* __ARM_PMU_H__ */