[deliverable/linux.git] / arch / arm / include / asm / processor.h

/*
 *  arch/arm/include/asm/processor.h
 *
 *  Copyright (C) 1995-1999 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ASM_ARM_PROCESSOR_H
#define __ASM_ARM_PROCESSOR_H

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ __label__ _l; _l: &&_l;})

#ifdef __KERNEL__

#include <asm/hw_breakpoint.h>
#include <asm/ptrace.h>
#include <asm/types.h>

#ifdef __KERNEL__
#define STACK_TOP	((current->personality & ADDR_LIMIT_32BIT) ? \
			 TASK_SIZE : TASK_SIZE_26)
#define STACK_TOP_MAX	TASK_SIZE
#endif

struct debug_info {
#ifdef CONFIG_HAVE_HW_BREAKPOINT
	struct perf_event	*hbp[ARM_MAX_HBP_SLOTS];
#endif
};

struct thread_struct {
							/* fault info	  */
	unsigned long		address;
	unsigned long		trap_no;
	unsigned long		error_code;
							/* debugging	  */
	struct debug_info	debug;
};

#define INIT_THREAD  {	}

#ifdef CONFIG_MMU
#define nommu_start_thread(regs) do { } while (0)
#else
#define nommu_start_thread(regs) regs->ARM_r10 = current->mm->start_data
#endif

#define start_thread(regs,pc,sp)					\
({									\
	memset(regs->uregs, 0, sizeof(regs->uregs));			\
	if (current->personality & ADDR_LIMIT_32BIT)			\
		regs->ARM_cpsr = USR_MODE;				\
	else								\
		regs->ARM_cpsr = USR26_MODE;				\
	if (elf_hwcap & HWCAP_THUMB && pc & 1)				\
		regs->ARM_cpsr |= PSR_T_BIT;				\
	regs->ARM_cpsr |= PSR_ENDSTATE;					\
	regs->ARM_pc = pc & ~1;		/* pc */			\
	regs->ARM_sp = sp;		/* sp */			\
	nommu_start_thread(regs);					\
})

/* Forward declaration, a strange C thing */
struct task_struct;

/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);

unsigned long get_wchan(struct task_struct *p);

#if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
#define cpu_relax()			smp_mb()
#else
#define cpu_relax()			barrier()
#endif

#define task_pt_regs(p) \
	((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)

#define KSTK_EIP(tsk)	task_pt_regs(tsk)->ARM_pc
#define KSTK_ESP(tsk)	task_pt_regs(tsk)->ARM_sp

/*
 * Prefetching support - only ARMv5.
 */
#if __LINUX_ARM_ARCH__ >= 5

#define ARCH_HAS_PREFETCH
static inline void prefetch(const void *ptr)
{
	__asm__ __volatile__(
		"pld\t%a0"
		:
		: "p" (ptr)
		: "cc");
}

#define ARCH_HAS_PREFETCHW
#define prefetchw(ptr)	prefetch(ptr)

#define ARCH_HAS_SPINLOCK_PREFETCH
#define spin_lock_prefetch(x) do { } while (0)

#endif

#define HAVE_ARCH_PICK_MMAP_LAYOUT

#endif

#endif /* __ASM_ARM_PROCESSOR_H */
Commit	Line	Data
1da177e4	1	/*
4baa9922	2	* arch/arm/include/asm/processor.h
1da177e4 LT	3	*
	4	* Copyright (C) 1995-1999 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#ifndef __ASM_ARM_PROCESSOR_H
	12	#define __ASM_ARM_PROCESSOR_H
	13
	14	/*
	15	* Default implementation of macro that returns current
	16	* instruction pointer ("program counter").
	17	*/
	18	#define current_text_addr() ({ __label__ _l; _l: &&_l;})
	19
	20	#ifdef __KERNEL__
	21
864232fa	22	#include <asm/hw_breakpoint.h>
1da177e4	23	#include <asm/ptrace.h>
1da177e4 LT	24	#include <asm/types.h>
1da177e4 LT	25
922a70d3	26	#ifdef __KERNEL__
794baba6	27	#define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \
922a70d3 DH	28	TASK_SIZE : TASK_SIZE_26)
	29	#define STACK_TOP_MAX TASK_SIZE
	30	#endif
	31
1da177e4	32	struct debug_info {
864232fa WD	33	#ifdef CONFIG_HAVE_HW_BREAKPOINT
	34	struct perf_event *hbp[ARM_MAX_HBP_SLOTS];
	35	#endif
1da177e4 LT	36	};
	37
	38	struct thread_struct {
	39	/* fault info */
	40	unsigned long address;
	41	unsigned long trap_no;
	42	unsigned long error_code;
	43	/* debugging */
	44	struct debug_info debug;
	45	};
	46
	47	#define INIT_THREAD { }
	48
e72b0475 HC	49	#ifdef CONFIG_MMU
	50	#define nommu_start_thread(regs) do { } while (0)
	51	#else
	52	#define nommu_start_thread(regs) regs->ARM_r10 = current->mm->start_data
	53	#endif
	54
1da177e4 LT	55	#define start_thread(regs,pc,sp) \
1da177e4 LT	56	({ \
59f0cb0f	57	memset(regs->uregs, 0, sizeof(regs->uregs)); \
1da177e4 LT	58	if (current->personality & ADDR_LIMIT_32BIT) \
	59	regs->ARM_cpsr = USR_MODE; \
	60	else \
	61	regs->ARM_cpsr = USR26_MODE; \
	62	if (elf_hwcap & HWCAP_THUMB && pc & 1) \
	63	regs->ARM_cpsr \|= PSR_T_BIT; \
26584853	64	regs->ARM_cpsr \|= PSR_ENDSTATE; \
1da177e4 LT	65	regs->ARM_pc = pc & ~1; /* pc */ \
1da177e4 LT	66	regs->ARM_sp = sp; /* sp */ \
e72b0475	67	nommu_start_thread(regs); \
1da177e4 LT	68	})
	69
	70	/* Forward declaration, a strange C thing */
	71	struct task_struct;
	72
	73	/* Free all resources held by a thread. */
	74	extern void release_thread(struct task_struct *);
	75
1da177e4 LT	76	unsigned long get_wchan(struct task_struct *p);
1da177e4 LT	77
5dab26af	78	#if __LINUX_ARM_ARCH__ == 6 \|\| defined(CONFIG_ARM_ERRATA_754327)
534be1d5 WD	79	#define cpu_relax() smp_mb()
534be1d5 WD	80	#else
1da177e4	81	#define cpu_relax() barrier()
534be1d5	82	#endif
1da177e4	83
815d5ec8	84	#define task_pt_regs(p) \
32d39a93	85	((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
815d5ec8 AV	86
	87	#define KSTK_EIP(tsk) task_pt_regs(tsk)->ARM_pc
	88	#define KSTK_ESP(tsk) task_pt_regs(tsk)->ARM_sp
1da177e4 LT	89
	90	/*
	91	* Prefetching support - only ARMv5.
	92	*/
	93	#if __LINUX_ARM_ARCH__ >= 5
	94
	95	#define ARCH_HAS_PREFETCH
02828845 NP	96	static inline void prefetch(const void *ptr)
	97	{
	98	__asm__ __volatile__(
16f719de	99	"pld\t%a0"
02828845	100	:
16f719de	101	: "p" (ptr)
02828845 NP	102	: "cc");
02828845 NP	103	}
1da177e4 LT	104
	105	#define ARCH_HAS_PREFETCHW
	106	#define prefetchw(ptr) prefetch(ptr)
	107
	108	#define ARCH_HAS_SPINLOCK_PREFETCH
	109	#define spin_lock_prefetch(x) do { } while (0)
	110
	111	#endif
	112
7dbaa466 RH	113	#define HAVE_ARCH_PICK_MMAP_LAYOUT
7dbaa466 RH	114
1da177e4 LT	115	#endif
	116
	117	#endif /* __ASM_ARM_PROCESSOR_H */