Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
4baa9922 | 2 | * arch/arm/include/asm/ptrace.h |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1996-2003 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #ifndef __ASM_ARM_PTRACE_H | |
11 | #define __ASM_ARM_PTRACE_H | |
12 | ||
cb8db5d4 | 13 | #include <uapi/asm/ptrace.h> |
68b7f715 | 14 | |
1da177e4 | 15 | #ifndef __ASSEMBLY__ |
092a4e95 JI |
16 | struct pt_regs { |
17 | unsigned long uregs[18]; | |
18 | }; | |
1da177e4 LT |
19 | |
20 | #define user_mode(regs) \ | |
21 | (((regs)->ARM_cpsr & 0xf) == 0) | |
22 | ||
23 | #ifdef CONFIG_ARM_THUMB | |
24 | #define thumb_mode(regs) \ | |
25 | (((regs)->ARM_cpsr & PSR_T_BIT)) | |
26 | #else | |
27 | #define thumb_mode(regs) (0) | |
28 | #endif | |
29 | ||
909d6c6c GD |
30 | #define isa_mode(regs) \ |
31 | ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \ | |
32 | (((regs)->ARM_cpsr & PSR_T_BIT) >> 5)) | |
33 | ||
1da177e4 LT |
34 | #define processor_mode(regs) \ |
35 | ((regs)->ARM_cpsr & MODE_MASK) | |
36 | ||
37 | #define interrupts_enabled(regs) \ | |
38 | (!((regs)->ARM_cpsr & PSR_I_BIT)) | |
39 | ||
40 | #define fast_interrupts_enabled(regs) \ | |
41 | (!((regs)->ARM_cpsr & PSR_F_BIT)) | |
42 | ||
1da177e4 LT |
43 | /* Are the current registers suitable for user mode? |
44 | * (used to maintain security in signal handlers) | |
45 | */ | |
46 | static inline int valid_user_regs(struct pt_regs *regs) | |
47 | { | |
55bdd694 | 48 | #ifndef CONFIG_CPU_V7M |
41e2e8fd RK |
49 | unsigned long mode = regs->ARM_cpsr & MODE_MASK; |
50 | ||
51 | /* | |
52 | * Always clear the F (FIQ) and A (delayed abort) bits | |
53 | */ | |
54 | regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); | |
55 | ||
56 | if ((regs->ARM_cpsr & PSR_I_BIT) == 0) { | |
57 | if (mode == USR_MODE) | |
58 | return 1; | |
59 | if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE) | |
60 | return 1; | |
d1cbbd6b | 61 | } |
1da177e4 LT |
62 | |
63 | /* | |
64 | * Force CPSR to something logical... | |
65 | */ | |
41e2e8fd | 66 | regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT; |
d1cbbd6b CM |
67 | if (!(elf_hwcap & HWCAP_26BIT)) |
68 | regs->ARM_cpsr |= USR_MODE; | |
1da177e4 LT |
69 | |
70 | return 0; | |
55bdd694 CM |
71 | #else /* ifndef CONFIG_CPU_V7M */ |
72 | return 1; | |
73 | #endif | |
1da177e4 LT |
74 | } |
75 | ||
29ef73b7 NH |
76 | static inline long regs_return_value(struct pt_regs *regs) |
77 | { | |
78 | return regs->ARM_r0; | |
79 | } | |
80 | ||
1de765c1 | 81 | #define instruction_pointer(regs) (regs)->ARM_pc |
1da177e4 LT |
82 | |
83 | #ifdef CONFIG_SMP | |
84 | extern unsigned long profile_pc(struct pt_regs *regs); | |
85 | #else | |
86 | #define profile_pc(regs) instruction_pointer(regs) | |
87 | #endif | |
88 | ||
652a12ef | 89 | #define predicate(x) ((x) & 0xf0000000) |
1da177e4 | 90 | #define PREDICATE_ALWAYS 0xe0000000 |
f22ab814 | 91 | |
592201a9 JM |
92 | /* |
93 | * True if instr is a 32-bit thumb instruction. This works if instr | |
94 | * is the first or only half-word of a thumb instruction. It also works | |
95 | * when instr holds all 32-bits of a wide thumb instruction if stored | |
96 | * in the form (first_half<<16)|(second_half) | |
97 | */ | |
98 | #define is_wide_instruction(instr) ((unsigned)(instr) >= 0xe800) | |
99 | ||
e513f8bf WD |
100 | /* |
101 | * kprobe-based event tracer support | |
102 | */ | |
103 | #include <linux/stddef.h> | |
104 | #include <linux/types.h> | |
105 | #define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0)) | |
106 | ||
107 | extern int regs_query_register_offset(const char *name); | |
108 | extern const char *regs_query_register_name(unsigned int offset); | |
109 | extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr); | |
110 | extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, | |
111 | unsigned int n); | |
112 | ||
113 | /** | |
114 | * regs_get_register() - get register value from its offset | |
115 | * @regs: pt_regs from which register value is gotten | |
116 | * @offset: offset number of the register. | |
117 | * | |
118 | * regs_get_register returns the value of a register whose offset from @regs. | |
119 | * The @offset is the offset of the register in struct pt_regs. | |
120 | * If @offset is bigger than MAX_REG_OFFSET, this returns 0. | |
121 | */ | |
122 | static inline unsigned long regs_get_register(struct pt_regs *regs, | |
123 | unsigned int offset) | |
124 | { | |
125 | if (unlikely(offset > MAX_REG_OFFSET)) | |
126 | return 0; | |
127 | return *(unsigned long *)((unsigned long)regs + offset); | |
128 | } | |
129 | ||
130 | /* Valid only for Kernel mode traps. */ | |
131 | static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) | |
132 | { | |
133 | return regs->ARM_sp; | |
134 | } | |
135 | ||
0693bf68 WF |
136 | static inline unsigned long user_stack_pointer(struct pt_regs *regs) |
137 | { | |
138 | return regs->ARM_sp; | |
139 | } | |
140 | ||
bfd170d5 AV |
141 | #define current_pt_regs(void) ({ \ |
142 | register unsigned long sp asm ("sp"); \ | |
143 | (struct pt_regs *)((sp | (THREAD_SIZE - 1)) - 7) - 1; \ | |
144 | }) | |
145 | ||
1da177e4 | 146 | #endif /* __ASSEMBLY__ */ |
1da177e4 | 147 | #endif |