Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/bios32.c | |
3 | * | |
4 | * PCI bios-type initialisation for PCI machines | |
5 | * | |
6 | * Bits taken from various places. | |
7 | */ | |
ecea4ab6 | 8 | #include <linux/export.h> |
1da177e4 LT |
9 | #include <linux/kernel.h> |
10 | #include <linux/pci.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/init.h> | |
fced80c7 | 13 | #include <linux/io.h> |
1da177e4 | 14 | |
1da177e4 | 15 | #include <asm/mach-types.h> |
c2794437 | 16 | #include <asm/mach/map.h> |
1da177e4 LT |
17 | #include <asm/mach/pci.h> |
18 | ||
19 | static int debug_pci; | |
1da177e4 | 20 | |
49dcc01a YW |
21 | #ifdef CONFIG_PCI_MSI |
22 | struct msi_controller *pcibios_msi_controller(struct pci_dev *dev) | |
23 | { | |
24 | struct pci_sys_data *sysdata = dev->bus->sysdata; | |
25 | ||
26 | return sysdata->msi_ctrl; | |
27 | } | |
28 | #endif | |
29 | ||
1da177e4 | 30 | /* |
5ee09efe | 31 | * We can't use pci_get_device() here since we are |
1da177e4 LT |
32 | * called from interrupt context. |
33 | */ | |
34 | static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn) | |
35 | { | |
36 | struct pci_dev *dev; | |
37 | ||
38 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
39 | u16 status; | |
40 | ||
41 | /* | |
42 | * ignore host bridge - we handle | |
43 | * that separately | |
44 | */ | |
45 | if (dev->bus->number == 0 && dev->devfn == 0) | |
46 | continue; | |
47 | ||
48 | pci_read_config_word(dev, PCI_STATUS, &status); | |
49 | if (status == 0xffff) | |
50 | continue; | |
51 | ||
52 | if ((status & status_mask) == 0) | |
53 | continue; | |
54 | ||
55 | /* clear the status errors */ | |
56 | pci_write_config_word(dev, PCI_STATUS, status & status_mask); | |
57 | ||
58 | if (warn) | |
59 | printk("(%s: %04X) ", pci_name(dev), status); | |
60 | } | |
61 | ||
62 | list_for_each_entry(dev, &bus->devices, bus_list) | |
63 | if (dev->subordinate) | |
64 | pcibios_bus_report_status(dev->subordinate, status_mask, warn); | |
65 | } | |
66 | ||
67 | void pcibios_report_status(u_int status_mask, int warn) | |
68 | { | |
f0197e0c | 69 | struct pci_bus *bus; |
1da177e4 | 70 | |
f0197e0c | 71 | list_for_each_entry(bus, &pci_root_buses, node) |
1da177e4 | 72 | pcibios_bus_report_status(bus, status_mask, warn); |
1da177e4 LT |
73 | } |
74 | ||
75 | /* | |
76 | * We don't use this to fix the device, but initialisation of it. | |
77 | * It's not the correct use for this, but it works. | |
78 | * Note that the arbiter/ISA bridge appears to be buggy, specifically in | |
79 | * the following area: | |
80 | * 1. park on CPU | |
81 | * 2. ISA bridge ping-pong | |
82 | * 3. ISA bridge master handling of target RETRY | |
83 | * | |
84 | * Bug 3 is responsible for the sound DMA grinding to a halt. We now | |
85 | * live with bug 2. | |
86 | */ | |
351a102d | 87 | static void pci_fixup_83c553(struct pci_dev *dev) |
1da177e4 LT |
88 | { |
89 | /* | |
90 | * Set memory region to start at address 0, and enable IO | |
91 | */ | |
92 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
93 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO); | |
94 | ||
95 | dev->resource[0].end -= dev->resource[0].start; | |
96 | dev->resource[0].start = 0; | |
97 | ||
98 | /* | |
99 | * All memory requests from ISA to be channelled to PCI | |
100 | */ | |
101 | pci_write_config_byte(dev, 0x48, 0xff); | |
102 | ||
103 | /* | |
104 | * Enable ping-pong on bus master to ISA bridge transactions. | |
105 | * This improves the sound DMA substantially. The fixed | |
106 | * priority arbiter also helps (see below). | |
107 | */ | |
108 | pci_write_config_byte(dev, 0x42, 0x01); | |
109 | ||
110 | /* | |
111 | * Enable PCI retry | |
112 | */ | |
113 | pci_write_config_byte(dev, 0x40, 0x22); | |
114 | ||
115 | /* | |
116 | * We used to set the arbiter to "park on last master" (bit | |
117 | * 1 set), but unfortunately the CyberPro does not park the | |
118 | * bus. We must therefore park on CPU. Unfortunately, this | |
119 | * may trigger yet another bug in the 553. | |
120 | */ | |
121 | pci_write_config_byte(dev, 0x83, 0x02); | |
122 | ||
123 | /* | |
124 | * Make the ISA DMA request lowest priority, and disable | |
125 | * rotating priorities completely. | |
126 | */ | |
127 | pci_write_config_byte(dev, 0x80, 0x11); | |
128 | pci_write_config_byte(dev, 0x81, 0x00); | |
129 | ||
130 | /* | |
131 | * Route INTA input to IRQ 11, and set IRQ11 to be level | |
132 | * sensitive. | |
133 | */ | |
134 | pci_write_config_word(dev, 0x44, 0xb000); | |
135 | outb(0x08, 0x4d1); | |
136 | } | |
137 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553); | |
138 | ||
351a102d | 139 | static void pci_fixup_unassign(struct pci_dev *dev) |
1da177e4 LT |
140 | { |
141 | dev->resource[0].end -= dev->resource[0].start; | |
142 | dev->resource[0].start = 0; | |
143 | } | |
144 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign); | |
145 | ||
146 | /* | |
147 | * Prevent the PCI layer from seeing the resources allocated to this device | |
148 | * if it is the host bridge by marking it as such. These resources are of | |
149 | * no consequence to the PCI layer (they are handled elsewhere). | |
150 | */ | |
351a102d | 151 | static void pci_fixup_dec21285(struct pci_dev *dev) |
1da177e4 LT |
152 | { |
153 | int i; | |
154 | ||
155 | if (dev->devfn == 0) { | |
156 | dev->class &= 0xff; | |
157 | dev->class |= PCI_CLASS_BRIDGE_HOST << 8; | |
158 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
159 | dev->resource[i].start = 0; | |
160 | dev->resource[i].end = 0; | |
161 | dev->resource[i].flags = 0; | |
162 | } | |
163 | } | |
164 | } | |
165 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285); | |
166 | ||
1da177e4 LT |
167 | /* |
168 | * PCI IDE controllers use non-standard I/O port decoding, respect it. | |
169 | */ | |
351a102d | 170 | static void pci_fixup_ide_bases(struct pci_dev *dev) |
1da177e4 LT |
171 | { |
172 | struct resource *r; | |
173 | int i; | |
174 | ||
175 | if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) | |
176 | return; | |
177 | ||
178 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
179 | r = dev->resource + i; | |
180 | if ((r->start & ~0x80) == 0x374) { | |
181 | r->start |= 2; | |
182 | r->end = r->start; | |
183 | } | |
184 | } | |
185 | } | |
186 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); | |
187 | ||
188 | /* | |
189 | * Put the DEC21142 to sleep | |
190 | */ | |
351a102d | 191 | static void pci_fixup_dec21142(struct pci_dev *dev) |
1da177e4 LT |
192 | { |
193 | pci_write_config_dword(dev, 0x40, 0x80000000); | |
194 | } | |
195 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142); | |
196 | ||
197 | /* | |
198 | * The CY82C693 needs some rather major fixups to ensure that it does | |
199 | * the right thing. Idea from the Alpha people, with a few additions. | |
200 | * | |
201 | * We ensure that the IDE base registers are set to 1f0/3f4 for the | |
202 | * primary bus, and 170/374 for the secondary bus. Also, hide them | |
203 | * from the PCI subsystem view as well so we won't try to perform | |
204 | * our own auto-configuration on them. | |
205 | * | |
206 | * In addition, we ensure that the PCI IDE interrupts are routed to | |
207 | * IRQ 14 and IRQ 15 respectively. | |
208 | * | |
209 | * The above gets us to a point where the IDE on this device is | |
210 | * functional. However, The CY82C693U _does not work_ in bus | |
211 | * master mode without locking the PCI bus solid. | |
212 | */ | |
351a102d | 213 | static void pci_fixup_cy82c693(struct pci_dev *dev) |
1da177e4 LT |
214 | { |
215 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
216 | u32 base0, base1; | |
217 | ||
218 | if (dev->class & 0x80) { /* primary */ | |
219 | base0 = 0x1f0; | |
220 | base1 = 0x3f4; | |
221 | } else { /* secondary */ | |
222 | base0 = 0x170; | |
223 | base1 = 0x374; | |
224 | } | |
225 | ||
226 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, | |
227 | base0 | PCI_BASE_ADDRESS_SPACE_IO); | |
228 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, | |
229 | base1 | PCI_BASE_ADDRESS_SPACE_IO); | |
230 | ||
231 | dev->resource[0].start = 0; | |
232 | dev->resource[0].end = 0; | |
233 | dev->resource[0].flags = 0; | |
234 | ||
235 | dev->resource[1].start = 0; | |
236 | dev->resource[1].end = 0; | |
237 | dev->resource[1].flags = 0; | |
238 | } else if (PCI_FUNC(dev->devfn) == 0) { | |
239 | /* | |
240 | * Setup IDE IRQ routing. | |
241 | */ | |
242 | pci_write_config_byte(dev, 0x4b, 14); | |
243 | pci_write_config_byte(dev, 0x4c, 15); | |
244 | ||
245 | /* | |
246 | * Disable FREQACK handshake, enable USB. | |
247 | */ | |
248 | pci_write_config_byte(dev, 0x4d, 0x41); | |
249 | ||
250 | /* | |
251 | * Enable PCI retry, and PCI post-write buffer. | |
252 | */ | |
253 | pci_write_config_byte(dev, 0x44, 0x17); | |
254 | ||
255 | /* | |
256 | * Enable ISA master and DMA post write buffering. | |
257 | */ | |
258 | pci_write_config_byte(dev, 0x45, 0x03); | |
259 | } | |
260 | } | |
261 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693); | |
262 | ||
351a102d | 263 | static void pci_fixup_it8152(struct pci_dev *dev) |
a8fc0789 MR |
264 | { |
265 | int i; | |
266 | /* fixup for ITE 8152 devices */ | |
267 | /* FIXME: add defines for class 0x68000 and 0x80103 */ | |
268 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST || | |
269 | dev->class == 0x68000 || | |
270 | dev->class == 0x80103) { | |
271 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
272 | dev->resource[i].start = 0; | |
273 | dev->resource[i].end = 0; | |
274 | dev->resource[i].flags = 0; | |
275 | } | |
276 | } | |
277 | } | |
278 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152); | |
279 | ||
1da177e4 LT |
280 | /* |
281 | * If the bus contains any of these devices, then we must not turn on | |
282 | * parity checking of any kind. Currently this is CyberPro 20x0 only. | |
283 | */ | |
284 | static inline int pdev_bad_for_parity(struct pci_dev *dev) | |
285 | { | |
a8fc0789 MR |
286 | return ((dev->vendor == PCI_VENDOR_ID_INTERG && |
287 | (dev->device == PCI_DEVICE_ID_INTERG_2000 || | |
288 | dev->device == PCI_DEVICE_ID_INTERG_2010)) || | |
289 | (dev->vendor == PCI_VENDOR_ID_ITE && | |
290 | dev->device == PCI_DEVICE_ID_ITE_8152)); | |
291 | ||
1da177e4 LT |
292 | } |
293 | ||
1da177e4 LT |
294 | /* |
295 | * pcibios_fixup_bus - Called after each bus is probed, | |
296 | * but before its children are examined. | |
297 | */ | |
46edfc54 | 298 | void pcibios_fixup_bus(struct pci_bus *bus) |
1da177e4 | 299 | { |
1da177e4 LT |
300 | struct pci_dev *dev; |
301 | u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK; | |
302 | ||
1da177e4 LT |
303 | /* |
304 | * Walk the devices on this bus, working out what we can | |
305 | * and can't support. | |
306 | */ | |
307 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
308 | u16 status; | |
309 | ||
1da177e4 LT |
310 | pci_read_config_word(dev, PCI_STATUS, &status); |
311 | ||
312 | /* | |
313 | * If any device on this bus does not support fast back | |
314 | * to back transfers, then the bus as a whole is not able | |
315 | * to support them. Having fast back to back transfers | |
316 | * on saves us one PCI cycle per transaction. | |
317 | */ | |
318 | if (!(status & PCI_STATUS_FAST_BACK)) | |
319 | features &= ~PCI_COMMAND_FAST_BACK; | |
320 | ||
321 | if (pdev_bad_for_parity(dev)) | |
322 | features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); | |
323 | ||
324 | switch (dev->class >> 8) { | |
1da177e4 LT |
325 | case PCI_CLASS_BRIDGE_PCI: |
326 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status); | |
327 | status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT; | |
328 | status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK); | |
329 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status); | |
330 | break; | |
331 | ||
332 | case PCI_CLASS_BRIDGE_CARDBUS: | |
333 | pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status); | |
334 | status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT; | |
335 | pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status); | |
336 | break; | |
337 | } | |
338 | } | |
339 | ||
340 | /* | |
341 | * Now walk the devices again, this time setting them up. | |
342 | */ | |
343 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
344 | u16 cmd; | |
345 | ||
346 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
347 | cmd |= features; | |
348 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
349 | ||
350 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, | |
351 | L1_CACHE_BYTES >> 2); | |
352 | } | |
353 | ||
354 | /* | |
355 | * Propagate the flags to the PCI bridge. | |
356 | */ | |
357 | if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
358 | if (features & PCI_COMMAND_FAST_BACK) | |
359 | bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK; | |
360 | if (features & PCI_COMMAND_PARITY) | |
361 | bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY; | |
362 | } | |
363 | ||
364 | /* | |
365 | * Report what we did for this bus | |
366 | */ | |
4ed89f22 | 367 | pr_info("PCI: bus%d: Fast back to back transfers %sabled\n", |
1da177e4 LT |
368 | bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis"); |
369 | } | |
b214bea5 | 370 | EXPORT_SYMBOL(pcibios_fixup_bus); |
1da177e4 | 371 | |
1da177e4 | 372 | /* |
daeb4c0c RK |
373 | * Swizzle the device pin each time we cross a bridge. If a platform does |
374 | * not provide a swizzle function, we perform the standard PCI swizzling. | |
375 | * | |
376 | * The default swizzling walks up the bus tree one level at a time, applying | |
377 | * the standard swizzle function at each step, stopping when it finds the PCI | |
378 | * root bus. This will return the slot number of the bridge device on the | |
379 | * root bus and the interrupt pin on that device which should correspond | |
380 | * with the downstream device interrupt. | |
381 | * | |
382 | * Platforms may override this, in which case the slot and pin returned | |
383 | * depend entirely on the platform code. However, please note that the | |
384 | * PCI standard swizzle is implemented on plug-in cards and Cardbus based | |
385 | * PCI extenders, so it can not be ignored. | |
1da177e4 | 386 | */ |
351a102d | 387 | static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin) |
1da177e4 LT |
388 | { |
389 | struct pci_sys_data *sys = dev->sysdata; | |
daeb4c0c | 390 | int slot, oldpin = *pin; |
1da177e4 LT |
391 | |
392 | if (sys->swizzle) | |
393 | slot = sys->swizzle(dev, pin); | |
daeb4c0c RK |
394 | else |
395 | slot = pci_common_swizzle(dev, pin); | |
1da177e4 LT |
396 | |
397 | if (debug_pci) | |
398 | printk("PCI: %s swizzling pin %d => pin %d slot %d\n", | |
399 | pci_name(dev), oldpin, *pin, slot); | |
400 | ||
401 | return slot; | |
402 | } | |
403 | ||
404 | /* | |
405 | * Map a slot/pin to an IRQ. | |
406 | */ | |
d5341942 | 407 | static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
1da177e4 LT |
408 | { |
409 | struct pci_sys_data *sys = dev->sysdata; | |
410 | int irq = -1; | |
411 | ||
412 | if (sys->map_irq) | |
413 | irq = sys->map_irq(dev, slot, pin); | |
414 | ||
415 | if (debug_pci) | |
416 | printk("PCI: %s mapping slot %d pin %d => irq %d\n", | |
417 | pci_name(dev), slot, pin, irq); | |
418 | ||
419 | return irq; | |
420 | } | |
421 | ||
276fd3c5 | 422 | static int pcibios_init_resources(int busnr, struct pci_sys_data *sys) |
3c5d1699 RH |
423 | { |
424 | int ret; | |
14d76b68 | 425 | struct resource_entry *window; |
3c5d1699 RH |
426 | |
427 | if (list_empty(&sys->resources)) { | |
428 | pci_add_resource_offset(&sys->resources, | |
429 | &iomem_resource, sys->mem_offset); | |
430 | } | |
431 | ||
14d76b68 | 432 | resource_list_for_each_entry(window, &sys->resources) |
3c5d1699 RH |
433 | if (resource_type(window->res) == IORESOURCE_IO) |
434 | return 0; | |
3c5d1699 RH |
435 | |
436 | sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io; | |
437 | sys->io_res.end = (busnr + 1) * SZ_64K - 1; | |
438 | sys->io_res.flags = IORESOURCE_IO; | |
439 | sys->io_res.name = sys->io_res_name; | |
440 | sprintf(sys->io_res_name, "PCI%d I/O", busnr); | |
441 | ||
442 | ret = request_resource(&ioport_resource, &sys->io_res); | |
443 | if (ret) { | |
444 | pr_err("PCI: unable to allocate I/O port region (%d)\n", ret); | |
445 | return ret; | |
446 | } | |
447 | pci_add_resource_offset(&sys->resources, &sys->io_res, | |
448 | sys->io_offset); | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
14d86e72 LW |
453 | static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, |
454 | struct list_head *head) | |
1da177e4 LT |
455 | { |
456 | struct pci_sys_data *sys = NULL; | |
457 | int ret; | |
458 | int nr, busnr; | |
459 | ||
460 | for (nr = busnr = 0; nr < hw->nr_controllers; nr++) { | |
d2a02b93 | 461 | sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL); |
ada8b675 LP |
462 | if (WARN(!sys, "PCI: unable to allocate sys data!")) |
463 | break; | |
1da177e4 | 464 | |
49dcc01a YW |
465 | #ifdef CONFIG_PCI_MSI |
466 | sys->msi_ctrl = hw->msi_ctrl; | |
52882173 | 467 | #endif |
1da177e4 LT |
468 | sys->busnr = busnr; |
469 | sys->swizzle = hw->swizzle; | |
470 | sys->map_irq = hw->map_irq; | |
029baf14 | 471 | sys->align_resource = hw->align_resource; |
37d15909 | 472 | INIT_LIST_HEAD(&sys->resources); |
1da177e4 | 473 | |
352af7d4 TR |
474 | if (hw->private_data) |
475 | sys->private_data = hw->private_data[nr]; | |
476 | ||
1da177e4 LT |
477 | ret = hw->setup(nr, sys); |
478 | ||
479 | if (ret > 0) { | |
3c5d1699 RH |
480 | ret = pcibios_init_resources(nr, sys); |
481 | if (ret) { | |
482 | kfree(sys); | |
483 | break; | |
37d15909 BH |
484 | } |
485 | ||
c23bfc38 RK |
486 | if (hw->scan) |
487 | sys->bus = hw->scan(nr, sys); | |
488 | else | |
14d86e72 | 489 | sys->bus = pci_scan_root_bus(parent, sys->busnr, |
c23bfc38 | 490 | hw->ops, sys, &sys->resources); |
1da177e4 | 491 | |
ada8b675 LP |
492 | if (WARN(!sys->bus, "PCI: unable to scan bus!")) { |
493 | kfree(sys); | |
494 | break; | |
495 | } | |
1da177e4 | 496 | |
b918c62e | 497 | busnr = sys->bus->busn_res.end + 1; |
1da177e4 | 498 | |
90cf2418 | 499 | list_add(&sys->node, head); |
1da177e4 LT |
500 | } else { |
501 | kfree(sys); | |
502 | if (ret < 0) | |
503 | break; | |
504 | } | |
505 | } | |
506 | } | |
507 | ||
14d86e72 | 508 | void pci_common_init_dev(struct device *parent, struct hw_pci *hw) |
1da177e4 LT |
509 | { |
510 | struct pci_sys_data *sys; | |
90cf2418 | 511 | LIST_HEAD(head); |
1da177e4 | 512 | |
6696cbc3 | 513 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); |
1da177e4 LT |
514 | if (hw->preinit) |
515 | hw->preinit(); | |
14d86e72 | 516 | pcibios_init_hw(parent, hw, &head); |
1da177e4 LT |
517 | if (hw->postinit) |
518 | hw->postinit(); | |
519 | ||
520 | pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq); | |
521 | ||
90cf2418 | 522 | list_for_each_entry(sys, &head, node) { |
1da177e4 LT |
523 | struct pci_bus *bus = sys->bus; |
524 | ||
a4fab044 | 525 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
808b27a5 MK |
526 | struct pci_bus *child; |
527 | ||
1da177e4 LT |
528 | /* |
529 | * Size the bridge windows. | |
530 | */ | |
531 | pci_bus_size_bridges(bus); | |
532 | ||
533 | /* | |
534 | * Assign resources. | |
535 | */ | |
536 | pci_bus_assign_resources(bus); | |
1da177e4 | 537 | |
808b27a5 MK |
538 | list_for_each_entry(child, &bus->children, node) |
539 | pcie_bus_configure_settings(child); | |
540 | } | |
1da177e4 LT |
541 | /* |
542 | * Tell drivers about devices found. | |
543 | */ | |
544 | pci_bus_add_devices(bus); | |
545 | } | |
546 | } | |
547 | ||
168c8619 MS |
548 | #ifndef CONFIG_PCI_HOST_ITE8152 |
549 | void pcibios_set_master(struct pci_dev *dev) | |
550 | { | |
551 | /* No special bus mastering setup handling */ | |
552 | } | |
553 | #endif | |
554 | ||
1da177e4 LT |
555 | char * __init pcibios_setup(char *str) |
556 | { | |
557 | if (!strcmp(str, "debug")) { | |
558 | debug_pci = 1; | |
559 | return NULL; | |
560 | } else if (!strcmp(str, "firmware")) { | |
a4fab044 | 561 | pci_add_flags(PCI_PROBE_ONLY); |
1da177e4 LT |
562 | return NULL; |
563 | } | |
564 | return str; | |
565 | } | |
566 | ||
567 | /* | |
568 | * From arch/i386/kernel/pci-i386.c: | |
569 | * | |
570 | * We need to avoid collisions with `mirrored' VGA ports | |
571 | * and other strange ISA hardware, so we always want the | |
572 | * addresses to be allocated in the 0x000-0x0ff region | |
573 | * modulo 0x400. | |
574 | * | |
575 | * Why? Because some silly external IO cards only decode | |
576 | * the low 10 bits of the IO address. The 0x00-0xff region | |
577 | * is reserved for motherboard devices that decode all 16 | |
578 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
579 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
580 | * which might be mirrored at 0x0100-0x03ff.. | |
581 | */ | |
3b7a17fc | 582 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
b26b2d49 | 583 | resource_size_t size, resource_size_t align) |
1da177e4 | 584 | { |
029baf14 TP |
585 | struct pci_dev *dev = data; |
586 | struct pci_sys_data *sys = dev->sysdata; | |
e31dd6e4 | 587 | resource_size_t start = res->start; |
1da177e4 LT |
588 | |
589 | if (res->flags & IORESOURCE_IO && start & 0x300) | |
590 | start = (start + 0x3ff) & ~0x3ff; | |
591 | ||
b26b2d49 DB |
592 | start = (start + align - 1) & ~(align - 1); |
593 | ||
029baf14 TP |
594 | if (sys->align_resource) |
595 | return sys->align_resource(dev, res, start, size, align); | |
596 | ||
b26b2d49 | 597 | return start; |
1da177e4 LT |
598 | } |
599 | ||
600 | /** | |
601 | * pcibios_enable_device - Enable I/O and memory. | |
602 | * @dev: PCI device to be enabled | |
603 | */ | |
604 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
605 | { | |
27e8efdb WD |
606 | if (pci_has_flag(PCI_PROBE_ONLY)) |
607 | return 0; | |
1da177e4 | 608 | |
27e8efdb | 609 | return pci_enable_resources(dev, mask); |
1da177e4 LT |
610 | } |
611 | ||
612 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
613 | enum pci_mmap_state mmap_state, int write_combine) | |
614 | { | |
415ae101 | 615 | if (mmap_state == pci_mmap_io) |
1da177e4 | 616 | return -EINVAL; |
1da177e4 LT |
617 | |
618 | /* | |
619 | * Mark this as IO | |
620 | */ | |
1da177e4 LT |
621 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
622 | ||
415ae101 | 623 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
1da177e4 LT |
624 | vma->vm_end - vma->vm_start, |
625 | vma->vm_page_prot)) | |
626 | return -EAGAIN; | |
627 | ||
628 | return 0; | |
629 | } | |
c2794437 RH |
630 | |
631 | void __init pci_map_io_early(unsigned long pfn) | |
632 | { | |
633 | struct map_desc pci_io_desc = { | |
634 | .virtual = PCI_IO_VIRT_BASE, | |
635 | .type = MT_DEVICE, | |
636 | .length = SZ_64K, | |
637 | }; | |
638 | ||
639 | pci_io_desc.pfn = pfn; | |
640 | iotable_init(&pci_io_desc, 1); | |
641 | } |