Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
70b6f2b4 NP |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
15 | * that causes it to save wrong values... Be aware! | |
1da177e4 | 16 | */ |
1da177e4 | 17 | |
9b9cf81a PG |
18 | #include <linux/init.h> |
19 | ||
6f6f6a70 | 20 | #include <asm/assembler.h> |
f09b9979 | 21 | #include <asm/memory.h> |
753790e7 RK |
22 | #include <asm/glue-df.h> |
23 | #include <asm/glue-pf.h> | |
1da177e4 | 24 | #include <asm/vfpmacros.h> |
243c8654 | 25 | #ifndef CONFIG_MULTI_IRQ_HANDLER |
a09e64fb | 26 | #include <mach/entry-macro.S> |
243c8654 | 27 | #endif |
d6551e88 | 28 | #include <asm/thread_notify.h> |
c4c5716e | 29 | #include <asm/unwind.h> |
cc20d429 | 30 | #include <asm/unistd.h> |
f159f4ed | 31 | #include <asm/tls.h> |
9f97da78 | 32 | #include <asm/system_info.h> |
1da177e4 LT |
33 | |
34 | #include "entry-header.S" | |
cd544ce7 | 35 | #include <asm/entry-macro-multi.S> |
a0266c21 | 36 | #include <asm/probes.h> |
1da177e4 | 37 | |
187a51ad | 38 | /* |
d9600c99 | 39 | * Interrupt handling. |
187a51ad RK |
40 | */ |
41 | .macro irq_handler | |
52108641 | 42 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
d9600c99 | 43 | ldr r1, =handle_arch_irq |
52108641 | 44 | mov r0, sp |
14327c66 | 45 | badr lr, 9997f |
abeb24ae MZ |
46 | ldr pc, [r1] |
47 | #else | |
cd544ce7 | 48 | arch_irq_handler_default |
abeb24ae | 49 | #endif |
f00ec48f | 50 | 9997: |
187a51ad RK |
51 | .endm |
52 | ||
ac8b9c1c | 53 | .macro pabt_helper |
8dfe7ac9 | 54 | @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 |
ac8b9c1c | 55 | #ifdef MULTI_PABORT |
0402bece | 56 | ldr ip, .LCprocfns |
ac8b9c1c | 57 | mov lr, pc |
0402bece | 58 | ldr pc, [ip, #PROCESSOR_PABT_FUNC] |
ac8b9c1c RK |
59 | #else |
60 | bl CPU_PABORT_HANDLER | |
61 | #endif | |
62 | .endm | |
63 | ||
64 | .macro dabt_helper | |
65 | ||
66 | @ | |
67 | @ Call the processor-specific abort handler: | |
68 | @ | |
da740472 | 69 | @ r2 - pt_regs |
3e287bec RK |
70 | @ r4 - aborted context pc |
71 | @ r5 - aborted context psr | |
ac8b9c1c RK |
72 | @ |
73 | @ The abort handler must return the aborted address in r0, and | |
74 | @ the fault status register in r1. r9 must be preserved. | |
75 | @ | |
76 | #ifdef MULTI_DABORT | |
0402bece | 77 | ldr ip, .LCprocfns |
ac8b9c1c | 78 | mov lr, pc |
0402bece | 79 | ldr pc, [ip, #PROCESSOR_DABT_FUNC] |
ac8b9c1c RK |
80 | #else |
81 | bl CPU_DABORT_HANDLER | |
82 | #endif | |
83 | .endm | |
84 | ||
785d3cd2 NP |
85 | #ifdef CONFIG_KPROBES |
86 | .section .kprobes.text,"ax",%progbits | |
87 | #else | |
88 | .text | |
89 | #endif | |
90 | ||
1da177e4 LT |
91 | /* |
92 | * Invalid mode handlers | |
93 | */ | |
ccea7a19 RK |
94 | .macro inv_entry, reason |
95 | sub sp, sp, #S_FRAME_SIZE | |
b86040a5 CM |
96 | ARM( stmib sp, {r1 - lr} ) |
97 | THUMB( stmia sp, {r0 - r12} ) | |
98 | THUMB( str sp, [sp, #S_SP] ) | |
99 | THUMB( str lr, [sp, #S_LR] ) | |
1da177e4 LT |
100 | mov r1, #\reason |
101 | .endm | |
102 | ||
103 | __pabt_invalid: | |
ccea7a19 RK |
104 | inv_entry BAD_PREFETCH |
105 | b common_invalid | |
93ed3970 | 106 | ENDPROC(__pabt_invalid) |
1da177e4 LT |
107 | |
108 | __dabt_invalid: | |
ccea7a19 RK |
109 | inv_entry BAD_DATA |
110 | b common_invalid | |
93ed3970 | 111 | ENDPROC(__dabt_invalid) |
1da177e4 LT |
112 | |
113 | __irq_invalid: | |
ccea7a19 RK |
114 | inv_entry BAD_IRQ |
115 | b common_invalid | |
93ed3970 | 116 | ENDPROC(__irq_invalid) |
1da177e4 LT |
117 | |
118 | __und_invalid: | |
ccea7a19 RK |
119 | inv_entry BAD_UNDEFINSTR |
120 | ||
121 | @ | |
122 | @ XXX fall through to common_invalid | |
123 | @ | |
124 | ||
125 | @ | |
126 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
127 | @ | |
128 | common_invalid: | |
129 | zero_fp | |
130 | ||
131 | ldmia r0, {r4 - r6} | |
132 | add r0, sp, #S_PC @ here for interlock avoidance | |
133 | mov r7, #-1 @ "" "" "" "" | |
134 | str r4, [sp] @ save preserved r0 | |
135 | stmia r0, {r5 - r7} @ lr_<exception>, | |
136 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 137 | |
1da177e4 | 138 | mov r0, sp |
1da177e4 | 139 | b bad_mode |
93ed3970 | 140 | ENDPROC(__und_invalid) |
1da177e4 LT |
141 | |
142 | /* | |
143 | * SVC mode handlers | |
144 | */ | |
2dede2d8 NP |
145 | |
146 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
147 | #define SPFIX(code...) code | |
148 | #else | |
149 | #define SPFIX(code...) | |
150 | #endif | |
151 | ||
c0e7f7ee | 152 | .macro svc_entry, stack_hole=0, trace=1 |
c4c5716e CM |
153 | UNWIND(.fnstart ) |
154 | UNWIND(.save {r0 - pc} ) | |
b86040a5 CM |
155 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
156 | #ifdef CONFIG_THUMB2_KERNEL | |
157 | SPFIX( str r0, [sp] ) @ temporarily saved | |
158 | SPFIX( mov r0, sp ) | |
159 | SPFIX( tst r0, #4 ) @ test original stack alignment | |
160 | SPFIX( ldr r0, [sp] ) @ restored | |
161 | #else | |
2dede2d8 | 162 | SPFIX( tst sp, #4 ) |
b86040a5 CM |
163 | #endif |
164 | SPFIX( subeq sp, sp, #4 ) | |
165 | stmia sp, {r1 - r12} | |
ccea7a19 | 166 | |
b059bdc3 RK |
167 | ldmia r0, {r3 - r5} |
168 | add r7, sp, #S_SP - 4 @ here for interlock avoidance | |
169 | mov r6, #-1 @ "" "" "" "" | |
170 | add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4) | |
171 | SPFIX( addeq r2, r2, #4 ) | |
172 | str r3, [sp, #-4]! @ save the "real" r0 copied | |
ccea7a19 RK |
173 | @ from the exception stack |
174 | ||
b059bdc3 | 175 | mov r3, lr |
1da177e4 LT |
176 | |
177 | @ | |
178 | @ We are now ready to fill in the remaining blanks on the stack: | |
179 | @ | |
b059bdc3 RK |
180 | @ r2 - sp_svc |
181 | @ r3 - lr_svc | |
182 | @ r4 - lr_<exception>, already fixed up for correct return/restart | |
183 | @ r5 - spsr_<exception> | |
184 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 | 185 | @ |
b059bdc3 | 186 | stmia r7, {r2 - r6} |
1da177e4 | 187 | |
c0e7f7ee | 188 | .if \trace |
02fe2845 RK |
189 | #ifdef CONFIG_TRACE_IRQFLAGS |
190 | bl trace_hardirqs_off | |
191 | #endif | |
c0e7f7ee | 192 | .endif |
f2741b78 | 193 | .endm |
1da177e4 | 194 | |
f2741b78 RK |
195 | .align 5 |
196 | __dabt_svc: | |
197 | svc_entry | |
1da177e4 | 198 | mov r2, sp |
da740472 | 199 | dabt_helper |
e16b31bf | 200 | THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR |
b059bdc3 | 201 | svc_exit r5 @ return from exception |
c4c5716e | 202 | UNWIND(.fnend ) |
93ed3970 | 203 | ENDPROC(__dabt_svc) |
1da177e4 LT |
204 | |
205 | .align 5 | |
206 | __irq_svc: | |
ccea7a19 | 207 | svc_entry |
187a51ad | 208 | irq_handler |
1613cc11 | 209 | |
1da177e4 | 210 | #ifdef CONFIG_PREEMPT |
1613cc11 RK |
211 | get_thread_info tsk |
212 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
706fdd9f | 213 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
28fab1a2 RK |
214 | teq r8, #0 @ if preempt count != 0 |
215 | movne r0, #0 @ force flags to 0 | |
1da177e4 LT |
216 | tst r0, #_TIF_NEED_RESCHED |
217 | blne svc_preempt | |
1da177e4 | 218 | #endif |
30891c90 | 219 | |
9b56febe | 220 | svc_exit r5, irq = 1 @ return from exception |
c4c5716e | 221 | UNWIND(.fnend ) |
93ed3970 | 222 | ENDPROC(__irq_svc) |
1da177e4 LT |
223 | |
224 | .ltorg | |
225 | ||
226 | #ifdef CONFIG_PREEMPT | |
227 | svc_preempt: | |
28fab1a2 | 228 | mov r8, lr |
1da177e4 | 229 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 230 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 | 231 | tst r0, #_TIF_NEED_RESCHED |
6ebbf2ce | 232 | reteq r8 @ go again |
1da177e4 LT |
233 | b 1b |
234 | #endif | |
235 | ||
15ac49b6 RK |
236 | __und_fault: |
237 | @ Correct the PC such that it is pointing at the instruction | |
238 | @ which caused the fault. If the faulting instruction was ARM | |
239 | @ the PC will be pointing at the next instruction, and have to | |
240 | @ subtract 4. Otherwise, it is Thumb, and the PC will be | |
241 | @ pointing at the second half of the Thumb instruction. We | |
242 | @ have to subtract 2. | |
243 | ldr r2, [r0, #S_PC] | |
244 | sub r2, r2, r1 | |
245 | str r2, [r0, #S_PC] | |
246 | b do_undefinstr | |
247 | ENDPROC(__und_fault) | |
248 | ||
1da177e4 LT |
249 | .align 5 |
250 | __und_svc: | |
d30a0c8b NP |
251 | #ifdef CONFIG_KPROBES |
252 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, | |
253 | @ it obviously needs free stack space which then will belong to | |
254 | @ the saved context. | |
a0266c21 | 255 | svc_entry MAX_STACK_SIZE |
d30a0c8b | 256 | #else |
ccea7a19 | 257 | svc_entry |
d30a0c8b | 258 | #endif |
1da177e4 LT |
259 | @ |
260 | @ call emulation code, which returns using r9 if it has emulated | |
261 | @ the instruction, or the more conventional lr if we are to treat | |
262 | @ this as a real undefined instruction | |
263 | @ | |
264 | @ r0 - instruction | |
265 | @ | |
15ac49b6 | 266 | #ifndef CONFIG_THUMB2_KERNEL |
b059bdc3 | 267 | ldr r0, [r4, #-4] |
83e686ea | 268 | #else |
15ac49b6 | 269 | mov r1, #2 |
b059bdc3 | 270 | ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 |
85519189 | 271 | cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 |
15ac49b6 RK |
272 | blo __und_svc_fault |
273 | ldrh r9, [r4] @ bottom 16 bits | |
274 | add r4, r4, #2 | |
275 | str r4, [sp, #S_PC] | |
276 | orr r0, r9, r0, lsl #16 | |
83e686ea | 277 | #endif |
14327c66 | 278 | badr r9, __und_svc_finish |
b059bdc3 | 279 | mov r2, r4 |
1da177e4 LT |
280 | bl call_fpe |
281 | ||
15ac49b6 RK |
282 | mov r1, #4 @ PC correction to apply |
283 | __und_svc_fault: | |
1da177e4 | 284 | mov r0, sp @ struct pt_regs *regs |
15ac49b6 | 285 | bl __und_fault |
1da177e4 | 286 | |
15ac49b6 | 287 | __und_svc_finish: |
b059bdc3 RK |
288 | ldr r5, [sp, #S_PSR] @ Get SVC cpsr |
289 | svc_exit r5 @ return from exception | |
c4c5716e | 290 | UNWIND(.fnend ) |
93ed3970 | 291 | ENDPROC(__und_svc) |
1da177e4 LT |
292 | |
293 | .align 5 | |
294 | __pabt_svc: | |
ccea7a19 | 295 | svc_entry |
4fb28474 | 296 | mov r2, sp @ regs |
8dfe7ac9 | 297 | pabt_helper |
b059bdc3 | 298 | svc_exit r5 @ return from exception |
c4c5716e | 299 | UNWIND(.fnend ) |
93ed3970 | 300 | ENDPROC(__pabt_svc) |
1da177e4 | 301 | |
c0e7f7ee DT |
302 | .align 5 |
303 | __fiq_svc: | |
304 | svc_entry trace=0 | |
305 | mov r0, sp @ struct pt_regs *regs | |
306 | bl handle_fiq_as_nmi | |
307 | svc_exit_via_fiq | |
308 | UNWIND(.fnend ) | |
309 | ENDPROC(__fiq_svc) | |
310 | ||
1da177e4 | 311 | .align 5 |
49f680ea RK |
312 | .LCcralign: |
313 | .word cr_alignment | |
48d7927b | 314 | #ifdef MULTI_DABORT |
1da177e4 LT |
315 | .LCprocfns: |
316 | .word processor | |
317 | #endif | |
318 | .LCfp: | |
319 | .word fp_enter | |
1da177e4 | 320 | |
c0e7f7ee DT |
321 | /* |
322 | * Abort mode handlers | |
323 | */ | |
324 | ||
325 | @ | |
326 | @ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode | |
327 | @ and reuses the same macros. However in abort mode we must also | |
328 | @ save/restore lr_abt and spsr_abt to make nested aborts safe. | |
329 | @ | |
330 | .align 5 | |
331 | __fiq_abt: | |
332 | svc_entry trace=0 | |
333 | ||
334 | ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
335 | THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
336 | THUMB( msr cpsr_c, r0 ) | |
337 | mov r1, lr @ Save lr_abt | |
338 | mrs r2, spsr @ Save spsr_abt, abort is now safe | |
339 | ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
340 | THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
341 | THUMB( msr cpsr_c, r0 ) | |
342 | stmfd sp!, {r1 - r2} | |
343 | ||
344 | add r0, sp, #8 @ struct pt_regs *regs | |
345 | bl handle_fiq_as_nmi | |
346 | ||
347 | ldmfd sp!, {r1 - r2} | |
348 | ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
349 | THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
350 | THUMB( msr cpsr_c, r0 ) | |
351 | mov lr, r1 @ Restore lr_abt, abort is unsafe | |
352 | msr spsr_cxsf, r2 @ Restore spsr_abt | |
353 | ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
354 | THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
355 | THUMB( msr cpsr_c, r0 ) | |
356 | ||
357 | svc_exit_via_fiq | |
358 | UNWIND(.fnend ) | |
359 | ENDPROC(__fiq_abt) | |
360 | ||
1da177e4 LT |
361 | /* |
362 | * User mode handlers | |
2dede2d8 NP |
363 | * |
364 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE | |
1da177e4 | 365 | */ |
2dede2d8 NP |
366 | |
367 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) | |
368 | #error "sizeof(struct pt_regs) must be a multiple of 8" | |
369 | #endif | |
370 | ||
c0e7f7ee | 371 | .macro usr_entry, trace=1 |
c4c5716e CM |
372 | UNWIND(.fnstart ) |
373 | UNWIND(.cantunwind ) @ don't unwind the user space | |
ccea7a19 | 374 | sub sp, sp, #S_FRAME_SIZE |
b86040a5 CM |
375 | ARM( stmib sp, {r1 - r12} ) |
376 | THUMB( stmia sp, {r0 - r12} ) | |
ccea7a19 | 377 | |
195b58ad RK |
378 | ATRAP( mrc p15, 0, r7, c1, c0, 0) |
379 | ATRAP( ldr r8, .LCcralign) | |
380 | ||
b059bdc3 | 381 | ldmia r0, {r3 - r5} |
ccea7a19 | 382 | add r0, sp, #S_PC @ here for interlock avoidance |
b059bdc3 | 383 | mov r6, #-1 @ "" "" "" "" |
ccea7a19 | 384 | |
b059bdc3 | 385 | str r3, [sp] @ save the "real" r0 copied |
ccea7a19 | 386 | @ from the exception stack |
1da177e4 | 387 | |
195b58ad RK |
388 | ATRAP( ldr r8, [r8, #0]) |
389 | ||
1da177e4 LT |
390 | @ |
391 | @ We are now ready to fill in the remaining blanks on the stack: | |
392 | @ | |
b059bdc3 RK |
393 | @ r4 - lr_<exception>, already fixed up for correct return/restart |
394 | @ r5 - spsr_<exception> | |
395 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 LT |
396 | @ |
397 | @ Also, separately save sp_usr and lr_usr | |
398 | @ | |
b059bdc3 | 399 | stmia r0, {r4 - r6} |
b86040a5 CM |
400 | ARM( stmdb r0, {sp, lr}^ ) |
401 | THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) | |
1da177e4 | 402 | |
1da177e4 | 403 | @ Enable the alignment trap while in kernel mode |
195b58ad RK |
404 | ATRAP( teq r8, r7) |
405 | ATRAP( mcrne p15, 0, r8, c1, c0, 0) | |
1da177e4 LT |
406 | |
407 | @ | |
408 | @ Clear FP to mark the first stack frame | |
409 | @ | |
410 | zero_fp | |
f2741b78 | 411 | |
c0e7f7ee | 412 | .if \trace |
f2741b78 RK |
413 | #ifdef CONFIG_IRQSOFF_TRACER |
414 | bl trace_hardirqs_off | |
415 | #endif | |
b0088480 | 416 | ct_user_exit save = 0 |
c0e7f7ee | 417 | .endif |
1da177e4 LT |
418 | .endm |
419 | ||
b49c0f24 | 420 | .macro kuser_cmpxchg_check |
1b16c4bc RK |
421 | #if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) && \ |
422 | !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) | |
b49c0f24 NP |
423 | #ifndef CONFIG_MMU |
424 | #warning "NPTL on non MMU needs fixing" | |
425 | #else | |
426 | @ Make sure our user space atomic helper is restarted | |
427 | @ if it was interrupted in a critical region. Here we | |
428 | @ perform a quick test inline since it should be false | |
429 | @ 99.9999% of the time. The rest is done out of line. | |
b059bdc3 | 430 | cmp r4, #TASK_SIZE |
40fb79c8 | 431 | blhs kuser_cmpxchg64_fixup |
b49c0f24 NP |
432 | #endif |
433 | #endif | |
434 | .endm | |
435 | ||
1da177e4 LT |
436 | .align 5 |
437 | __dabt_usr: | |
ccea7a19 | 438 | usr_entry |
b49c0f24 | 439 | kuser_cmpxchg_check |
1da177e4 | 440 | mov r2, sp |
da740472 RK |
441 | dabt_helper |
442 | b ret_from_exception | |
c4c5716e | 443 | UNWIND(.fnend ) |
93ed3970 | 444 | ENDPROC(__dabt_usr) |
1da177e4 LT |
445 | |
446 | .align 5 | |
447 | __irq_usr: | |
ccea7a19 | 448 | usr_entry |
bc089602 | 449 | kuser_cmpxchg_check |
187a51ad | 450 | irq_handler |
1613cc11 | 451 | get_thread_info tsk |
1da177e4 | 452 | mov why, #0 |
9fc2552a | 453 | b ret_to_user_from_irq |
c4c5716e | 454 | UNWIND(.fnend ) |
93ed3970 | 455 | ENDPROC(__irq_usr) |
1da177e4 LT |
456 | |
457 | .ltorg | |
458 | ||
459 | .align 5 | |
460 | __und_usr: | |
ccea7a19 | 461 | usr_entry |
bc089602 | 462 | |
b059bdc3 RK |
463 | mov r2, r4 |
464 | mov r3, r5 | |
1da177e4 | 465 | |
15ac49b6 RK |
466 | @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the |
467 | @ faulting instruction depending on Thumb mode. | |
468 | @ r3 = regs->ARM_cpsr | |
1da177e4 | 469 | @ |
15ac49b6 RK |
470 | @ The emulation code returns using r9 if it has emulated the |
471 | @ instruction, or the more conventional lr if we are to treat | |
472 | @ this as a real undefined instruction | |
1da177e4 | 473 | @ |
14327c66 | 474 | badr r9, ret_from_exception |
15ac49b6 | 475 | |
1417a6b8 CM |
476 | @ IRQs must be enabled before attempting to read the instruction from |
477 | @ user space since that could cause a page/translation fault if the | |
478 | @ page table was modified by another CPU. | |
479 | enable_irq | |
480 | ||
cb170a45 | 481 | tst r3, #PSR_T_BIT @ Thumb mode? |
15ac49b6 RK |
482 | bne __und_usr_thumb |
483 | sub r4, r2, #4 @ ARM instr at LR - 4 | |
484 | 1: ldrt r0, [r4] | |
457c2403 BD |
485 | ARM_BE8(rev r0, r0) @ little endian instruction |
486 | ||
15ac49b6 RK |
487 | @ r0 = 32-bit ARM instruction which caused the exception |
488 | @ r2 = PC value for the following instruction (:= regs->ARM_pc) | |
489 | @ r4 = PC value for the faulting instruction | |
490 | @ lr = 32-bit undefined instruction function | |
14327c66 | 491 | badr lr, __und_usr_fault_32 |
15ac49b6 RK |
492 | b call_fpe |
493 | ||
494 | __und_usr_thumb: | |
cb170a45 | 495 | @ Thumb instruction |
15ac49b6 | 496 | sub r4, r2, #2 @ First half of thumb instr at LR - 2 |
ef4c5368 DM |
497 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
498 | /* | |
499 | * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms | |
500 | * can never be supported in a single kernel, this code is not applicable at | |
501 | * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be | |
502 | * made about .arch directives. | |
503 | */ | |
504 | #if __LINUX_ARM_ARCH__ < 7 | |
505 | /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ | |
506 | #define NEED_CPU_ARCHITECTURE | |
507 | ldr r5, .LCcpu_architecture | |
508 | ldr r5, [r5] | |
509 | cmp r5, #CPU_ARCH_ARMv7 | |
15ac49b6 | 510 | blo __und_usr_fault_16 @ 16bit undefined instruction |
ef4c5368 DM |
511 | /* |
512 | * The following code won't get run unless the running CPU really is v7, so | |
513 | * coding round the lack of ldrht on older arches is pointless. Temporarily | |
514 | * override the assembler target arch with the minimum required instead: | |
515 | */ | |
516 | .arch armv6t2 | |
517 | #endif | |
15ac49b6 | 518 | 2: ldrht r5, [r4] |
f8fe23ec | 519 | ARM_BE8(rev16 r5, r5) @ little endian instruction |
85519189 | 520 | cmp r5, #0xe800 @ 32bit instruction if xx != 0 |
15ac49b6 RK |
521 | blo __und_usr_fault_16 @ 16bit undefined instruction |
522 | 3: ldrht r0, [r2] | |
f8fe23ec | 523 | ARM_BE8(rev16 r0, r0) @ little endian instruction |
cb170a45 | 524 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 |
15ac49b6 | 525 | str r2, [sp, #S_PC] @ it's a 2x16bit instr, update |
cb170a45 | 526 | orr r0, r0, r5, lsl #16 |
14327c66 | 527 | badr lr, __und_usr_fault_32 |
15ac49b6 RK |
528 | @ r0 = the two 16-bit Thumb instructions which caused the exception |
529 | @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) | |
530 | @ r4 = PC value for the first 16-bit Thumb instruction | |
531 | @ lr = 32bit undefined instruction function | |
ef4c5368 DM |
532 | |
533 | #if __LINUX_ARM_ARCH__ < 7 | |
534 | /* If the target arch was overridden, change it back: */ | |
535 | #ifdef CONFIG_CPU_32v6K | |
536 | .arch armv6k | |
cb170a45 | 537 | #else |
ef4c5368 DM |
538 | .arch armv6 |
539 | #endif | |
540 | #endif /* __LINUX_ARM_ARCH__ < 7 */ | |
541 | #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ | |
15ac49b6 | 542 | b __und_usr_fault_16 |
cb170a45 | 543 | #endif |
15ac49b6 | 544 | UNWIND(.fnend) |
93ed3970 | 545 | ENDPROC(__und_usr) |
cb170a45 | 546 | |
1da177e4 | 547 | /* |
15ac49b6 | 548 | * The out of line fixup for the ldrt instructions above. |
1da177e4 | 549 | */ |
c4a84ae3 | 550 | .pushsection .text.fixup, "ax" |
667d1b48 | 551 | .align 2 |
3780f7ab | 552 | 4: str r4, [sp, #S_PC] @ retry current instruction |
6ebbf2ce | 553 | ret r9 |
4260415f RK |
554 | .popsection |
555 | .pushsection __ex_table,"a" | |
cb170a45 | 556 | .long 1b, 4b |
c89cefed | 557 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
cb170a45 PB |
558 | .long 2b, 4b |
559 | .long 3b, 4b | |
560 | #endif | |
4260415f | 561 | .popsection |
1da177e4 LT |
562 | |
563 | /* | |
564 | * Check whether the instruction is a co-processor instruction. | |
565 | * If yes, we need to call the relevant co-processor handler. | |
566 | * | |
567 | * Note that we don't do a full check here for the co-processor | |
568 | * instructions; all instructions with bit 27 set are well | |
569 | * defined. The only instructions that should fault are the | |
570 | * co-processor instructions. However, we have to watch out | |
571 | * for the ARM6/ARM7 SWI bug. | |
572 | * | |
b5872db4 CM |
573 | * NEON is a special case that has to be handled here. Not all |
574 | * NEON instructions are co-processor instructions, so we have | |
575 | * to make a special case of checking for them. Plus, there's | |
576 | * five groups of them, so we have a table of mask/opcode pairs | |
577 | * to check against, and if any match then we branch off into the | |
578 | * NEON handler code. | |
579 | * | |
1da177e4 | 580 | * Emulators may wish to make use of the following registers: |
15ac49b6 RK |
581 | * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) |
582 | * r2 = PC value to resume execution after successful emulation | |
db6ccbb6 | 583 | * r9 = normal "successful" return address |
15ac49b6 | 584 | * r10 = this threads thread_info structure |
db6ccbb6 | 585 | * lr = unrecognised instruction return address |
1417a6b8 | 586 | * IRQs enabled, FIQs enabled. |
1da177e4 | 587 | */ |
cb170a45 PB |
588 | @ |
589 | @ Fall-through from Thumb-2 __und_usr | |
590 | @ | |
591 | #ifdef CONFIG_NEON | |
d3f79584 | 592 | get_thread_info r10 @ get current thread |
cb170a45 PB |
593 | adr r6, .LCneon_thumb_opcodes |
594 | b 2f | |
595 | #endif | |
1da177e4 | 596 | call_fpe: |
d3f79584 | 597 | get_thread_info r10 @ get current thread |
b5872db4 | 598 | #ifdef CONFIG_NEON |
cb170a45 | 599 | adr r6, .LCneon_arm_opcodes |
d3f79584 | 600 | 2: ldr r5, [r6], #4 @ mask value |
b5872db4 | 601 | ldr r7, [r6], #4 @ opcode bits matching in mask |
d3f79584 RK |
602 | cmp r5, #0 @ end mask? |
603 | beq 1f | |
604 | and r8, r0, r5 | |
b5872db4 CM |
605 | cmp r8, r7 @ NEON instruction? |
606 | bne 2b | |
b5872db4 CM |
607 | mov r7, #1 |
608 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used | |
609 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used | |
610 | b do_vfp @ let VFP handler handle this | |
611 | 1: | |
612 | #endif | |
1da177e4 | 613 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
cb170a45 | 614 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
6ebbf2ce | 615 | reteq lr |
1da177e4 | 616 | and r8, r0, #0x00000f00 @ mask out CP number |
b86040a5 | 617 | THUMB( lsr r8, r8, #8 ) |
1da177e4 LT |
618 | mov r7, #1 |
619 | add r6, r10, #TI_USED_CP | |
b86040a5 CM |
620 | ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] |
621 | THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] | |
1da177e4 LT |
622 | #ifdef CONFIG_IWMMXT |
623 | @ Test if we need to give access to iWMMXt coprocessors | |
624 | ldr r5, [r10, #TI_FLAGS] | |
625 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
626 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
627 | bcs iwmmxt_task_enable | |
628 | #endif | |
b86040a5 CM |
629 | ARM( add pc, pc, r8, lsr #6 ) |
630 | THUMB( lsl r8, r8, #2 ) | |
631 | THUMB( add pc, r8 ) | |
632 | nop | |
633 | ||
6ebbf2ce | 634 | ret.w lr @ CP#0 |
b86040a5 CM |
635 | W(b) do_fpe @ CP#1 (FPE) |
636 | W(b) do_fpe @ CP#2 (FPE) | |
6ebbf2ce | 637 | ret.w lr @ CP#3 |
c17fad11 LB |
638 | #ifdef CONFIG_CRUNCH |
639 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
640 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
641 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
642 | #else | |
6ebbf2ce RK |
643 | ret.w lr @ CP#4 |
644 | ret.w lr @ CP#5 | |
645 | ret.w lr @ CP#6 | |
c17fad11 | 646 | #endif |
6ebbf2ce RK |
647 | ret.w lr @ CP#7 |
648 | ret.w lr @ CP#8 | |
649 | ret.w lr @ CP#9 | |
1da177e4 | 650 | #ifdef CONFIG_VFP |
b86040a5 CM |
651 | W(b) do_vfp @ CP#10 (VFP) |
652 | W(b) do_vfp @ CP#11 (VFP) | |
1da177e4 | 653 | #else |
6ebbf2ce RK |
654 | ret.w lr @ CP#10 (VFP) |
655 | ret.w lr @ CP#11 (VFP) | |
1da177e4 | 656 | #endif |
6ebbf2ce RK |
657 | ret.w lr @ CP#12 |
658 | ret.w lr @ CP#13 | |
659 | ret.w lr @ CP#14 (Debug) | |
660 | ret.w lr @ CP#15 (Control) | |
1da177e4 | 661 | |
ef4c5368 DM |
662 | #ifdef NEED_CPU_ARCHITECTURE |
663 | .align 2 | |
664 | .LCcpu_architecture: | |
665 | .word __cpu_architecture | |
666 | #endif | |
667 | ||
b5872db4 CM |
668 | #ifdef CONFIG_NEON |
669 | .align 6 | |
670 | ||
cb170a45 | 671 | .LCneon_arm_opcodes: |
b5872db4 CM |
672 | .word 0xfe000000 @ mask |
673 | .word 0xf2000000 @ opcode | |
674 | ||
675 | .word 0xff100000 @ mask | |
676 | .word 0xf4000000 @ opcode | |
677 | ||
cb170a45 PB |
678 | .word 0x00000000 @ mask |
679 | .word 0x00000000 @ opcode | |
680 | ||
681 | .LCneon_thumb_opcodes: | |
682 | .word 0xef000000 @ mask | |
683 | .word 0xef000000 @ opcode | |
684 | ||
685 | .word 0xff100000 @ mask | |
686 | .word 0xf9000000 @ opcode | |
687 | ||
b5872db4 CM |
688 | .word 0x00000000 @ mask |
689 | .word 0x00000000 @ opcode | |
690 | #endif | |
691 | ||
1da177e4 LT |
692 | do_fpe: |
693 | ldr r4, .LCfp | |
694 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
695 | ldr pc, [r4] @ Call FP module USR entry point | |
696 | ||
697 | /* | |
698 | * The FP module is called with these registers set: | |
699 | * r0 = instruction | |
700 | * r2 = PC+4 | |
701 | * r9 = normal "successful" return address | |
702 | * r10 = FP workspace | |
703 | * lr = unrecognised FP instruction return address | |
704 | */ | |
705 | ||
124efc27 | 706 | .pushsection .data |
1da177e4 | 707 | ENTRY(fp_enter) |
db6ccbb6 | 708 | .word no_fp |
124efc27 | 709 | .popsection |
1da177e4 | 710 | |
83e686ea | 711 | ENTRY(no_fp) |
6ebbf2ce | 712 | ret lr |
83e686ea | 713 | ENDPROC(no_fp) |
db6ccbb6 | 714 | |
15ac49b6 RK |
715 | __und_usr_fault_32: |
716 | mov r1, #4 | |
717 | b 1f | |
718 | __und_usr_fault_16: | |
719 | mov r1, #2 | |
1417a6b8 | 720 | 1: mov r0, sp |
14327c66 | 721 | badr lr, ret_from_exception |
15ac49b6 RK |
722 | b __und_fault |
723 | ENDPROC(__und_usr_fault_32) | |
724 | ENDPROC(__und_usr_fault_16) | |
1da177e4 LT |
725 | |
726 | .align 5 | |
727 | __pabt_usr: | |
ccea7a19 | 728 | usr_entry |
4fb28474 | 729 | mov r2, sp @ regs |
8dfe7ac9 | 730 | pabt_helper |
c4c5716e | 731 | UNWIND(.fnend ) |
1da177e4 LT |
732 | /* fall through */ |
733 | /* | |
734 | * This is the return code to user mode for abort handlers | |
735 | */ | |
736 | ENTRY(ret_from_exception) | |
c4c5716e CM |
737 | UNWIND(.fnstart ) |
738 | UNWIND(.cantunwind ) | |
1da177e4 LT |
739 | get_thread_info tsk |
740 | mov why, #0 | |
741 | b ret_to_user | |
c4c5716e | 742 | UNWIND(.fnend ) |
93ed3970 CM |
743 | ENDPROC(__pabt_usr) |
744 | ENDPROC(ret_from_exception) | |
1da177e4 | 745 | |
c0e7f7ee DT |
746 | .align 5 |
747 | __fiq_usr: | |
748 | usr_entry trace=0 | |
749 | kuser_cmpxchg_check | |
750 | mov r0, sp @ struct pt_regs *regs | |
751 | bl handle_fiq_as_nmi | |
752 | get_thread_info tsk | |
753 | restore_user_regs fast = 0, offset = 0 | |
754 | UNWIND(.fnend ) | |
755 | ENDPROC(__fiq_usr) | |
756 | ||
1da177e4 LT |
757 | /* |
758 | * Register switch for ARMv3 and ARMv4 processors | |
759 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
760 | * previous and next are guaranteed not to be the same. | |
761 | */ | |
762 | ENTRY(__switch_to) | |
c4c5716e CM |
763 | UNWIND(.fnstart ) |
764 | UNWIND(.cantunwind ) | |
1da177e4 | 765 | add ip, r1, #TI_CPU_SAVE |
b86040a5 CM |
766 | ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack |
767 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack | |
768 | THUMB( str sp, [ip], #4 ) | |
769 | THUMB( str lr, [ip], #4 ) | |
a4780ade AH |
770 | ldr r4, [r2, #TI_TP_VALUE] |
771 | ldr r5, [r2, #TI_TP_VALUE + 4] | |
247055aa | 772 | #ifdef CONFIG_CPU_USE_DOMAINS |
1eef5d2f RK |
773 | mrc p15, 0, r6, c3, c0, 0 @ Get domain register |
774 | str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register | |
d6551e88 | 775 | ldr r6, [r2, #TI_CPU_DOMAIN] |
afeb90ca | 776 | #endif |
a4780ade | 777 | switch_tls r1, r4, r5, r3, r7 |
df0698be NP |
778 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
779 | ldr r7, [r2, #TI_TASK] | |
780 | ldr r8, =__stack_chk_guard | |
781 | ldr r7, [r7, #TSK_STACK_CANARY] | |
782 | #endif | |
247055aa | 783 | #ifdef CONFIG_CPU_USE_DOMAINS |
1da177e4 | 784 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 785 | #endif |
d6551e88 RK |
786 | mov r5, r0 |
787 | add r4, r2, #TI_CPU_SAVE | |
788 | ldr r0, =thread_notify_head | |
789 | mov r1, #THREAD_NOTIFY_SWITCH | |
790 | bl atomic_notifier_call_chain | |
df0698be NP |
791 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
792 | str r7, [r8] | |
793 | #endif | |
b86040a5 | 794 | THUMB( mov ip, r4 ) |
d6551e88 | 795 | mov r0, r5 |
b86040a5 CM |
796 | ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously |
797 | THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously | |
798 | THUMB( ldr sp, [ip], #4 ) | |
799 | THUMB( ldr pc, [ip] ) | |
c4c5716e | 800 | UNWIND(.fnend ) |
93ed3970 | 801 | ENDPROC(__switch_to) |
1da177e4 LT |
802 | |
803 | __INIT | |
2d2669b6 NP |
804 | |
805 | /* | |
806 | * User helpers. | |
807 | * | |
2d2669b6 NP |
808 | * Each segment is 32-byte aligned and will be moved to the top of the high |
809 | * vector page. New segments (if ever needed) must be added in front of | |
810 | * existing ones. This mechanism should be used only for things that are | |
811 | * really small and justified, and not be abused freely. | |
812 | * | |
37b83046 | 813 | * See Documentation/arm/kernel_user_helpers.txt for formal definitions. |
2d2669b6 | 814 | */ |
b86040a5 | 815 | THUMB( .arm ) |
2d2669b6 | 816 | |
ba9b5d76 NP |
817 | .macro usr_ret, reg |
818 | #ifdef CONFIG_ARM_THUMB | |
819 | bx \reg | |
820 | #else | |
6ebbf2ce | 821 | ret \reg |
ba9b5d76 NP |
822 | #endif |
823 | .endm | |
824 | ||
5b43e7a3 RK |
825 | .macro kuser_pad, sym, size |
826 | .if (. - \sym) & 3 | |
827 | .rept 4 - (. - \sym) & 3 | |
828 | .byte 0 | |
829 | .endr | |
830 | .endif | |
831 | .rept (\size - (. - \sym)) / 4 | |
832 | .word 0xe7fddef1 | |
833 | .endr | |
834 | .endm | |
835 | ||
f6f91b0d | 836 | #ifdef CONFIG_KUSER_HELPERS |
2d2669b6 NP |
837 | .align 5 |
838 | .globl __kuser_helper_start | |
839 | __kuser_helper_start: | |
840 | ||
7c612bfd | 841 | /* |
40fb79c8 NP |
842 | * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular |
843 | * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. | |
7c612bfd NP |
844 | */ |
845 | ||
40fb79c8 NP |
846 | __kuser_cmpxchg64: @ 0xffff0f60 |
847 | ||
848 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) | |
849 | ||
850 | /* | |
851 | * Poor you. No fast solution possible... | |
852 | * The kernel itself must perform the operation. | |
853 | * A special ghost syscall is used for that (see traps.c). | |
854 | */ | |
855 | stmfd sp!, {r7, lr} | |
856 | ldr r7, 1f @ it's 20 bits | |
857 | swi __ARM_NR_cmpxchg64 | |
858 | ldmfd sp!, {r7, pc} | |
859 | 1: .word __ARM_NR_cmpxchg64 | |
860 | ||
861 | #elif defined(CONFIG_CPU_32v6K) | |
862 | ||
863 | stmfd sp!, {r4, r5, r6, r7} | |
864 | ldrd r4, r5, [r0] @ load old val | |
865 | ldrd r6, r7, [r1] @ load new val | |
866 | smp_dmb arm | |
867 | 1: ldrexd r0, r1, [r2] @ load current val | |
868 | eors r3, r0, r4 @ compare with oldval (1) | |
869 | eoreqs r3, r1, r5 @ compare with oldval (2) | |
870 | strexdeq r3, r6, r7, [r2] @ store newval if eq | |
871 | teqeq r3, #1 @ success? | |
872 | beq 1b @ if no then retry | |
ed3768a8 | 873 | smp_dmb arm |
40fb79c8 NP |
874 | rsbs r0, r3, #0 @ set returned val and C flag |
875 | ldmfd sp!, {r4, r5, r6, r7} | |
5a97d0ae | 876 | usr_ret lr |
40fb79c8 NP |
877 | |
878 | #elif !defined(CONFIG_SMP) | |
879 | ||
880 | #ifdef CONFIG_MMU | |
881 | ||
882 | /* | |
883 | * The only thing that can break atomicity in this cmpxchg64 | |
884 | * implementation is either an IRQ or a data abort exception | |
885 | * causing another process/thread to be scheduled in the middle of | |
886 | * the critical sequence. The same strategy as for cmpxchg is used. | |
887 | */ | |
888 | stmfd sp!, {r4, r5, r6, lr} | |
889 | ldmia r0, {r4, r5} @ load old val | |
890 | ldmia r1, {r6, lr} @ load new val | |
891 | 1: ldmia r2, {r0, r1} @ load current val | |
892 | eors r3, r0, r4 @ compare with oldval (1) | |
893 | eoreqs r3, r1, r5 @ compare with oldval (2) | |
894 | 2: stmeqia r2, {r6, lr} @ store newval if eq | |
895 | rsbs r0, r3, #0 @ set return val and C flag | |
896 | ldmfd sp!, {r4, r5, r6, pc} | |
897 | ||
898 | .text | |
899 | kuser_cmpxchg64_fixup: | |
900 | @ Called from kuser_cmpxchg_fixup. | |
3ad55155 | 901 | @ r4 = address of interrupted insn (must be preserved). |
40fb79c8 NP |
902 | @ sp = saved regs. r7 and r8 are clobbered. |
903 | @ 1b = first critical insn, 2b = last critical insn. | |
3ad55155 | 904 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
40fb79c8 NP |
905 | mov r7, #0xffff0fff |
906 | sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) | |
3ad55155 | 907 | subs r8, r4, r7 |
40fb79c8 NP |
908 | rsbcss r8, r8, #(2b - 1b) |
909 | strcs r7, [sp, #S_PC] | |
910 | #if __LINUX_ARM_ARCH__ < 6 | |
911 | bcc kuser_cmpxchg32_fixup | |
912 | #endif | |
6ebbf2ce | 913 | ret lr |
40fb79c8 NP |
914 | .previous |
915 | ||
916 | #else | |
917 | #warning "NPTL on non MMU needs fixing" | |
918 | mov r0, #-1 | |
919 | adds r0, r0, #0 | |
ba9b5d76 | 920 | usr_ret lr |
40fb79c8 NP |
921 | #endif |
922 | ||
923 | #else | |
924 | #error "incoherent kernel configuration" | |
925 | #endif | |
926 | ||
5b43e7a3 | 927 | kuser_pad __kuser_cmpxchg64, 64 |
7c612bfd | 928 | |
7c612bfd | 929 | __kuser_memory_barrier: @ 0xffff0fa0 |
ed3768a8 | 930 | smp_dmb arm |
ba9b5d76 | 931 | usr_ret lr |
7c612bfd | 932 | |
5b43e7a3 | 933 | kuser_pad __kuser_memory_barrier, 32 |
2d2669b6 NP |
934 | |
935 | __kuser_cmpxchg: @ 0xffff0fc0 | |
936 | ||
dcef1f63 | 937 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 938 | |
dcef1f63 NP |
939 | /* |
940 | * Poor you. No fast solution possible... | |
941 | * The kernel itself must perform the operation. | |
942 | * A special ghost syscall is used for that (see traps.c). | |
943 | */ | |
5e097445 | 944 | stmfd sp!, {r7, lr} |
55afd264 | 945 | ldr r7, 1f @ it's 20 bits |
cc20d429 | 946 | swi __ARM_NR_cmpxchg |
5e097445 | 947 | ldmfd sp!, {r7, pc} |
cc20d429 | 948 | 1: .word __ARM_NR_cmpxchg |
dcef1f63 NP |
949 | |
950 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 | 951 | |
b49c0f24 NP |
952 | #ifdef CONFIG_MMU |
953 | ||
2d2669b6 | 954 | /* |
b49c0f24 NP |
955 | * The only thing that can break atomicity in this cmpxchg |
956 | * implementation is either an IRQ or a data abort exception | |
957 | * causing another process/thread to be scheduled in the middle | |
958 | * of the critical sequence. To prevent this, code is added to | |
959 | * the IRQ and data abort exception handlers to set the pc back | |
960 | * to the beginning of the critical section if it is found to be | |
961 | * within that critical section (see kuser_cmpxchg_fixup). | |
2d2669b6 | 962 | */ |
b49c0f24 NP |
963 | 1: ldr r3, [r2] @ load current val |
964 | subs r3, r3, r0 @ compare with oldval | |
965 | 2: streq r1, [r2] @ store newval if eq | |
966 | rsbs r0, r3, #0 @ set return val and C flag | |
967 | usr_ret lr | |
968 | ||
969 | .text | |
40fb79c8 | 970 | kuser_cmpxchg32_fixup: |
b49c0f24 | 971 | @ Called from kuser_cmpxchg_check macro. |
b059bdc3 | 972 | @ r4 = address of interrupted insn (must be preserved). |
b49c0f24 NP |
973 | @ sp = saved regs. r7 and r8 are clobbered. |
974 | @ 1b = first critical insn, 2b = last critical insn. | |
b059bdc3 | 975 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
b49c0f24 NP |
976 | mov r7, #0xffff0fff |
977 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) | |
b059bdc3 | 978 | subs r8, r4, r7 |
b49c0f24 NP |
979 | rsbcss r8, r8, #(2b - 1b) |
980 | strcs r7, [sp, #S_PC] | |
6ebbf2ce | 981 | ret lr |
b49c0f24 NP |
982 | .previous |
983 | ||
49bca4c2 NP |
984 | #else |
985 | #warning "NPTL on non MMU needs fixing" | |
986 | mov r0, #-1 | |
987 | adds r0, r0, #0 | |
ba9b5d76 | 988 | usr_ret lr |
b49c0f24 | 989 | #endif |
2d2669b6 NP |
990 | |
991 | #else | |
992 | ||
ed3768a8 | 993 | smp_dmb arm |
b49c0f24 | 994 | 1: ldrex r3, [r2] |
2d2669b6 NP |
995 | subs r3, r3, r0 |
996 | strexeq r3, r1, [r2] | |
b49c0f24 NP |
997 | teqeq r3, #1 |
998 | beq 1b | |
2d2669b6 | 999 | rsbs r0, r3, #0 |
b49c0f24 | 1000 | /* beware -- each __kuser slot must be 8 instructions max */ |
f00ec48f RK |
1001 | ALT_SMP(b __kuser_memory_barrier) |
1002 | ALT_UP(usr_ret lr) | |
2d2669b6 NP |
1003 | |
1004 | #endif | |
1005 | ||
5b43e7a3 | 1006 | kuser_pad __kuser_cmpxchg, 32 |
2d2669b6 | 1007 | |
2d2669b6 | 1008 | __kuser_get_tls: @ 0xffff0fe0 |
f159f4ed | 1009 | ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init |
ba9b5d76 | 1010 | usr_ret lr |
f159f4ed | 1011 | mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code |
5b43e7a3 RK |
1012 | kuser_pad __kuser_get_tls, 16 |
1013 | .rep 3 | |
f159f4ed TL |
1014 | .word 0 @ 0xffff0ff0 software TLS value, then |
1015 | .endr @ pad up to __kuser_helper_version | |
2d2669b6 | 1016 | |
2d2669b6 NP |
1017 | __kuser_helper_version: @ 0xffff0ffc |
1018 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
1019 | ||
1020 | .globl __kuser_helper_end | |
1021 | __kuser_helper_end: | |
1022 | ||
f6f91b0d RK |
1023 | #endif |
1024 | ||
b86040a5 | 1025 | THUMB( .thumb ) |
2d2669b6 | 1026 | |
1da177e4 LT |
1027 | /* |
1028 | * Vector stubs. | |
1029 | * | |
19accfd3 RK |
1030 | * This code is copied to 0xffff1000 so we can use branches in the |
1031 | * vectors, rather than ldr's. Note that this code must not exceed | |
1032 | * a page size. | |
1da177e4 LT |
1033 | * |
1034 | * Common stub entry macro: | |
1035 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
1036 | * |
1037 | * SP points to a minimal amount of processor-private memory, the address | |
1038 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 1039 | */ |
b7ec4795 | 1040 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
1041 | .align 5 |
1042 | ||
1043 | vector_\name: | |
1da177e4 LT |
1044 | .if \correction |
1045 | sub lr, lr, #\correction | |
1046 | .endif | |
ccea7a19 RK |
1047 | |
1048 | @ | |
1049 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
1050 | @ (parent CPSR) | |
1051 | @ | |
1052 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 1053 | mrs lr, spsr |
ccea7a19 RK |
1054 | str lr, [sp, #8] @ save spsr |
1055 | ||
1da177e4 | 1056 | @ |
ccea7a19 | 1057 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 1058 | @ |
ccea7a19 | 1059 | mrs r0, cpsr |
b86040a5 | 1060 | eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) |
ccea7a19 | 1061 | msr spsr_cxsf, r0 |
1da177e4 | 1062 | |
ccea7a19 RK |
1063 | @ |
1064 | @ the branch table must immediately follow this code | |
1065 | @ | |
ccea7a19 | 1066 | and lr, lr, #0x0f |
b86040a5 CM |
1067 | THUMB( adr r0, 1f ) |
1068 | THUMB( ldr lr, [r0, lr, lsl #2] ) | |
b7ec4795 | 1069 | mov r0, sp |
b86040a5 | 1070 | ARM( ldr lr, [pc, lr, lsl #2] ) |
ccea7a19 | 1071 | movs pc, lr @ branch to handler in SVC mode |
93ed3970 | 1072 | ENDPROC(vector_\name) |
88987ef9 CM |
1073 | |
1074 | .align 2 | |
1075 | @ handler addresses follow this label | |
1076 | 1: | |
1da177e4 LT |
1077 | .endm |
1078 | ||
b9b32bf7 | 1079 | .section .stubs, "ax", %progbits |
1da177e4 | 1080 | __stubs_start: |
19accfd3 RK |
1081 | @ This must be the first word |
1082 | .word vector_swi | |
1083 | ||
1084 | vector_rst: | |
1085 | ARM( swi SYS_ERROR0 ) | |
1086 | THUMB( svc #0 ) | |
1087 | THUMB( nop ) | |
1088 | b vector_und | |
1089 | ||
1da177e4 LT |
1090 | /* |
1091 | * Interrupt dispatcher | |
1092 | */ | |
b7ec4795 | 1093 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
1094 | |
1095 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
1096 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
1097 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
1098 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
1099 | .long __irq_invalid @ 4 | |
1100 | .long __irq_invalid @ 5 | |
1101 | .long __irq_invalid @ 6 | |
1102 | .long __irq_invalid @ 7 | |
1103 | .long __irq_invalid @ 8 | |
1104 | .long __irq_invalid @ 9 | |
1105 | .long __irq_invalid @ a | |
1106 | .long __irq_invalid @ b | |
1107 | .long __irq_invalid @ c | |
1108 | .long __irq_invalid @ d | |
1109 | .long __irq_invalid @ e | |
1110 | .long __irq_invalid @ f | |
1111 | ||
1112 | /* | |
1113 | * Data abort dispatcher | |
1114 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1115 | */ | |
b7ec4795 | 1116 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
1117 | |
1118 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
1119 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1120 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1121 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
1122 | .long __dabt_invalid @ 4 | |
1123 | .long __dabt_invalid @ 5 | |
1124 | .long __dabt_invalid @ 6 | |
1125 | .long __dabt_invalid @ 7 | |
1126 | .long __dabt_invalid @ 8 | |
1127 | .long __dabt_invalid @ 9 | |
1128 | .long __dabt_invalid @ a | |
1129 | .long __dabt_invalid @ b | |
1130 | .long __dabt_invalid @ c | |
1131 | .long __dabt_invalid @ d | |
1132 | .long __dabt_invalid @ e | |
1133 | .long __dabt_invalid @ f | |
1134 | ||
1135 | /* | |
1136 | * Prefetch abort dispatcher | |
1137 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1138 | */ | |
b7ec4795 | 1139 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
1140 | |
1141 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
1142 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1143 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1144 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
1145 | .long __pabt_invalid @ 4 | |
1146 | .long __pabt_invalid @ 5 | |
1147 | .long __pabt_invalid @ 6 | |
1148 | .long __pabt_invalid @ 7 | |
1149 | .long __pabt_invalid @ 8 | |
1150 | .long __pabt_invalid @ 9 | |
1151 | .long __pabt_invalid @ a | |
1152 | .long __pabt_invalid @ b | |
1153 | .long __pabt_invalid @ c | |
1154 | .long __pabt_invalid @ d | |
1155 | .long __pabt_invalid @ e | |
1156 | .long __pabt_invalid @ f | |
1157 | ||
1158 | /* | |
1159 | * Undef instr entry dispatcher | |
1160 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1161 | */ | |
b7ec4795 | 1162 | vector_stub und, UND_MODE |
1da177e4 LT |
1163 | |
1164 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1165 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1166 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1167 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1168 | .long __und_invalid @ 4 | |
1169 | .long __und_invalid @ 5 | |
1170 | .long __und_invalid @ 6 | |
1171 | .long __und_invalid @ 7 | |
1172 | .long __und_invalid @ 8 | |
1173 | .long __und_invalid @ 9 | |
1174 | .long __und_invalid @ a | |
1175 | .long __und_invalid @ b | |
1176 | .long __und_invalid @ c | |
1177 | .long __und_invalid @ d | |
1178 | .long __und_invalid @ e | |
1179 | .long __und_invalid @ f | |
1180 | ||
1181 | .align 5 | |
1182 | ||
19accfd3 RK |
1183 | /*============================================================================= |
1184 | * Address exception handler | |
1185 | *----------------------------------------------------------------------------- | |
1186 | * These aren't too critical. | |
1187 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1188 | */ | |
1189 | ||
1190 | vector_addrexcptn: | |
1191 | b vector_addrexcptn | |
1192 | ||
1da177e4 | 1193 | /*============================================================================= |
c0e7f7ee | 1194 | * FIQ "NMI" handler |
1da177e4 | 1195 | *----------------------------------------------------------------------------- |
c0e7f7ee DT |
1196 | * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 |
1197 | * systems. | |
1da177e4 | 1198 | */ |
c0e7f7ee DT |
1199 | vector_stub fiq, FIQ_MODE, 4 |
1200 | ||
1201 | .long __fiq_usr @ 0 (USR_26 / USR_32) | |
1202 | .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) | |
1203 | .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) | |
1204 | .long __fiq_svc @ 3 (SVC_26 / SVC_32) | |
1205 | .long __fiq_svc @ 4 | |
1206 | .long __fiq_svc @ 5 | |
1207 | .long __fiq_svc @ 6 | |
1208 | .long __fiq_abt @ 7 | |
1209 | .long __fiq_svc @ 8 | |
1210 | .long __fiq_svc @ 9 | |
1211 | .long __fiq_svc @ a | |
1212 | .long __fiq_svc @ b | |
1213 | .long __fiq_svc @ c | |
1214 | .long __fiq_svc @ d | |
1215 | .long __fiq_svc @ e | |
1216 | .long __fiq_svc @ f | |
1da177e4 | 1217 | |
e39e3f3e RK |
1218 | .globl vector_fiq_offset |
1219 | .equ vector_fiq_offset, vector_fiq | |
1220 | ||
b9b32bf7 | 1221 | .section .vectors, "ax", %progbits |
7933523d | 1222 | __vectors_start: |
b9b32bf7 RK |
1223 | W(b) vector_rst |
1224 | W(b) vector_und | |
1225 | W(ldr) pc, __vectors_start + 0x1000 | |
1226 | W(b) vector_pabt | |
1227 | W(b) vector_dabt | |
1228 | W(b) vector_addrexcptn | |
1229 | W(b) vector_irq | |
1230 | W(b) vector_fiq | |
1da177e4 LT |
1231 | |
1232 | .data | |
1233 | ||
1da177e4 | 1234 | .globl cr_alignment |
1da177e4 LT |
1235 | cr_alignment: |
1236 | .space 4 | |
52108641 | 1237 | |
1238 | #ifdef CONFIG_MULTI_IRQ_HANDLER | |
1239 | .globl handle_arch_irq | |
1240 | handle_arch_irq: | |
1241 | .space 4 | |
1242 | #endif |