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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * Low-level vector interface routines | |
12 | * | |
13 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes | |
14 | * it to save wrong values... Be aware! | |
15 | */ | |
16 | #include <linux/config.h> | |
1da177e4 | 17 | |
1da177e4 | 18 | #include <asm/glue.h> |
1da177e4 | 19 | #include <asm/vfpmacros.h> |
41e46d6a NP |
20 | #include <asm/hardware.h> /* should be moved into entry-macro.S */ |
21 | #include <asm/arch/irqs.h> /* should be moved into entry-macro.S */ | |
bce495d8 | 22 | #include <asm/arch/entry-macro.S> |
1da177e4 LT |
23 | |
24 | #include "entry-header.S" | |
25 | ||
187a51ad RK |
26 | /* |
27 | * Interrupt handling. Preserves r7, r8, r9 | |
28 | */ | |
29 | .macro irq_handler | |
30 | 1: get_irqnr_and_base r0, r6, r5, lr | |
31 | movne r1, sp | |
32 | @ | |
33 | @ routine called with r0 = irq number, r1 = struct pt_regs * | |
34 | @ | |
35 | adrne lr, 1b | |
36 | bne asm_do_IRQ | |
791be9b9 RK |
37 | |
38 | #ifdef CONFIG_SMP | |
39 | /* | |
40 | * XXX | |
41 | * | |
42 | * this macro assumes that irqstat (r6) and base (r5) are | |
43 | * preserved from get_irqnr_and_base above | |
44 | */ | |
45 | test_for_ipi r0, r6, r5, lr | |
46 | movne r0, sp | |
47 | adrne lr, 1b | |
48 | bne do_IPI | |
49 | #endif | |
50 | ||
187a51ad RK |
51 | .endm |
52 | ||
1da177e4 LT |
53 | /* |
54 | * Invalid mode handlers | |
55 | */ | |
ccea7a19 RK |
56 | .macro inv_entry, reason |
57 | sub sp, sp, #S_FRAME_SIZE | |
58 | stmib sp, {r1 - lr} | |
1da177e4 LT |
59 | mov r1, #\reason |
60 | .endm | |
61 | ||
62 | __pabt_invalid: | |
ccea7a19 RK |
63 | inv_entry BAD_PREFETCH |
64 | b common_invalid | |
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65 | |
66 | __dabt_invalid: | |
ccea7a19 RK |
67 | inv_entry BAD_DATA |
68 | b common_invalid | |
1da177e4 LT |
69 | |
70 | __irq_invalid: | |
ccea7a19 RK |
71 | inv_entry BAD_IRQ |
72 | b common_invalid | |
1da177e4 LT |
73 | |
74 | __und_invalid: | |
ccea7a19 RK |
75 | inv_entry BAD_UNDEFINSTR |
76 | ||
77 | @ | |
78 | @ XXX fall through to common_invalid | |
79 | @ | |
80 | ||
81 | @ | |
82 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
83 | @ | |
84 | common_invalid: | |
85 | zero_fp | |
86 | ||
87 | ldmia r0, {r4 - r6} | |
88 | add r0, sp, #S_PC @ here for interlock avoidance | |
89 | mov r7, #-1 @ "" "" "" "" | |
90 | str r4, [sp] @ save preserved r0 | |
91 | stmia r0, {r5 - r7} @ lr_<exception>, | |
92 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 93 | |
1da177e4 | 94 | mov r0, sp |
ccea7a19 | 95 | and r2, r6, #0x1f |
1da177e4 LT |
96 | b bad_mode |
97 | ||
98 | /* | |
99 | * SVC mode handlers | |
100 | */ | |
ccea7a19 | 101 | .macro svc_entry |
1da177e4 | 102 | sub sp, sp, #S_FRAME_SIZE |
ccea7a19 RK |
103 | stmib sp, {r1 - r12} |
104 | ||
105 | ldmia r0, {r1 - r3} | |
106 | add r5, sp, #S_SP @ here for interlock avoidance | |
107 | mov r4, #-1 @ "" "" "" "" | |
108 | add r0, sp, #S_FRAME_SIZE @ "" "" "" "" | |
109 | str r1, [sp] @ save the "real" r0 copied | |
110 | @ from the exception stack | |
111 | ||
1da177e4 LT |
112 | mov r1, lr |
113 | ||
114 | @ | |
115 | @ We are now ready to fill in the remaining blanks on the stack: | |
116 | @ | |
117 | @ r0 - sp_svc | |
118 | @ r1 - lr_svc | |
119 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
120 | @ r3 - spsr_<exception> | |
121 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
122 | @ | |
123 | stmia r5, {r0 - r4} | |
124 | .endm | |
125 | ||
126 | .align 5 | |
127 | __dabt_svc: | |
ccea7a19 | 128 | svc_entry |
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129 | |
130 | @ | |
131 | @ get ready to re-enable interrupts if appropriate | |
132 | @ | |
133 | mrs r9, cpsr | |
134 | tst r3, #PSR_I_BIT | |
135 | biceq r9, r9, #PSR_I_BIT | |
136 | ||
137 | @ | |
138 | @ Call the processor-specific abort handler: | |
139 | @ | |
140 | @ r2 - aborted context pc | |
141 | @ r3 - aborted context cpsr | |
142 | @ | |
143 | @ The abort handler must return the aborted address in r0, and | |
144 | @ the fault status register in r1. r9 must be preserved. | |
145 | @ | |
146 | #ifdef MULTI_ABORT | |
147 | ldr r4, .LCprocfns | |
148 | mov lr, pc | |
149 | ldr pc, [r4] | |
150 | #else | |
151 | bl CPU_ABORT_HANDLER | |
152 | #endif | |
153 | ||
154 | @ | |
155 | @ set desired IRQ state, then call main handler | |
156 | @ | |
157 | msr cpsr_c, r9 | |
158 | mov r2, sp | |
159 | bl do_DataAbort | |
160 | ||
161 | @ | |
162 | @ IRQs off again before pulling preserved data off the stack | |
163 | @ | |
1ec42c0c | 164 | disable_irq |
1da177e4 LT |
165 | |
166 | @ | |
167 | @ restore SPSR and restart the instruction | |
168 | @ | |
169 | ldr r0, [sp, #S_PSR] | |
170 | msr spsr_cxsf, r0 | |
171 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
172 | ||
173 | .align 5 | |
174 | __irq_svc: | |
ccea7a19 RK |
175 | svc_entry |
176 | ||
1da177e4 | 177 | #ifdef CONFIG_PREEMPT |
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178 | get_thread_info tsk |
179 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
180 | add r7, r8, #1 @ increment it | |
181 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 182 | #endif |
ccea7a19 | 183 | |
187a51ad | 184 | irq_handler |
1da177e4 | 185 | #ifdef CONFIG_PREEMPT |
706fdd9f | 186 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
1da177e4 LT |
187 | tst r0, #_TIF_NEED_RESCHED |
188 | blne svc_preempt | |
189 | preempt_return: | |
706fdd9f RK |
190 | ldr r0, [tsk, #TI_PREEMPT] @ read preempt value |
191 | str r8, [tsk, #TI_PREEMPT] @ restore preempt count | |
1da177e4 | 192 | teq r0, r7 |
1da177e4 LT |
193 | strne r0, [r0, -r0] @ bug() |
194 | #endif | |
195 | ldr r0, [sp, #S_PSR] @ irqs are already disabled | |
196 | msr spsr_cxsf, r0 | |
197 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
198 | ||
199 | .ltorg | |
200 | ||
201 | #ifdef CONFIG_PREEMPT | |
202 | svc_preempt: | |
706fdd9f | 203 | teq r8, #0 @ was preempt count = 0 |
1da177e4 LT |
204 | ldreq r6, .LCirq_stat |
205 | movne pc, lr @ no | |
206 | ldr r0, [r6, #4] @ local_irq_count | |
207 | ldr r1, [r6, #8] @ local_bh_count | |
208 | adds r0, r0, r1 | |
209 | movne pc, lr | |
210 | mov r7, #0 @ preempt_schedule_irq | |
706fdd9f | 211 | str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0 |
1da177e4 | 212 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 213 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 LT |
214 | tst r0, #_TIF_NEED_RESCHED |
215 | beq preempt_return @ go again | |
216 | b 1b | |
217 | #endif | |
218 | ||
219 | .align 5 | |
220 | __und_svc: | |
ccea7a19 | 221 | svc_entry |
1da177e4 LT |
222 | |
223 | @ | |
224 | @ call emulation code, which returns using r9 if it has emulated | |
225 | @ the instruction, or the more conventional lr if we are to treat | |
226 | @ this as a real undefined instruction | |
227 | @ | |
228 | @ r0 - instruction | |
229 | @ | |
230 | ldr r0, [r2, #-4] | |
231 | adr r9, 1f | |
232 | bl call_fpe | |
233 | ||
234 | mov r0, sp @ struct pt_regs *regs | |
235 | bl do_undefinstr | |
236 | ||
237 | @ | |
238 | @ IRQs off again before pulling preserved data off the stack | |
239 | @ | |
1ec42c0c | 240 | 1: disable_irq |
1da177e4 LT |
241 | |
242 | @ | |
243 | @ restore SPSR and restart the instruction | |
244 | @ | |
245 | ldr lr, [sp, #S_PSR] @ Get SVC cpsr | |
246 | msr spsr_cxsf, lr | |
247 | ldmia sp, {r0 - pc}^ @ Restore SVC registers | |
248 | ||
249 | .align 5 | |
250 | __pabt_svc: | |
ccea7a19 | 251 | svc_entry |
1da177e4 LT |
252 | |
253 | @ | |
254 | @ re-enable interrupts if appropriate | |
255 | @ | |
256 | mrs r9, cpsr | |
257 | tst r3, #PSR_I_BIT | |
258 | biceq r9, r9, #PSR_I_BIT | |
259 | msr cpsr_c, r9 | |
260 | ||
261 | @ | |
262 | @ set args, then call main handler | |
263 | @ | |
264 | @ r0 - address of faulting instruction | |
265 | @ r1 - pointer to registers on stack | |
266 | @ | |
267 | mov r0, r2 @ address (pc) | |
268 | mov r1, sp @ regs | |
269 | bl do_PrefetchAbort @ call abort handler | |
270 | ||
271 | @ | |
272 | @ IRQs off again before pulling preserved data off the stack | |
273 | @ | |
1ec42c0c | 274 | disable_irq |
1da177e4 LT |
275 | |
276 | @ | |
277 | @ restore SPSR and restart the instruction | |
278 | @ | |
279 | ldr r0, [sp, #S_PSR] | |
280 | msr spsr_cxsf, r0 | |
281 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
282 | ||
283 | .align 5 | |
49f680ea RK |
284 | .LCcralign: |
285 | .word cr_alignment | |
1da177e4 LT |
286 | #ifdef MULTI_ABORT |
287 | .LCprocfns: | |
288 | .word processor | |
289 | #endif | |
290 | .LCfp: | |
291 | .word fp_enter | |
292 | #ifdef CONFIG_PREEMPT | |
293 | .LCirq_stat: | |
294 | .word irq_stat | |
295 | #endif | |
296 | ||
297 | /* | |
298 | * User mode handlers | |
299 | */ | |
ccea7a19 RK |
300 | .macro usr_entry |
301 | sub sp, sp, #S_FRAME_SIZE | |
302 | stmib sp, {r1 - r12} | |
303 | ||
304 | ldmia r0, {r1 - r3} | |
305 | add r0, sp, #S_PC @ here for interlock avoidance | |
306 | mov r4, #-1 @ "" "" "" "" | |
307 | ||
308 | str r1, [sp] @ save the "real" r0 copied | |
309 | @ from the exception stack | |
1da177e4 | 310 | |
dcef1f63 | 311 | #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 NP |
312 | @ make sure our user space atomic helper is aborted |
313 | cmp r2, #VIRT_OFFSET | |
314 | bichs r3, r3, #PSR_Z_BIT | |
315 | #endif | |
316 | ||
1da177e4 LT |
317 | @ |
318 | @ We are now ready to fill in the remaining blanks on the stack: | |
319 | @ | |
320 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
321 | @ r3 - spsr_<exception> | |
322 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
323 | @ | |
324 | @ Also, separately save sp_usr and lr_usr | |
325 | @ | |
ccea7a19 RK |
326 | stmia r0, {r2 - r4} |
327 | stmdb r0, {sp, lr}^ | |
1da177e4 LT |
328 | |
329 | @ | |
330 | @ Enable the alignment trap while in kernel mode | |
331 | @ | |
49f680ea | 332 | alignment_trap r0 |
1da177e4 LT |
333 | |
334 | @ | |
335 | @ Clear FP to mark the first stack frame | |
336 | @ | |
337 | zero_fp | |
338 | .endm | |
339 | ||
340 | .align 5 | |
341 | __dabt_usr: | |
ccea7a19 | 342 | usr_entry |
1da177e4 LT |
343 | |
344 | @ | |
345 | @ Call the processor-specific abort handler: | |
346 | @ | |
347 | @ r2 - aborted context pc | |
348 | @ r3 - aborted context cpsr | |
349 | @ | |
350 | @ The abort handler must return the aborted address in r0, and | |
351 | @ the fault status register in r1. | |
352 | @ | |
353 | #ifdef MULTI_ABORT | |
354 | ldr r4, .LCprocfns | |
355 | mov lr, pc | |
356 | ldr pc, [r4] | |
357 | #else | |
358 | bl CPU_ABORT_HANDLER | |
359 | #endif | |
360 | ||
361 | @ | |
362 | @ IRQs on, then call the main handler | |
363 | @ | |
1ec42c0c | 364 | enable_irq |
1da177e4 LT |
365 | mov r2, sp |
366 | adr lr, ret_from_exception | |
367 | b do_DataAbort | |
368 | ||
369 | .align 5 | |
370 | __irq_usr: | |
ccea7a19 | 371 | usr_entry |
1da177e4 | 372 | |
706fdd9f | 373 | get_thread_info tsk |
1da177e4 | 374 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
375 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count |
376 | add r7, r8, #1 @ increment it | |
377 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 378 | #endif |
ccea7a19 | 379 | |
187a51ad | 380 | irq_handler |
1da177e4 | 381 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
382 | ldr r0, [tsk, #TI_PREEMPT] |
383 | str r8, [tsk, #TI_PREEMPT] | |
1da177e4 | 384 | teq r0, r7 |
1da177e4 | 385 | strne r0, [r0, -r0] |
1da177e4 | 386 | #endif |
ccea7a19 | 387 | |
1da177e4 LT |
388 | mov why, #0 |
389 | b ret_to_user | |
390 | ||
391 | .ltorg | |
392 | ||
393 | .align 5 | |
394 | __und_usr: | |
ccea7a19 | 395 | usr_entry |
1da177e4 LT |
396 | |
397 | tst r3, #PSR_T_BIT @ Thumb mode? | |
398 | bne fpundefinstr @ ignore FP | |
399 | sub r4, r2, #4 | |
400 | ||
401 | @ | |
402 | @ fall through to the emulation code, which returns using r9 if | |
403 | @ it has emulated the instruction, or the more conventional lr | |
404 | @ if we are to treat this as a real undefined instruction | |
405 | @ | |
406 | @ r0 - instruction | |
407 | @ | |
408 | 1: ldrt r0, [r4] | |
409 | adr r9, ret_from_exception | |
410 | adr lr, fpundefinstr | |
411 | @ | |
412 | @ fallthrough to call_fpe | |
413 | @ | |
414 | ||
415 | /* | |
416 | * The out of line fixup for the ldrt above. | |
417 | */ | |
418 | .section .fixup, "ax" | |
419 | 2: mov pc, r9 | |
420 | .previous | |
421 | .section __ex_table,"a" | |
422 | .long 1b, 2b | |
423 | .previous | |
424 | ||
425 | /* | |
426 | * Check whether the instruction is a co-processor instruction. | |
427 | * If yes, we need to call the relevant co-processor handler. | |
428 | * | |
429 | * Note that we don't do a full check here for the co-processor | |
430 | * instructions; all instructions with bit 27 set are well | |
431 | * defined. The only instructions that should fault are the | |
432 | * co-processor instructions. However, we have to watch out | |
433 | * for the ARM6/ARM7 SWI bug. | |
434 | * | |
435 | * Emulators may wish to make use of the following registers: | |
436 | * r0 = instruction opcode. | |
437 | * r2 = PC+4 | |
438 | * r10 = this threads thread_info structure. | |
439 | */ | |
440 | call_fpe: | |
441 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 | |
442 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) | |
443 | and r8, r0, #0x0f000000 @ mask out op-code bits | |
444 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | |
445 | #endif | |
446 | moveq pc, lr | |
447 | get_thread_info r10 @ get current thread | |
448 | and r8, r0, #0x00000f00 @ mask out CP number | |
449 | mov r7, #1 | |
450 | add r6, r10, #TI_USED_CP | |
451 | strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[] | |
452 | #ifdef CONFIG_IWMMXT | |
453 | @ Test if we need to give access to iWMMXt coprocessors | |
454 | ldr r5, [r10, #TI_FLAGS] | |
455 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
456 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
457 | bcs iwmmxt_task_enable | |
458 | #endif | |
1ec42c0c | 459 | enable_irq |
1da177e4 LT |
460 | add pc, pc, r8, lsr #6 |
461 | mov r0, r0 | |
462 | ||
463 | mov pc, lr @ CP#0 | |
464 | b do_fpe @ CP#1 (FPE) | |
465 | b do_fpe @ CP#2 (FPE) | |
466 | mov pc, lr @ CP#3 | |
467 | mov pc, lr @ CP#4 | |
468 | mov pc, lr @ CP#5 | |
469 | mov pc, lr @ CP#6 | |
470 | mov pc, lr @ CP#7 | |
471 | mov pc, lr @ CP#8 | |
472 | mov pc, lr @ CP#9 | |
473 | #ifdef CONFIG_VFP | |
474 | b do_vfp @ CP#10 (VFP) | |
475 | b do_vfp @ CP#11 (VFP) | |
476 | #else | |
477 | mov pc, lr @ CP#10 (VFP) | |
478 | mov pc, lr @ CP#11 (VFP) | |
479 | #endif | |
480 | mov pc, lr @ CP#12 | |
481 | mov pc, lr @ CP#13 | |
482 | mov pc, lr @ CP#14 (Debug) | |
483 | mov pc, lr @ CP#15 (Control) | |
484 | ||
485 | do_fpe: | |
486 | ldr r4, .LCfp | |
487 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
488 | ldr pc, [r4] @ Call FP module USR entry point | |
489 | ||
490 | /* | |
491 | * The FP module is called with these registers set: | |
492 | * r0 = instruction | |
493 | * r2 = PC+4 | |
494 | * r9 = normal "successful" return address | |
495 | * r10 = FP workspace | |
496 | * lr = unrecognised FP instruction return address | |
497 | */ | |
498 | ||
499 | .data | |
500 | ENTRY(fp_enter) | |
501 | .word fpundefinstr | |
502 | .text | |
503 | ||
504 | fpundefinstr: | |
505 | mov r0, sp | |
506 | adr lr, ret_from_exception | |
507 | b do_undefinstr | |
508 | ||
509 | .align 5 | |
510 | __pabt_usr: | |
ccea7a19 | 511 | usr_entry |
1da177e4 | 512 | |
1ec42c0c | 513 | enable_irq @ Enable interrupts |
1da177e4 LT |
514 | mov r0, r2 @ address (pc) |
515 | mov r1, sp @ regs | |
516 | bl do_PrefetchAbort @ call abort handler | |
517 | /* fall through */ | |
518 | /* | |
519 | * This is the return code to user mode for abort handlers | |
520 | */ | |
521 | ENTRY(ret_from_exception) | |
522 | get_thread_info tsk | |
523 | mov why, #0 | |
524 | b ret_to_user | |
525 | ||
526 | /* | |
527 | * Register switch for ARMv3 and ARMv4 processors | |
528 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
529 | * previous and next are guaranteed not to be the same. | |
530 | */ | |
531 | ENTRY(__switch_to) | |
532 | add ip, r1, #TI_CPU_SAVE | |
533 | ldr r3, [r2, #TI_TP_VALUE] | |
534 | stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack | |
535 | ldr r6, [r2, #TI_CPU_DOMAIN]! | |
b876386e RK |
536 | #if __LINUX_ARM_ARCH__ >= 6 |
537 | #ifdef CONFIG_CPU_MPCORE | |
538 | clrex | |
539 | #else | |
73394322 | 540 | strex r5, r4, [ip] @ Clear exclusive monitor |
b876386e RK |
541 | #endif |
542 | #endif | |
1da177e4 LT |
543 | #if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT) |
544 | mra r4, r5, acc0 | |
545 | stmia ip, {r4, r5} | |
546 | #endif | |
4b0e07a5 | 547 | #if defined(CONFIG_HAS_TLS_REG) |
2d2669b6 | 548 | mcr p15, 0, r3, c13, c0, 3 @ set TLS register |
4b0e07a5 | 549 | #elif !defined(CONFIG_TLS_REG_EMUL) |
1da177e4 | 550 | mov r4, #0xffff0fff |
2d2669b6 NP |
551 | str r3, [r4, #-15] @ TLS val at 0xffff0ff0 |
552 | #endif | |
1da177e4 LT |
553 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
554 | #ifdef CONFIG_VFP | |
555 | @ Always disable VFP so we can lazily save/restore the old | |
556 | @ state. This occurs in the context of the previous thread. | |
557 | VFPFMRX r4, FPEXC | |
558 | bic r4, r4, #FPEXC_ENABLE | |
559 | VFPFMXR FPEXC, r4 | |
560 | #endif | |
561 | #if defined(CONFIG_IWMMXT) | |
562 | bl iwmmxt_task_switch | |
563 | #elif defined(CONFIG_CPU_XSCALE) | |
564 | add r4, r2, #40 @ cpu_context_save->extra | |
565 | ldmib r4, {r4, r5} | |
566 | mar acc0, r4, r5 | |
567 | #endif | |
568 | ldmib r2, {r4 - sl, fp, sp, pc} @ Load all regs saved previously | |
569 | ||
570 | __INIT | |
2d2669b6 NP |
571 | |
572 | /* | |
573 | * User helpers. | |
574 | * | |
575 | * These are segment of kernel provided user code reachable from user space | |
576 | * at a fixed address in kernel memory. This is used to provide user space | |
577 | * with some operations which require kernel help because of unimplemented | |
578 | * native feature and/or instructions in many ARM CPUs. The idea is for | |
579 | * this code to be executed directly in user mode for best efficiency but | |
580 | * which is too intimate with the kernel counter part to be left to user | |
581 | * libraries. In fact this code might even differ from one CPU to another | |
582 | * depending on the available instruction set and restrictions like on | |
583 | * SMP systems. In other words, the kernel reserves the right to change | |
584 | * this code as needed without warning. Only the entry points and their | |
585 | * results are guaranteed to be stable. | |
586 | * | |
587 | * Each segment is 32-byte aligned and will be moved to the top of the high | |
588 | * vector page. New segments (if ever needed) must be added in front of | |
589 | * existing ones. This mechanism should be used only for things that are | |
590 | * really small and justified, and not be abused freely. | |
591 | * | |
592 | * User space is expected to implement those things inline when optimizing | |
593 | * for a processor that has the necessary native support, but only if such | |
594 | * resulting binaries are already to be incompatible with earlier ARM | |
595 | * processors due to the use of unsupported instructions other than what | |
596 | * is provided here. In other words don't make binaries unable to run on | |
597 | * earlier processors just for the sake of not using these kernel helpers | |
598 | * if your compiled code is not going to use the new instructions for other | |
599 | * purpose. | |
600 | */ | |
601 | ||
602 | .align 5 | |
603 | .globl __kuser_helper_start | |
604 | __kuser_helper_start: | |
605 | ||
606 | /* | |
607 | * Reference prototype: | |
608 | * | |
609 | * int __kernel_cmpxchg(int oldval, int newval, int *ptr) | |
610 | * | |
611 | * Input: | |
612 | * | |
613 | * r0 = oldval | |
614 | * r1 = newval | |
615 | * r2 = ptr | |
616 | * lr = return address | |
617 | * | |
618 | * Output: | |
619 | * | |
620 | * r0 = returned value (zero or non-zero) | |
621 | * C flag = set if r0 == 0, clear if r0 != 0 | |
622 | * | |
623 | * Clobbered: | |
624 | * | |
625 | * r3, ip, flags | |
626 | * | |
627 | * Definition and user space usage example: | |
628 | * | |
629 | * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); | |
630 | * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) | |
631 | * | |
632 | * Atomically store newval in *ptr if *ptr is equal to oldval for user space. | |
633 | * Return zero if *ptr was changed or non-zero if no exchange happened. | |
634 | * The C flag is also set if *ptr was changed to allow for assembly | |
635 | * optimization in the calling code. | |
636 | * | |
637 | * For example, a user space atomic_add implementation could look like this: | |
638 | * | |
639 | * #define atomic_add(ptr, val) \ | |
640 | * ({ register unsigned int *__ptr asm("r2") = (ptr); \ | |
641 | * register unsigned int __result asm("r1"); \ | |
642 | * asm volatile ( \ | |
643 | * "1: @ atomic_add\n\t" \ | |
644 | * "ldr r0, [r2]\n\t" \ | |
645 | * "mov r3, #0xffff0fff\n\t" \ | |
646 | * "add lr, pc, #4\n\t" \ | |
647 | * "add r1, r0, %2\n\t" \ | |
648 | * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ | |
649 | * "bcc 1b" \ | |
650 | * : "=&r" (__result) \ | |
651 | * : "r" (__ptr), "rIL" (val) \ | |
652 | * : "r0","r3","ip","lr","cc","memory" ); \ | |
653 | * __result; }) | |
654 | */ | |
655 | ||
656 | __kuser_cmpxchg: @ 0xffff0fc0 | |
657 | ||
dcef1f63 | 658 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 659 | |
dcef1f63 NP |
660 | /* |
661 | * Poor you. No fast solution possible... | |
662 | * The kernel itself must perform the operation. | |
663 | * A special ghost syscall is used for that (see traps.c). | |
664 | */ | |
665 | swi #0x9ffff0 | |
666 | mov pc, lr | |
667 | ||
668 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 NP |
669 | |
670 | /* | |
671 | * Theory of operation: | |
672 | * | |
673 | * We set the Z flag before loading oldval. If ever an exception | |
674 | * occurs we can not be sure the loaded value will still be the same | |
675 | * when the exception returns, therefore the user exception handler | |
676 | * will clear the Z flag whenever the interrupted user code was | |
677 | * actually from the kernel address space (see the usr_entry macro). | |
678 | * | |
679 | * The post-increment on the str is used to prevent a race with an | |
680 | * exception happening just after the str instruction which would | |
681 | * clear the Z flag although the exchange was done. | |
682 | */ | |
683 | teq ip, ip @ set Z flag | |
684 | ldr ip, [r2] @ load current val | |
685 | add r3, r2, #1 @ prepare store ptr | |
686 | teqeq ip, r0 @ compare with oldval if still allowed | |
687 | streq r1, [r3, #-1]! @ store newval if still allowed | |
688 | subs r0, r2, r3 @ if r2 == r3 the str occured | |
689 | mov pc, lr | |
690 | ||
691 | #else | |
692 | ||
693 | ldrex r3, [r2] | |
694 | subs r3, r3, r0 | |
695 | strexeq r3, r1, [r2] | |
696 | rsbs r0, r3, #0 | |
697 | mov pc, lr | |
698 | ||
699 | #endif | |
700 | ||
701 | .align 5 | |
702 | ||
703 | /* | |
704 | * Reference prototype: | |
705 | * | |
706 | * int __kernel_get_tls(void) | |
707 | * | |
708 | * Input: | |
709 | * | |
710 | * lr = return address | |
711 | * | |
712 | * Output: | |
713 | * | |
714 | * r0 = TLS value | |
715 | * | |
716 | * Clobbered: | |
717 | * | |
718 | * the Z flag might be lost | |
719 | * | |
720 | * Definition and user space usage example: | |
721 | * | |
722 | * typedef int (__kernel_get_tls_t)(void); | |
723 | * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) | |
724 | * | |
725 | * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. | |
726 | * | |
727 | * This could be used as follows: | |
728 | * | |
729 | * #define __kernel_get_tls() \ | |
730 | * ({ register unsigned int __val asm("r0"); \ | |
731 | * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ | |
732 | * : "=r" (__val) : : "lr","cc" ); \ | |
733 | * __val; }) | |
734 | */ | |
735 | ||
736 | __kuser_get_tls: @ 0xffff0fe0 | |
737 | ||
4b0e07a5 | 738 | #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) |
2d2669b6 NP |
739 | |
740 | ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 | |
741 | mov pc, lr | |
742 | ||
743 | #else | |
744 | ||
745 | mrc p15, 0, r0, c13, c0, 3 @ read TLS register | |
746 | mov pc, lr | |
747 | ||
748 | #endif | |
749 | ||
750 | .rep 5 | |
751 | .word 0 @ pad up to __kuser_helper_version | |
752 | .endr | |
753 | ||
754 | /* | |
755 | * Reference declaration: | |
756 | * | |
757 | * extern unsigned int __kernel_helper_version; | |
758 | * | |
759 | * Definition and user space usage example: | |
760 | * | |
761 | * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) | |
762 | * | |
763 | * User space may read this to determine the curent number of helpers | |
764 | * available. | |
765 | */ | |
766 | ||
767 | __kuser_helper_version: @ 0xffff0ffc | |
768 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
769 | ||
770 | .globl __kuser_helper_end | |
771 | __kuser_helper_end: | |
772 | ||
773 | ||
1da177e4 LT |
774 | /* |
775 | * Vector stubs. | |
776 | * | |
7933523d RK |
777 | * This code is copied to 0xffff0200 so we can use branches in the |
778 | * vectors, rather than ldr's. Note that this code must not | |
779 | * exceed 0x300 bytes. | |
1da177e4 LT |
780 | * |
781 | * Common stub entry macro: | |
782 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
783 | * |
784 | * SP points to a minimal amount of processor-private memory, the address | |
785 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 786 | */ |
ccea7a19 | 787 | .macro vector_stub, name, correction=0 |
1da177e4 LT |
788 | .align 5 |
789 | ||
790 | vector_\name: | |
1da177e4 LT |
791 | .if \correction |
792 | sub lr, lr, #\correction | |
793 | .endif | |
ccea7a19 RK |
794 | |
795 | @ | |
796 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
797 | @ (parent CPSR) | |
798 | @ | |
799 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 800 | mrs lr, spsr |
ccea7a19 RK |
801 | str lr, [sp, #8] @ save spsr |
802 | ||
1da177e4 | 803 | @ |
ccea7a19 | 804 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 805 | @ |
ccea7a19 RK |
806 | mrs r0, cpsr |
807 | bic r0, r0, #MODE_MASK | |
808 | orr r0, r0, #SVC_MODE | |
809 | msr spsr_cxsf, r0 | |
1da177e4 | 810 | |
ccea7a19 RK |
811 | @ |
812 | @ the branch table must immediately follow this code | |
813 | @ | |
814 | mov r0, sp | |
815 | and lr, lr, #0x0f | |
1da177e4 | 816 | ldr lr, [pc, lr, lsl #2] |
ccea7a19 | 817 | movs pc, lr @ branch to handler in SVC mode |
1da177e4 LT |
818 | .endm |
819 | ||
7933523d | 820 | .globl __stubs_start |
1da177e4 LT |
821 | __stubs_start: |
822 | /* | |
823 | * Interrupt dispatcher | |
824 | */ | |
ccea7a19 | 825 | vector_stub irq, 4 |
1da177e4 LT |
826 | |
827 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
828 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
829 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
830 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
831 | .long __irq_invalid @ 4 | |
832 | .long __irq_invalid @ 5 | |
833 | .long __irq_invalid @ 6 | |
834 | .long __irq_invalid @ 7 | |
835 | .long __irq_invalid @ 8 | |
836 | .long __irq_invalid @ 9 | |
837 | .long __irq_invalid @ a | |
838 | .long __irq_invalid @ b | |
839 | .long __irq_invalid @ c | |
840 | .long __irq_invalid @ d | |
841 | .long __irq_invalid @ e | |
842 | .long __irq_invalid @ f | |
843 | ||
844 | /* | |
845 | * Data abort dispatcher | |
846 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
847 | */ | |
ccea7a19 | 848 | vector_stub dabt, 8 |
1da177e4 LT |
849 | |
850 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
851 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
852 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
853 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
854 | .long __dabt_invalid @ 4 | |
855 | .long __dabt_invalid @ 5 | |
856 | .long __dabt_invalid @ 6 | |
857 | .long __dabt_invalid @ 7 | |
858 | .long __dabt_invalid @ 8 | |
859 | .long __dabt_invalid @ 9 | |
860 | .long __dabt_invalid @ a | |
861 | .long __dabt_invalid @ b | |
862 | .long __dabt_invalid @ c | |
863 | .long __dabt_invalid @ d | |
864 | .long __dabt_invalid @ e | |
865 | .long __dabt_invalid @ f | |
866 | ||
867 | /* | |
868 | * Prefetch abort dispatcher | |
869 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
870 | */ | |
ccea7a19 | 871 | vector_stub pabt, 4 |
1da177e4 LT |
872 | |
873 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
874 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
875 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
876 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
877 | .long __pabt_invalid @ 4 | |
878 | .long __pabt_invalid @ 5 | |
879 | .long __pabt_invalid @ 6 | |
880 | .long __pabt_invalid @ 7 | |
881 | .long __pabt_invalid @ 8 | |
882 | .long __pabt_invalid @ 9 | |
883 | .long __pabt_invalid @ a | |
884 | .long __pabt_invalid @ b | |
885 | .long __pabt_invalid @ c | |
886 | .long __pabt_invalid @ d | |
887 | .long __pabt_invalid @ e | |
888 | .long __pabt_invalid @ f | |
889 | ||
890 | /* | |
891 | * Undef instr entry dispatcher | |
892 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
893 | */ | |
ccea7a19 | 894 | vector_stub und |
1da177e4 LT |
895 | |
896 | .long __und_usr @ 0 (USR_26 / USR_32) | |
897 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
898 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
899 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
900 | .long __und_invalid @ 4 | |
901 | .long __und_invalid @ 5 | |
902 | .long __und_invalid @ 6 | |
903 | .long __und_invalid @ 7 | |
904 | .long __und_invalid @ 8 | |
905 | .long __und_invalid @ 9 | |
906 | .long __und_invalid @ a | |
907 | .long __und_invalid @ b | |
908 | .long __und_invalid @ c | |
909 | .long __und_invalid @ d | |
910 | .long __und_invalid @ e | |
911 | .long __und_invalid @ f | |
912 | ||
913 | .align 5 | |
914 | ||
915 | /*============================================================================= | |
916 | * Undefined FIQs | |
917 | *----------------------------------------------------------------------------- | |
918 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC | |
919 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. | |
920 | * Basically to switch modes, we *HAVE* to clobber one register... brain | |
921 | * damage alert! I don't think that we can execute any code in here in any | |
922 | * other mode than FIQ... Ok you can switch to another mode, but you can't | |
923 | * get out of that mode without clobbering one register. | |
924 | */ | |
925 | vector_fiq: | |
926 | disable_fiq | |
927 | subs pc, lr, #4 | |
928 | ||
929 | /*============================================================================= | |
930 | * Address exception handler | |
931 | *----------------------------------------------------------------------------- | |
932 | * These aren't too critical. | |
933 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
934 | */ | |
935 | ||
936 | vector_addrexcptn: | |
937 | b vector_addrexcptn | |
938 | ||
939 | /* | |
940 | * We group all the following data together to optimise | |
941 | * for CPUs with separate I & D caches. | |
942 | */ | |
943 | .align 5 | |
944 | ||
945 | .LCvswi: | |
946 | .word vector_swi | |
947 | ||
7933523d | 948 | .globl __stubs_end |
1da177e4 LT |
949 | __stubs_end: |
950 | ||
7933523d | 951 | .equ stubs_offset, __vectors_start + 0x200 - __stubs_start |
1da177e4 | 952 | |
7933523d RK |
953 | .globl __vectors_start |
954 | __vectors_start: | |
1da177e4 | 955 | swi SYS_ERROR0 |
7933523d RK |
956 | b vector_und + stubs_offset |
957 | ldr pc, .LCvswi + stubs_offset | |
958 | b vector_pabt + stubs_offset | |
959 | b vector_dabt + stubs_offset | |
960 | b vector_addrexcptn + stubs_offset | |
961 | b vector_irq + stubs_offset | |
962 | b vector_fiq + stubs_offset | |
963 | ||
964 | .globl __vectors_end | |
965 | __vectors_end: | |
1da177e4 LT |
966 | |
967 | .data | |
968 | ||
1da177e4 LT |
969 | .globl cr_alignment |
970 | .globl cr_no_alignment | |
971 | cr_alignment: | |
972 | .space 4 | |
973 | cr_no_alignment: | |
974 | .space 4 |