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75d90832 HC |
1 | /* |
2 | * linux/arch/arm/kernel/head-nommu.S | |
3 | * | |
4 | * Copyright (C) 1994-2002 Russell King | |
5 | * Copyright (C) 2003-2006 Hyok S. Choi | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * Common kernel startup code (non-paged MM) | |
75d90832 HC |
12 | * |
13 | */ | |
75d90832 HC |
14 | #include <linux/linkage.h> |
15 | #include <linux/init.h> | |
16 | ||
17 | #include <asm/assembler.h> | |
75d90832 | 18 | #include <asm/ptrace.h> |
2eb9d315 | 19 | #include <asm/asm-offsets.h> |
15d07dc9 | 20 | #include <asm/cp15.h> |
3b920cef | 21 | #include <asm/thread_info.h> |
55bdd694 | 22 | #include <asm/v7m.h> |
75d90832 | 23 | |
75d90832 HC |
24 | /* |
25 | * Kernel startup entry point. | |
26 | * --------------------------- | |
27 | * | |
28 | * This is normally called from the decompressor code. The requirements | |
29 | * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, | |
30 | * r1 = machine nr. | |
31 | * | |
32 | * See linux/arch/arm/tools/mach-types for the complete list of machine | |
33 | * numbers for r1. | |
34 | * | |
35 | */ | |
540b5738 | 36 | |
2abc1c50 | 37 | __HEAD |
bc7dea00 UKK |
38 | |
39 | #ifdef CONFIG_CPU_THUMBONLY | |
40 | .thumb | |
41 | ENTRY(stext) | |
42 | #else | |
43 | .arm | |
75d90832 | 44 | ENTRY(stext) |
540b5738 DM |
45 | |
46 | THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. | |
47 | THUMB( bx r9 ) @ If this is a Thumb-2 kernel, | |
48 | THUMB( .thumb ) @ switch to Thumb now. | |
49 | THUMB(1: ) | |
bc7dea00 | 50 | #endif |
540b5738 | 51 | |
b86040a5 | 52 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode |
75d90832 | 53 | @ and irqs disabled |
55bdd694 | 54 | #if defined(CONFIG_CPU_CP15) |
75d90832 | 55 | mrc p15, 0, r9, c0, c0 @ get processor id |
55bdd694 CM |
56 | #elif defined(CONFIG_CPU_V7M) |
57 | ldr r9, =BASEADDR_V7M_SCB | |
58 | ldr r9, [r9, V7M_SCB_CPUID] | |
59 | #else | |
60 | ldr r9, =CONFIG_PROCESSOR_ID | |
f12d0d7c | 61 | #endif |
75d90832 HC |
62 | bl __lookup_processor_type @ r5=procinfo r9=cpuid |
63 | movs r10, r5 @ invalid processor (r5=0)? | |
64 | beq __error_p @ yes, error 'p' | |
75d90832 | 65 | |
b86040a5 CM |
66 | adr lr, BSYM(__after_proc_init) @ return (PIC) address |
67 | ARM( add pc, r10, #PROCINFO_INITFUNC ) | |
68 | THUMB( add r12, r10, #PROCINFO_INITFUNC ) | |
69 | THUMB( mov pc, r12 ) | |
93ed3970 | 70 | ENDPROC(stext) |
75d90832 HC |
71 | |
72 | /* | |
73 | * Set the Control Register and Read the process ID. | |
74 | */ | |
75d90832 | 75 | __after_proc_init: |
f12d0d7c | 76 | #ifdef CONFIG_CPU_CP15 |
05efde9d CM |
77 | /* |
78 | * CP15 system control register value returned in r0 from | |
79 | * the CPU init function. | |
80 | */ | |
76e09204 | 81 | #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 |
75d90832 HC |
82 | orr r0, r0, #CR_A |
83 | #else | |
84 | bic r0, r0, #CR_A | |
85 | #endif | |
86 | #ifdef CONFIG_CPU_DCACHE_DISABLE | |
87 | bic r0, r0, #CR_C | |
88 | #endif | |
89 | #ifdef CONFIG_CPU_BPREDICT_DISABLE | |
90 | bic r0, r0, #CR_Z | |
91 | #endif | |
92 | #ifdef CONFIG_CPU_ICACHE_DISABLE | |
93 | bic r0, r0, #CR_I | |
6afd6fae HC |
94 | #endif |
95 | #ifdef CONFIG_CPU_HIGH_VECTOR | |
96 | orr r0, r0, #CR_V | |
97 | #else | |
98 | bic r0, r0, #CR_V | |
75d90832 HC |
99 | #endif |
100 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
f12d0d7c | 101 | #endif /* CONFIG_CPU_CP15 */ |
75d90832 | 102 | |
f131a080 | 103 | b __mmap_switched @ clear the BSS and jump |
75d90832 | 104 | @ to start_kernel |
93ed3970 | 105 | ENDPROC(__after_proc_init) |
3b920cef | 106 | .ltorg |
75d90832 HC |
107 | |
108 | #include "head-common.S" |