Commit | Line | Data |
---|---|---|
f81ef4a9 WD |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License version 2 as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
14 | * | |
15 | * Copyright (C) 2009, 2010 ARM Limited | |
16 | * | |
17 | * Author: Will Deacon <will.deacon@arm.com> | |
18 | */ | |
19 | ||
20 | /* | |
21 | * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility, | |
22 | * using the CPU's debug registers. | |
23 | */ | |
24 | #define pr_fmt(fmt) "hw-breakpoint: " fmt | |
25 | ||
26 | #include <linux/errno.h> | |
7e202696 | 27 | #include <linux/hardirq.h> |
f81ef4a9 WD |
28 | #include <linux/perf_event.h> |
29 | #include <linux/hw_breakpoint.h> | |
30 | #include <linux/smp.h> | |
31 | ||
32 | #include <asm/cacheflush.h> | |
33 | #include <asm/cputype.h> | |
34 | #include <asm/current.h> | |
35 | #include <asm/hw_breakpoint.h> | |
36 | #include <asm/kdebug.h> | |
37 | #include <asm/system.h> | |
38 | #include <asm/traps.h> | |
39 | ||
40 | /* Breakpoint currently in use for each BRP. */ | |
41 | static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]); | |
42 | ||
43 | /* Watchpoint currently in use for each WRP. */ | |
44 | static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]); | |
45 | ||
46 | /* Number of BRP/WRP registers on this CPU. */ | |
47 | static int core_num_brps; | |
0017ff42 | 48 | static int core_num_reserved_brps; |
f81ef4a9 WD |
49 | static int core_num_wrps; |
50 | ||
51 | /* Debug architecture version. */ | |
52 | static u8 debug_arch; | |
53 | ||
54 | /* Maximum supported watchpoint length. */ | |
55 | static u8 max_watchpoint_len; | |
56 | ||
f81ef4a9 WD |
57 | #define READ_WB_REG_CASE(OP2, M, VAL) \ |
58 | case ((OP2 << 4) + M): \ | |
59 | ARM_DBG_READ(c ## M, OP2, VAL); \ | |
60 | break | |
61 | ||
62 | #define WRITE_WB_REG_CASE(OP2, M, VAL) \ | |
63 | case ((OP2 << 4) + M): \ | |
64 | ARM_DBG_WRITE(c ## M, OP2, VAL);\ | |
65 | break | |
66 | ||
67 | #define GEN_READ_WB_REG_CASES(OP2, VAL) \ | |
68 | READ_WB_REG_CASE(OP2, 0, VAL); \ | |
69 | READ_WB_REG_CASE(OP2, 1, VAL); \ | |
70 | READ_WB_REG_CASE(OP2, 2, VAL); \ | |
71 | READ_WB_REG_CASE(OP2, 3, VAL); \ | |
72 | READ_WB_REG_CASE(OP2, 4, VAL); \ | |
73 | READ_WB_REG_CASE(OP2, 5, VAL); \ | |
74 | READ_WB_REG_CASE(OP2, 6, VAL); \ | |
75 | READ_WB_REG_CASE(OP2, 7, VAL); \ | |
76 | READ_WB_REG_CASE(OP2, 8, VAL); \ | |
77 | READ_WB_REG_CASE(OP2, 9, VAL); \ | |
78 | READ_WB_REG_CASE(OP2, 10, VAL); \ | |
79 | READ_WB_REG_CASE(OP2, 11, VAL); \ | |
80 | READ_WB_REG_CASE(OP2, 12, VAL); \ | |
81 | READ_WB_REG_CASE(OP2, 13, VAL); \ | |
82 | READ_WB_REG_CASE(OP2, 14, VAL); \ | |
83 | READ_WB_REG_CASE(OP2, 15, VAL) | |
84 | ||
85 | #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \ | |
86 | WRITE_WB_REG_CASE(OP2, 0, VAL); \ | |
87 | WRITE_WB_REG_CASE(OP2, 1, VAL); \ | |
88 | WRITE_WB_REG_CASE(OP2, 2, VAL); \ | |
89 | WRITE_WB_REG_CASE(OP2, 3, VAL); \ | |
90 | WRITE_WB_REG_CASE(OP2, 4, VAL); \ | |
91 | WRITE_WB_REG_CASE(OP2, 5, VAL); \ | |
92 | WRITE_WB_REG_CASE(OP2, 6, VAL); \ | |
93 | WRITE_WB_REG_CASE(OP2, 7, VAL); \ | |
94 | WRITE_WB_REG_CASE(OP2, 8, VAL); \ | |
95 | WRITE_WB_REG_CASE(OP2, 9, VAL); \ | |
96 | WRITE_WB_REG_CASE(OP2, 10, VAL); \ | |
97 | WRITE_WB_REG_CASE(OP2, 11, VAL); \ | |
98 | WRITE_WB_REG_CASE(OP2, 12, VAL); \ | |
99 | WRITE_WB_REG_CASE(OP2, 13, VAL); \ | |
100 | WRITE_WB_REG_CASE(OP2, 14, VAL); \ | |
101 | WRITE_WB_REG_CASE(OP2, 15, VAL) | |
102 | ||
103 | static u32 read_wb_reg(int n) | |
104 | { | |
105 | u32 val = 0; | |
106 | ||
107 | switch (n) { | |
108 | GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val); | |
109 | GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val); | |
110 | GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val); | |
111 | GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val); | |
112 | default: | |
113 | pr_warning("attempt to read from unknown breakpoint " | |
114 | "register %d\n", n); | |
115 | } | |
116 | ||
117 | return val; | |
118 | } | |
119 | ||
120 | static void write_wb_reg(int n, u32 val) | |
121 | { | |
122 | switch (n) { | |
123 | GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val); | |
124 | GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val); | |
125 | GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val); | |
126 | GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val); | |
127 | default: | |
128 | pr_warning("attempt to write to unknown breakpoint " | |
129 | "register %d\n", n); | |
130 | } | |
131 | isb(); | |
132 | } | |
133 | ||
0017ff42 WD |
134 | /* Determine debug architecture. */ |
135 | static u8 get_debug_arch(void) | |
136 | { | |
137 | u32 didr; | |
138 | ||
139 | /* Do we implement the extended CPUID interface? */ | |
140 | if (((read_cpuid_id() >> 16) & 0xf) != 0xf) { | |
141 | pr_warning("CPUID feature registers not supported. " | |
142 | "Assuming v6 debug is present.\n"); | |
143 | return ARM_DEBUG_ARCH_V6; | |
144 | } | |
145 | ||
146 | ARM_DBG_READ(c0, 0, didr); | |
147 | return (didr >> 16) & 0xf; | |
148 | } | |
149 | ||
150 | u8 arch_get_debug_arch(void) | |
151 | { | |
152 | return debug_arch; | |
153 | } | |
154 | ||
155 | /* Determine number of BRP register available. */ | |
156 | static int get_num_brp_resources(void) | |
157 | { | |
158 | u32 didr; | |
159 | ARM_DBG_READ(c0, 0, didr); | |
160 | return ((didr >> 24) & 0xf) + 1; | |
161 | } | |
162 | ||
163 | /* Does this core support mismatch breakpoints? */ | |
164 | static int core_has_mismatch_brps(void) | |
165 | { | |
166 | return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 && | |
167 | get_num_brp_resources() > 1); | |
168 | } | |
169 | ||
170 | /* Determine number of usable WRPs available. */ | |
171 | static int get_num_wrps(void) | |
172 | { | |
173 | /* | |
174 | * FIXME: When a watchpoint fires, the only way to work out which | |
175 | * watchpoint it was is by disassembling the faulting instruction | |
176 | * and working out the address of the memory access. | |
177 | * | |
178 | * Furthermore, we can only do this if the watchpoint was precise | |
179 | * since imprecise watchpoints prevent us from calculating register | |
180 | * based addresses. | |
181 | * | |
182 | * Providing we have more than 1 breakpoint register, we only report | |
183 | * a single watchpoint register for the time being. This way, we always | |
184 | * know which watchpoint fired. In the future we can either add a | |
185 | * disassembler and address generation emulator, or we can insert a | |
186 | * check to see if the DFAR is set on watchpoint exception entry | |
187 | * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows | |
188 | * that it is set on some implementations]. | |
189 | */ | |
190 | ||
191 | #if 0 | |
192 | int wrps; | |
193 | u32 didr; | |
194 | ARM_DBG_READ(c0, 0, didr); | |
195 | wrps = ((didr >> 28) & 0xf) + 1; | |
196 | #endif | |
197 | int wrps = 1; | |
198 | ||
199 | if (core_has_mismatch_brps() && wrps >= get_num_brp_resources()) | |
200 | wrps = get_num_brp_resources() - 1; | |
201 | ||
202 | return wrps; | |
203 | } | |
204 | ||
205 | /* We reserve one breakpoint for each watchpoint. */ | |
206 | static int get_num_reserved_brps(void) | |
207 | { | |
208 | if (core_has_mismatch_brps()) | |
209 | return get_num_wrps(); | |
210 | return 0; | |
211 | } | |
212 | ||
213 | /* Determine number of usable BRPs available. */ | |
214 | static int get_num_brps(void) | |
215 | { | |
216 | int brps = get_num_brp_resources(); | |
217 | if (core_has_mismatch_brps()) | |
218 | brps -= get_num_reserved_brps(); | |
219 | return brps; | |
220 | } | |
221 | ||
222 | int hw_breakpoint_slots(int type) | |
223 | { | |
224 | /* | |
225 | * We can be called early, so don't rely on | |
226 | * our static variables being initialised. | |
227 | */ | |
228 | switch (type) { | |
229 | case TYPE_INST: | |
230 | return get_num_brps(); | |
231 | case TYPE_DATA: | |
232 | return get_num_wrps(); | |
233 | default: | |
234 | pr_warning("unknown slot type: %d\n", type); | |
235 | return 0; | |
236 | } | |
237 | } | |
238 | ||
f81ef4a9 WD |
239 | /* |
240 | * In order to access the breakpoint/watchpoint control registers, | |
241 | * we must be running in debug monitor mode. Unfortunately, we can | |
242 | * be put into halting debug mode at any time by an external debugger | |
243 | * but there is nothing we can do to prevent that. | |
244 | */ | |
245 | static int enable_monitor_mode(void) | |
246 | { | |
247 | u32 dscr; | |
248 | int ret = 0; | |
249 | ||
250 | ARM_DBG_READ(c1, 0, dscr); | |
251 | ||
252 | /* Ensure that halting mode is disabled. */ | |
253 | if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, "halting debug mode enabled." | |
254 | "Unable to access hardware resources.")) { | |
255 | ret = -EPERM; | |
256 | goto out; | |
257 | } | |
258 | ||
259 | /* Write to the corresponding DSCR. */ | |
260 | switch (debug_arch) { | |
261 | case ARM_DEBUG_ARCH_V6: | |
262 | case ARM_DEBUG_ARCH_V6_1: | |
263 | ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN)); | |
264 | break; | |
265 | case ARM_DEBUG_ARCH_V7_ECP14: | |
266 | ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN)); | |
267 | break; | |
268 | default: | |
269 | ret = -ENODEV; | |
270 | goto out; | |
271 | } | |
272 | ||
273 | /* Check that the write made it through. */ | |
274 | ARM_DBG_READ(c1, 0, dscr); | |
275 | if (WARN_ONCE(!(dscr & ARM_DSCR_MDBGEN), | |
276 | "failed to enable monitor mode.")) { | |
277 | ret = -EPERM; | |
278 | } | |
279 | ||
280 | out: | |
281 | return ret; | |
282 | } | |
283 | ||
284 | /* | |
285 | * Check if 8-bit byte-address select is available. | |
286 | * This clobbers WRP 0. | |
287 | */ | |
288 | static u8 get_max_wp_len(void) | |
289 | { | |
290 | u32 ctrl_reg; | |
291 | struct arch_hw_breakpoint_ctrl ctrl; | |
292 | u8 size = 4; | |
293 | ||
294 | if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14) | |
295 | goto out; | |
296 | ||
297 | if (enable_monitor_mode()) | |
298 | goto out; | |
299 | ||
300 | memset(&ctrl, 0, sizeof(ctrl)); | |
301 | ctrl.len = ARM_BREAKPOINT_LEN_8; | |
302 | ctrl_reg = encode_ctrl_reg(ctrl); | |
303 | ||
304 | write_wb_reg(ARM_BASE_WVR, 0); | |
305 | write_wb_reg(ARM_BASE_WCR, ctrl_reg); | |
306 | if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg) | |
307 | size = 8; | |
308 | ||
309 | out: | |
310 | return size; | |
311 | } | |
312 | ||
313 | u8 arch_get_max_wp_len(void) | |
314 | { | |
315 | return max_watchpoint_len; | |
316 | } | |
317 | ||
f81ef4a9 WD |
318 | /* |
319 | * Install a perf counter breakpoint. | |
320 | */ | |
321 | int arch_install_hw_breakpoint(struct perf_event *bp) | |
322 | { | |
323 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
324 | struct perf_event **slot, **slots; | |
325 | int i, max_slots, ctrl_base, val_base, ret = 0; | |
93a04a34 | 326 | u32 addr, ctrl; |
f81ef4a9 WD |
327 | |
328 | /* Ensure that we are in monitor mode and halting mode is disabled. */ | |
329 | ret = enable_monitor_mode(); | |
330 | if (ret) | |
331 | goto out; | |
332 | ||
93a04a34 WD |
333 | addr = info->address; |
334 | ctrl = encode_ctrl_reg(info->ctrl) | 0x1; | |
335 | ||
f81ef4a9 WD |
336 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { |
337 | /* Breakpoint */ | |
338 | ctrl_base = ARM_BASE_BCR; | |
339 | val_base = ARM_BASE_BVR; | |
4a55c18e | 340 | slots = (struct perf_event **)__get_cpu_var(bp_on_reg); |
0017ff42 | 341 | max_slots = core_num_brps; |
9ebb3cbc WD |
342 | if (info->step_ctrl.enabled) { |
343 | /* Override the breakpoint data with the step data. */ | |
344 | addr = info->trigger & ~0x3; | |
345 | ctrl = encode_ctrl_reg(info->step_ctrl); | |
346 | } | |
f81ef4a9 WD |
347 | } else { |
348 | /* Watchpoint */ | |
93a04a34 WD |
349 | if (info->step_ctrl.enabled) { |
350 | /* Install into the reserved breakpoint region. */ | |
351 | ctrl_base = ARM_BASE_BCR + core_num_brps; | |
352 | val_base = ARM_BASE_BVR + core_num_brps; | |
353 | /* Override the watchpoint data with the step data. */ | |
354 | addr = info->trigger & ~0x3; | |
355 | ctrl = encode_ctrl_reg(info->step_ctrl); | |
356 | } else { | |
357 | ctrl_base = ARM_BASE_WCR; | |
358 | val_base = ARM_BASE_WVR; | |
359 | } | |
4a55c18e | 360 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); |
f81ef4a9 WD |
361 | max_slots = core_num_wrps; |
362 | } | |
363 | ||
364 | for (i = 0; i < max_slots; ++i) { | |
365 | slot = &slots[i]; | |
366 | ||
367 | if (!*slot) { | |
368 | *slot = bp; | |
369 | break; | |
370 | } | |
371 | } | |
372 | ||
373 | if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) { | |
374 | ret = -EBUSY; | |
375 | goto out; | |
376 | } | |
377 | ||
f81ef4a9 | 378 | /* Setup the address register. */ |
93a04a34 | 379 | write_wb_reg(val_base + i, addr); |
f81ef4a9 WD |
380 | |
381 | /* Setup the control register. */ | |
93a04a34 | 382 | write_wb_reg(ctrl_base + i, ctrl); |
f81ef4a9 WD |
383 | |
384 | out: | |
385 | return ret; | |
386 | } | |
387 | ||
388 | void arch_uninstall_hw_breakpoint(struct perf_event *bp) | |
389 | { | |
390 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
391 | struct perf_event **slot, **slots; | |
392 | int i, max_slots, base; | |
393 | ||
394 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { | |
395 | /* Breakpoint */ | |
396 | base = ARM_BASE_BCR; | |
4a55c18e | 397 | slots = (struct perf_event **)__get_cpu_var(bp_on_reg); |
0017ff42 | 398 | max_slots = core_num_brps; |
f81ef4a9 WD |
399 | } else { |
400 | /* Watchpoint */ | |
93a04a34 WD |
401 | if (info->step_ctrl.enabled) |
402 | base = ARM_BASE_BCR + core_num_brps; | |
403 | else | |
404 | base = ARM_BASE_WCR; | |
4a55c18e | 405 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); |
f81ef4a9 WD |
406 | max_slots = core_num_wrps; |
407 | } | |
408 | ||
409 | /* Remove the breakpoint. */ | |
410 | for (i = 0; i < max_slots; ++i) { | |
411 | slot = &slots[i]; | |
412 | ||
413 | if (*slot == bp) { | |
414 | *slot = NULL; | |
415 | break; | |
416 | } | |
417 | } | |
418 | ||
419 | if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) | |
420 | return; | |
421 | ||
f81ef4a9 WD |
422 | /* Reset the control register. */ |
423 | write_wb_reg(base + i, 0); | |
424 | } | |
425 | ||
426 | static int get_hbp_len(u8 hbp_len) | |
427 | { | |
428 | unsigned int len_in_bytes = 0; | |
429 | ||
430 | switch (hbp_len) { | |
431 | case ARM_BREAKPOINT_LEN_1: | |
432 | len_in_bytes = 1; | |
433 | break; | |
434 | case ARM_BREAKPOINT_LEN_2: | |
435 | len_in_bytes = 2; | |
436 | break; | |
437 | case ARM_BREAKPOINT_LEN_4: | |
438 | len_in_bytes = 4; | |
439 | break; | |
440 | case ARM_BREAKPOINT_LEN_8: | |
441 | len_in_bytes = 8; | |
442 | break; | |
443 | } | |
444 | ||
445 | return len_in_bytes; | |
446 | } | |
447 | ||
448 | /* | |
449 | * Check whether bp virtual address is in kernel space. | |
450 | */ | |
451 | int arch_check_bp_in_kernelspace(struct perf_event *bp) | |
452 | { | |
453 | unsigned int len; | |
454 | unsigned long va; | |
455 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
456 | ||
457 | va = info->address; | |
458 | len = get_hbp_len(info->ctrl.len); | |
459 | ||
460 | return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE); | |
461 | } | |
462 | ||
463 | /* | |
464 | * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl. | |
465 | * Hopefully this will disappear when ptrace can bypass the conversion | |
466 | * to generic breakpoint descriptions. | |
467 | */ | |
468 | int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, | |
469 | int *gen_len, int *gen_type) | |
470 | { | |
471 | /* Type */ | |
472 | switch (ctrl.type) { | |
473 | case ARM_BREAKPOINT_EXECUTE: | |
474 | *gen_type = HW_BREAKPOINT_X; | |
475 | break; | |
476 | case ARM_BREAKPOINT_LOAD: | |
477 | *gen_type = HW_BREAKPOINT_R; | |
478 | break; | |
479 | case ARM_BREAKPOINT_STORE: | |
480 | *gen_type = HW_BREAKPOINT_W; | |
481 | break; | |
482 | case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE: | |
483 | *gen_type = HW_BREAKPOINT_RW; | |
484 | break; | |
485 | default: | |
486 | return -EINVAL; | |
487 | } | |
488 | ||
489 | /* Len */ | |
490 | switch (ctrl.len) { | |
491 | case ARM_BREAKPOINT_LEN_1: | |
492 | *gen_len = HW_BREAKPOINT_LEN_1; | |
493 | break; | |
494 | case ARM_BREAKPOINT_LEN_2: | |
495 | *gen_len = HW_BREAKPOINT_LEN_2; | |
496 | break; | |
497 | case ARM_BREAKPOINT_LEN_4: | |
498 | *gen_len = HW_BREAKPOINT_LEN_4; | |
499 | break; | |
500 | case ARM_BREAKPOINT_LEN_8: | |
501 | *gen_len = HW_BREAKPOINT_LEN_8; | |
502 | break; | |
503 | default: | |
504 | return -EINVAL; | |
505 | } | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | /* | |
511 | * Construct an arch_hw_breakpoint from a perf_event. | |
512 | */ | |
513 | static int arch_build_bp_info(struct perf_event *bp) | |
514 | { | |
515 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
516 | ||
517 | /* Type */ | |
518 | switch (bp->attr.bp_type) { | |
519 | case HW_BREAKPOINT_X: | |
520 | info->ctrl.type = ARM_BREAKPOINT_EXECUTE; | |
521 | break; | |
522 | case HW_BREAKPOINT_R: | |
523 | info->ctrl.type = ARM_BREAKPOINT_LOAD; | |
524 | break; | |
525 | case HW_BREAKPOINT_W: | |
526 | info->ctrl.type = ARM_BREAKPOINT_STORE; | |
527 | break; | |
528 | case HW_BREAKPOINT_RW: | |
529 | info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; | |
530 | break; | |
531 | default: | |
532 | return -EINVAL; | |
533 | } | |
534 | ||
535 | /* Len */ | |
536 | switch (bp->attr.bp_len) { | |
537 | case HW_BREAKPOINT_LEN_1: | |
538 | info->ctrl.len = ARM_BREAKPOINT_LEN_1; | |
539 | break; | |
540 | case HW_BREAKPOINT_LEN_2: | |
541 | info->ctrl.len = ARM_BREAKPOINT_LEN_2; | |
542 | break; | |
543 | case HW_BREAKPOINT_LEN_4: | |
544 | info->ctrl.len = ARM_BREAKPOINT_LEN_4; | |
545 | break; | |
546 | case HW_BREAKPOINT_LEN_8: | |
547 | info->ctrl.len = ARM_BREAKPOINT_LEN_8; | |
548 | if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE) | |
549 | && max_watchpoint_len >= 8) | |
550 | break; | |
551 | default: | |
552 | return -EINVAL; | |
553 | } | |
554 | ||
6ee33c27 WD |
555 | /* |
556 | * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes. | |
557 | * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported | |
558 | * by the hardware and must be aligned to the appropriate number of | |
559 | * bytes. | |
560 | */ | |
561 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE && | |
562 | info->ctrl.len != ARM_BREAKPOINT_LEN_2 && | |
563 | info->ctrl.len != ARM_BREAKPOINT_LEN_4) | |
564 | return -EINVAL; | |
565 | ||
f81ef4a9 WD |
566 | /* Address */ |
567 | info->address = bp->attr.bp_addr; | |
568 | ||
569 | /* Privilege */ | |
570 | info->ctrl.privilege = ARM_BREAKPOINT_USER; | |
93a04a34 | 571 | if (arch_check_bp_in_kernelspace(bp)) |
f81ef4a9 WD |
572 | info->ctrl.privilege |= ARM_BREAKPOINT_PRIV; |
573 | ||
574 | /* Enabled? */ | |
575 | info->ctrl.enabled = !bp->attr.disabled; | |
576 | ||
577 | /* Mismatch */ | |
578 | info->ctrl.mismatch = 0; | |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
583 | /* | |
584 | * Validate the arch-specific HW Breakpoint register settings. | |
585 | */ | |
586 | int arch_validate_hwbkpt_settings(struct perf_event *bp) | |
587 | { | |
588 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
589 | int ret = 0; | |
6ee33c27 | 590 | u32 offset, alignment_mask = 0x3; |
f81ef4a9 WD |
591 | |
592 | /* Build the arch_hw_breakpoint. */ | |
593 | ret = arch_build_bp_info(bp); | |
594 | if (ret) | |
595 | goto out; | |
596 | ||
597 | /* Check address alignment. */ | |
598 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) | |
599 | alignment_mask = 0x7; | |
6ee33c27 WD |
600 | offset = info->address & alignment_mask; |
601 | switch (offset) { | |
602 | case 0: | |
603 | /* Aligned */ | |
604 | break; | |
605 | case 1: | |
606 | /* Allow single byte watchpoint. */ | |
607 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) | |
608 | break; | |
609 | case 2: | |
610 | /* Allow halfword watchpoints and breakpoints. */ | |
611 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) | |
612 | break; | |
613 | default: | |
614 | ret = -EINVAL; | |
615 | goto out; | |
f81ef4a9 WD |
616 | } |
617 | ||
6ee33c27 WD |
618 | info->address &= ~alignment_mask; |
619 | info->ctrl.len <<= offset; | |
620 | ||
f81ef4a9 WD |
621 | /* |
622 | * Currently we rely on an overflow handler to take | |
623 | * care of single-stepping the breakpoint when it fires. | |
624 | * In the case of userspace breakpoints on a core with V7 debug, | |
3ce70b2e WD |
625 | * we can use the mismatch feature as a poor-man's hardware |
626 | * single-step, but this only works for per-task breakpoints. | |
f81ef4a9 WD |
627 | */ |
628 | if (WARN_ONCE(!bp->overflow_handler && | |
3ce70b2e WD |
629 | (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_brps() |
630 | || !bp->hw.bp_target), | |
f81ef4a9 WD |
631 | "overflow handler required but none found")) { |
632 | ret = -EINVAL; | |
f81ef4a9 WD |
633 | } |
634 | out: | |
635 | return ret; | |
636 | } | |
637 | ||
9ebb3cbc WD |
638 | /* |
639 | * Enable/disable single-stepping over the breakpoint bp at address addr. | |
640 | */ | |
641 | static void enable_single_step(struct perf_event *bp, u32 addr) | |
f81ef4a9 | 642 | { |
9ebb3cbc | 643 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); |
f81ef4a9 | 644 | |
9ebb3cbc WD |
645 | arch_uninstall_hw_breakpoint(bp); |
646 | info->step_ctrl.mismatch = 1; | |
647 | info->step_ctrl.len = ARM_BREAKPOINT_LEN_4; | |
648 | info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE; | |
649 | info->step_ctrl.privilege = info->ctrl.privilege; | |
650 | info->step_ctrl.enabled = 1; | |
651 | info->trigger = addr; | |
652 | arch_install_hw_breakpoint(bp); | |
653 | } | |
f81ef4a9 | 654 | |
9ebb3cbc WD |
655 | static void disable_single_step(struct perf_event *bp) |
656 | { | |
657 | arch_uninstall_hw_breakpoint(bp); | |
658 | counter_arch_bp(bp)->step_ctrl.enabled = 0; | |
659 | arch_install_hw_breakpoint(bp); | |
f81ef4a9 WD |
660 | } |
661 | ||
662 | static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs) | |
663 | { | |
664 | int i; | |
4a55c18e | 665 | struct perf_event *wp, **slots; |
f81ef4a9 | 666 | struct arch_hw_breakpoint *info; |
f81ef4a9 | 667 | |
4a55c18e WD |
668 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); |
669 | ||
f81ef4a9 WD |
670 | /* Without a disassembler, we can only handle 1 watchpoint. */ |
671 | BUG_ON(core_num_wrps > 1); | |
672 | ||
f81ef4a9 WD |
673 | for (i = 0; i < core_num_wrps; ++i) { |
674 | rcu_read_lock(); | |
675 | ||
93a04a34 WD |
676 | wp = slots[i]; |
677 | ||
678 | if (wp == NULL) { | |
f81ef4a9 WD |
679 | rcu_read_unlock(); |
680 | continue; | |
681 | } | |
682 | ||
683 | /* | |
684 | * The DFAR is an unknown value. Since we only allow a | |
685 | * single watchpoint, we can set the trigger to the lowest | |
686 | * possible faulting address. | |
687 | */ | |
93a04a34 WD |
688 | info = counter_arch_bp(wp); |
689 | info->trigger = wp->attr.bp_addr; | |
f81ef4a9 | 690 | pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); |
93a04a34 | 691 | perf_bp_event(wp, regs); |
f81ef4a9 WD |
692 | |
693 | /* | |
694 | * If no overflow handler is present, insert a temporary | |
695 | * mismatch breakpoint so we can single-step over the | |
696 | * watchpoint trigger. | |
697 | */ | |
9ebb3cbc WD |
698 | if (!wp->overflow_handler) |
699 | enable_single_step(wp, instruction_pointer(regs)); | |
f81ef4a9 WD |
700 | |
701 | rcu_read_unlock(); | |
702 | } | |
703 | } | |
704 | ||
93a04a34 WD |
705 | static void watchpoint_single_step_handler(unsigned long pc) |
706 | { | |
707 | int i; | |
4a55c18e | 708 | struct perf_event *wp, **slots; |
93a04a34 WD |
709 | struct arch_hw_breakpoint *info; |
710 | ||
4a55c18e WD |
711 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); |
712 | ||
93a04a34 WD |
713 | for (i = 0; i < core_num_reserved_brps; ++i) { |
714 | rcu_read_lock(); | |
715 | ||
716 | wp = slots[i]; | |
717 | ||
718 | if (wp == NULL) | |
719 | goto unlock; | |
720 | ||
721 | info = counter_arch_bp(wp); | |
722 | if (!info->step_ctrl.enabled) | |
723 | goto unlock; | |
724 | ||
725 | /* | |
726 | * Restore the original watchpoint if we've completed the | |
727 | * single-step. | |
728 | */ | |
9ebb3cbc WD |
729 | if (info->trigger != pc) |
730 | disable_single_step(wp); | |
93a04a34 WD |
731 | |
732 | unlock: | |
733 | rcu_read_unlock(); | |
734 | } | |
735 | } | |
736 | ||
f81ef4a9 WD |
737 | static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) |
738 | { | |
739 | int i; | |
f81ef4a9 | 740 | u32 ctrl_reg, val, addr; |
4a55c18e | 741 | struct perf_event *bp, **slots; |
f81ef4a9 WD |
742 | struct arch_hw_breakpoint *info; |
743 | struct arch_hw_breakpoint_ctrl ctrl; | |
744 | ||
4a55c18e WD |
745 | slots = (struct perf_event **)__get_cpu_var(bp_on_reg); |
746 | ||
f81ef4a9 WD |
747 | /* The exception entry code places the amended lr in the PC. */ |
748 | addr = regs->ARM_pc; | |
749 | ||
93a04a34 WD |
750 | /* Check the currently installed breakpoints first. */ |
751 | for (i = 0; i < core_num_brps; ++i) { | |
f81ef4a9 WD |
752 | rcu_read_lock(); |
753 | ||
754 | bp = slots[i]; | |
755 | ||
9ebb3cbc WD |
756 | if (bp == NULL) |
757 | goto unlock; | |
f81ef4a9 | 758 | |
9ebb3cbc | 759 | info = counter_arch_bp(bp); |
f81ef4a9 WD |
760 | |
761 | /* Check if the breakpoint value matches. */ | |
762 | val = read_wb_reg(ARM_BASE_BVR + i); | |
763 | if (val != (addr & ~0x3)) | |
9ebb3cbc | 764 | goto mismatch; |
f81ef4a9 WD |
765 | |
766 | /* Possible match, check the byte address select to confirm. */ | |
767 | ctrl_reg = read_wb_reg(ARM_BASE_BCR + i); | |
768 | decode_ctrl_reg(ctrl_reg, &ctrl); | |
769 | if ((1 << (addr & 0x3)) & ctrl.len) { | |
f81ef4a9 | 770 | info->trigger = addr; |
f81ef4a9 WD |
771 | pr_debug("breakpoint fired: address = 0x%x\n", addr); |
772 | perf_bp_event(bp, regs); | |
9ebb3cbc WD |
773 | if (!bp->overflow_handler) |
774 | enable_single_step(bp, addr); | |
775 | goto unlock; | |
f81ef4a9 WD |
776 | } |
777 | ||
9ebb3cbc WD |
778 | mismatch: |
779 | /* If we're stepping a breakpoint, it can now be restored. */ | |
780 | if (info->step_ctrl.enabled) | |
781 | disable_single_step(bp); | |
782 | unlock: | |
f81ef4a9 WD |
783 | rcu_read_unlock(); |
784 | } | |
93a04a34 WD |
785 | |
786 | /* Handle any pending watchpoint single-step breakpoints. */ | |
787 | watchpoint_single_step_handler(addr); | |
f81ef4a9 WD |
788 | } |
789 | ||
790 | /* | |
791 | * Called from either the Data Abort Handler [watchpoint] or the | |
7e202696 | 792 | * Prefetch Abort Handler [breakpoint] with preemption disabled. |
f81ef4a9 WD |
793 | */ |
794 | static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, | |
795 | struct pt_regs *regs) | |
796 | { | |
7e202696 | 797 | int ret = 0; |
f81ef4a9 WD |
798 | u32 dscr; |
799 | ||
7e202696 WD |
800 | /* We must be called with preemption disabled. */ |
801 | WARN_ON(preemptible()); | |
802 | ||
f81ef4a9 WD |
803 | /* We only handle watchpoints and hardware breakpoints. */ |
804 | ARM_DBG_READ(c1, 0, dscr); | |
805 | ||
806 | /* Perform perf callbacks. */ | |
807 | switch (ARM_DSCR_MOE(dscr)) { | |
808 | case ARM_ENTRY_BREAKPOINT: | |
809 | breakpoint_handler(addr, regs); | |
810 | break; | |
811 | case ARM_ENTRY_ASYNC_WATCHPOINT: | |
235584b6 | 812 | WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n"); |
f81ef4a9 WD |
813 | case ARM_ENTRY_SYNC_WATCHPOINT: |
814 | watchpoint_handler(addr, regs); | |
815 | break; | |
816 | default: | |
7e202696 | 817 | ret = 1; /* Unhandled fault. */ |
f81ef4a9 WD |
818 | } |
819 | ||
7e202696 WD |
820 | /* |
821 | * Re-enable preemption after it was disabled in the | |
822 | * low-level exception handling code. | |
823 | */ | |
824 | preempt_enable(); | |
825 | ||
f81ef4a9 WD |
826 | return ret; |
827 | } | |
828 | ||
829 | /* | |
830 | * One-time initialisation. | |
831 | */ | |
7d99331e | 832 | static void reset_ctrl_regs(void *unused) |
f81ef4a9 WD |
833 | { |
834 | int i; | |
835 | ||
ac88e071 WD |
836 | /* |
837 | * v7 debug contains save and restore registers so that debug state | |
838 | * can be maintained across low-power modes without leaving | |
839 | * the debug logic powered up. It is IMPLEMENTATION DEFINED whether | |
840 | * we can write to the debug registers out of reset, so we must | |
841 | * unlock the OS Lock Access Register to avoid taking undefined | |
842 | * instruction exceptions later on. | |
843 | */ | |
844 | if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) { | |
845 | /* | |
846 | * Unconditionally clear the lock by writing a value | |
847 | * other than 0xC5ACCE55 to the access register. | |
848 | */ | |
849 | asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0)); | |
850 | isb(); | |
851 | } | |
852 | ||
f81ef4a9 WD |
853 | if (enable_monitor_mode()) |
854 | return; | |
855 | ||
0017ff42 WD |
856 | /* We must also reset any reserved registers. */ |
857 | for (i = 0; i < core_num_brps + core_num_reserved_brps; ++i) { | |
f81ef4a9 WD |
858 | write_wb_reg(ARM_BASE_BCR + i, 0UL); |
859 | write_wb_reg(ARM_BASE_BVR + i, 0UL); | |
860 | } | |
861 | ||
862 | for (i = 0; i < core_num_wrps; ++i) { | |
863 | write_wb_reg(ARM_BASE_WCR + i, 0UL); | |
864 | write_wb_reg(ARM_BASE_WVR + i, 0UL); | |
865 | } | |
866 | } | |
867 | ||
7d99331e WD |
868 | static int __cpuinit dbg_reset_notify(struct notifier_block *self, |
869 | unsigned long action, void *cpu) | |
870 | { | |
871 | if (action == CPU_ONLINE) | |
872 | smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1); | |
873 | return NOTIFY_OK; | |
874 | } | |
875 | ||
876 | static struct notifier_block __cpuinitdata dbg_reset_nb = { | |
877 | .notifier_call = dbg_reset_notify, | |
878 | }; | |
879 | ||
f81ef4a9 WD |
880 | static int __init arch_hw_breakpoint_init(void) |
881 | { | |
882 | int ret = 0; | |
883 | u32 dscr; | |
884 | ||
885 | debug_arch = get_debug_arch(); | |
886 | ||
887 | if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) { | |
888 | pr_info("debug architecture 0x%x unsupported.\n", debug_arch); | |
889 | ret = -ENODEV; | |
890 | goto out; | |
891 | } | |
892 | ||
893 | /* Determine how many BRPs/WRPs are available. */ | |
894 | core_num_brps = get_num_brps(); | |
0017ff42 | 895 | core_num_reserved_brps = get_num_reserved_brps(); |
f81ef4a9 WD |
896 | core_num_wrps = get_num_wrps(); |
897 | ||
898 | pr_info("found %d breakpoint and %d watchpoint registers.\n", | |
0017ff42 | 899 | core_num_brps + core_num_reserved_brps, core_num_wrps); |
f81ef4a9 | 900 | |
0017ff42 WD |
901 | if (core_num_reserved_brps) |
902 | pr_info("%d breakpoint(s) reserved for watchpoint " | |
903 | "single-step.\n", core_num_reserved_brps); | |
f81ef4a9 WD |
904 | |
905 | ARM_DBG_READ(c1, 0, dscr); | |
906 | if (dscr & ARM_DSCR_HDBGEN) { | |
907 | pr_warning("halting debug mode enabled. Assuming maximum " | |
908 | "watchpoint size of 4 bytes."); | |
909 | } else { | |
f81ef4a9 WD |
910 | /* |
911 | * Reset the breakpoint resources. We assume that a halting | |
912 | * debugger will leave the world in a nice state for us. | |
913 | */ | |
914 | smp_call_function(reset_ctrl_regs, NULL, 1); | |
915 | reset_ctrl_regs(NULL); | |
ac88e071 WD |
916 | |
917 | /* Work out the maximum supported watchpoint length. */ | |
918 | max_watchpoint_len = get_max_wp_len(); | |
919 | pr_info("maximum watchpoint size is %u bytes.\n", | |
920 | max_watchpoint_len); | |
f81ef4a9 WD |
921 | } |
922 | ||
923 | /* Register debug fault handler. */ | |
924 | hook_fault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, | |
925 | "watchpoint debug exception"); | |
926 | hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, | |
927 | "breakpoint debug exception"); | |
928 | ||
7d99331e WD |
929 | /* Register hotplug notifier. */ |
930 | register_cpu_notifier(&dbg_reset_nb); | |
f81ef4a9 WD |
931 | out: |
932 | return ret; | |
933 | } | |
934 | arch_initcall(arch_hw_breakpoint_init); | |
935 | ||
936 | void hw_breakpoint_pmu_read(struct perf_event *bp) | |
937 | { | |
938 | } | |
939 | ||
940 | /* | |
941 | * Dummy function to register with die_notifier. | |
942 | */ | |
943 | int hw_breakpoint_exceptions_notify(struct notifier_block *unused, | |
944 | unsigned long val, void *data) | |
945 | { | |
946 | return NOTIFY_DONE; | |
947 | } |