Commit | Line | Data |
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1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 JI |
9 | * This code is based on the sparc64 perf event code, which is in turn based |
10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | |
11 | * code. | |
12 | */ | |
13 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
14 | ||
15 | #include <linux/interrupt.h> | |
16 | #include <linux/kernel.h> | |
181193f3 | 17 | #include <linux/module.h> |
1b8873a0 | 18 | #include <linux/perf_event.h> |
49c006b9 | 19 | #include <linux/platform_device.h> |
1b8873a0 JI |
20 | #include <linux/spinlock.h> |
21 | #include <linux/uaccess.h> | |
22 | ||
23 | #include <asm/cputype.h> | |
24 | #include <asm/irq.h> | |
25 | #include <asm/irq_regs.h> | |
26 | #include <asm/pmu.h> | |
27 | #include <asm/stacktrace.h> | |
28 | ||
1b8873a0 | 29 | /* |
ecf5a893 | 30 | * ARMv6 supports a maximum of 3 events, starting from index 0. If we add |
1b8873a0 JI |
31 | * another platform that supports more, we need to increase this to be the |
32 | * largest of all platforms. | |
796d1295 JP |
33 | * |
34 | * ARMv7 supports up to 32 events: | |
35 | * cycle counter CCNT + 31 events counters CNT0..30. | |
36 | * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. | |
1b8873a0 | 37 | */ |
ecf5a893 | 38 | #define ARMPMU_MAX_HWEVENTS 32 |
1b8873a0 JI |
39 | |
40 | /* The events for a given CPU. */ | |
41 | struct cpu_hw_events { | |
42 | /* | |
ecf5a893 | 43 | * The events that are active on the CPU for the given index. |
1b8873a0 | 44 | */ |
3fc2c830 | 45 | struct perf_event **events; |
1b8873a0 JI |
46 | |
47 | /* | |
48 | * A 1 bit for an index indicates that the counter is being used for | |
49 | * an event. A 0 means that the counter can be used. | |
50 | */ | |
3fc2c830 | 51 | unsigned long *used_mask; |
0f78d2d5 MR |
52 | |
53 | /* | |
54 | * Hardware lock to serialize accesses to PMU registers. Needed for the | |
55 | * read/modify/write sequences. | |
56 | */ | |
57 | raw_spinlock_t pmu_lock; | |
1b8873a0 | 58 | }; |
3fc2c830 MR |
59 | |
60 | static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events); | |
61 | static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask); | |
4d6b7a77 | 62 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
181193f3 | 63 | |
1b8873a0 | 64 | struct arm_pmu { |
8a16b34e | 65 | struct pmu pmu; |
181193f3 | 66 | enum arm_perf_pmu_ids id; |
7ae18a57 | 67 | enum arm_pmu_type type; |
0b390e21 | 68 | cpumask_t active_irqs; |
62994831 | 69 | const char *name; |
1b8873a0 JI |
70 | irqreturn_t (*handle_irq)(int irq_num, void *dev); |
71 | void (*enable)(struct hw_perf_event *evt, int idx); | |
72 | void (*disable)(struct hw_perf_event *evt, int idx); | |
1b8873a0 JI |
73 | int (*get_event_idx)(struct cpu_hw_events *cpuc, |
74 | struct hw_perf_event *hwc); | |
05d22fde WD |
75 | int (*set_event_filter)(struct hw_perf_event *evt, |
76 | struct perf_event_attr *attr); | |
1b8873a0 JI |
77 | u32 (*read_counter)(int idx); |
78 | void (*write_counter)(int idx, u32 val); | |
79 | void (*start)(void); | |
80 | void (*stop)(void); | |
574b69cb | 81 | void (*reset)(void *); |
e1f431b5 | 82 | int (*map_event)(struct perf_event *event); |
1b8873a0 | 83 | int num_events; |
03b7898d MR |
84 | atomic_t active_events; |
85 | struct mutex reserve_mutex; | |
1b8873a0 | 86 | u64 max_period; |
a9356a04 | 87 | struct platform_device *plat_device; |
92f701e1 | 88 | struct cpu_hw_events *(*get_hw_events)(void); |
1b8873a0 JI |
89 | }; |
90 | ||
8a16b34e MR |
91 | #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) |
92 | ||
1b8873a0 | 93 | /* Set at runtime when we know what CPU type we are. */ |
a6c93afe | 94 | static struct arm_pmu *armpmu; |
1b8873a0 | 95 | |
181193f3 WD |
96 | enum arm_perf_pmu_ids |
97 | armpmu_get_pmu_id(void) | |
98 | { | |
99 | int id = -ENODEV; | |
100 | ||
101 | if (armpmu != NULL) | |
102 | id = armpmu->id; | |
103 | ||
104 | return id; | |
105 | } | |
106 | EXPORT_SYMBOL_GPL(armpmu_get_pmu_id); | |
107 | ||
929f5199 WD |
108 | int |
109 | armpmu_get_max_events(void) | |
110 | { | |
111 | int max_events = 0; | |
112 | ||
113 | if (armpmu != NULL) | |
114 | max_events = armpmu->num_events; | |
115 | ||
116 | return max_events; | |
117 | } | |
118 | EXPORT_SYMBOL_GPL(armpmu_get_max_events); | |
119 | ||
3bf101ba MF |
120 | int perf_num_counters(void) |
121 | { | |
122 | return armpmu_get_max_events(); | |
123 | } | |
124 | EXPORT_SYMBOL_GPL(perf_num_counters); | |
125 | ||
1b8873a0 JI |
126 | #define HW_OP_UNSUPPORTED 0xFFFF |
127 | ||
128 | #define C(_x) \ | |
129 | PERF_COUNT_HW_CACHE_##_x | |
130 | ||
131 | #define CACHE_OP_UNSUPPORTED 0xFFFF | |
132 | ||
1b8873a0 | 133 | static int |
e1f431b5 MR |
134 | armpmu_map_cache_event(const unsigned (*cache_map) |
135 | [PERF_COUNT_HW_CACHE_MAX] | |
136 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
137 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
138 | u64 config) | |
1b8873a0 JI |
139 | { |
140 | unsigned int cache_type, cache_op, cache_result, ret; | |
141 | ||
142 | cache_type = (config >> 0) & 0xff; | |
143 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
144 | return -EINVAL; | |
145 | ||
146 | cache_op = (config >> 8) & 0xff; | |
147 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
148 | return -EINVAL; | |
149 | ||
150 | cache_result = (config >> 16) & 0xff; | |
151 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
152 | return -EINVAL; | |
153 | ||
e1f431b5 | 154 | ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
155 | |
156 | if (ret == CACHE_OP_UNSUPPORTED) | |
157 | return -ENOENT; | |
158 | ||
159 | return ret; | |
160 | } | |
161 | ||
84fee97a | 162 | static int |
e1f431b5 | 163 | armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) |
84fee97a | 164 | { |
e1f431b5 MR |
165 | int mapping = (*event_map)[config]; |
166 | return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; | |
84fee97a WD |
167 | } |
168 | ||
169 | static int | |
e1f431b5 | 170 | armpmu_map_raw_event(u32 raw_event_mask, u64 config) |
84fee97a | 171 | { |
e1f431b5 MR |
172 | return (int)(config & raw_event_mask); |
173 | } | |
174 | ||
175 | static int map_cpu_event(struct perf_event *event, | |
176 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], | |
177 | const unsigned (*cache_map) | |
178 | [PERF_COUNT_HW_CACHE_MAX] | |
179 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
180 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
181 | u32 raw_event_mask) | |
182 | { | |
183 | u64 config = event->attr.config; | |
184 | ||
185 | switch (event->attr.type) { | |
186 | case PERF_TYPE_HARDWARE: | |
187 | return armpmu_map_event(event_map, config); | |
188 | case PERF_TYPE_HW_CACHE: | |
189 | return armpmu_map_cache_event(cache_map, config); | |
190 | case PERF_TYPE_RAW: | |
191 | return armpmu_map_raw_event(raw_event_mask, config); | |
192 | } | |
193 | ||
194 | return -ENOENT; | |
84fee97a WD |
195 | } |
196 | ||
1b8873a0 JI |
197 | static int |
198 | armpmu_event_set_period(struct perf_event *event, | |
199 | struct hw_perf_event *hwc, | |
200 | int idx) | |
201 | { | |
8a16b34e | 202 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
e7850595 | 203 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
204 | s64 period = hwc->sample_period; |
205 | int ret = 0; | |
206 | ||
207 | if (unlikely(left <= -period)) { | |
208 | left = period; | |
e7850595 | 209 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
210 | hwc->last_period = period; |
211 | ret = 1; | |
212 | } | |
213 | ||
214 | if (unlikely(left <= 0)) { | |
215 | left += period; | |
e7850595 | 216 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
217 | hwc->last_period = period; |
218 | ret = 1; | |
219 | } | |
220 | ||
221 | if (left > (s64)armpmu->max_period) | |
222 | left = armpmu->max_period; | |
223 | ||
e7850595 | 224 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 JI |
225 | |
226 | armpmu->write_counter(idx, (u64)(-left) & 0xffffffff); | |
227 | ||
228 | perf_event_update_userpage(event); | |
229 | ||
230 | return ret; | |
231 | } | |
232 | ||
233 | static u64 | |
234 | armpmu_event_update(struct perf_event *event, | |
235 | struct hw_perf_event *hwc, | |
a737823d | 236 | int idx, int overflow) |
1b8873a0 | 237 | { |
8a16b34e | 238 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
a737823d | 239 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
240 | |
241 | again: | |
e7850595 | 242 | prev_raw_count = local64_read(&hwc->prev_count); |
1b8873a0 JI |
243 | new_raw_count = armpmu->read_counter(idx); |
244 | ||
e7850595 | 245 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
246 | new_raw_count) != prev_raw_count) |
247 | goto again; | |
248 | ||
a737823d WD |
249 | new_raw_count &= armpmu->max_period; |
250 | prev_raw_count &= armpmu->max_period; | |
251 | ||
252 | if (overflow) | |
6759788b | 253 | delta = armpmu->max_period - prev_raw_count + new_raw_count + 1; |
a737823d WD |
254 | else |
255 | delta = new_raw_count - prev_raw_count; | |
1b8873a0 | 256 | |
e7850595 PZ |
257 | local64_add(delta, &event->count); |
258 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
259 | |
260 | return new_raw_count; | |
261 | } | |
262 | ||
263 | static void | |
a4eaf7f1 | 264 | armpmu_read(struct perf_event *event) |
1b8873a0 | 265 | { |
1b8873a0 | 266 | struct hw_perf_event *hwc = &event->hw; |
1b8873a0 | 267 | |
a4eaf7f1 PZ |
268 | /* Don't read disabled counters! */ |
269 | if (hwc->idx < 0) | |
270 | return; | |
1b8873a0 | 271 | |
a737823d | 272 | armpmu_event_update(event, hwc, hwc->idx, 0); |
1b8873a0 JI |
273 | } |
274 | ||
275 | static void | |
a4eaf7f1 | 276 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 | 277 | { |
8a16b34e | 278 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
279 | struct hw_perf_event *hwc = &event->hw; |
280 | ||
a4eaf7f1 PZ |
281 | /* |
282 | * ARM pmu always has to update the counter, so ignore | |
283 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
284 | */ | |
285 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
286 | armpmu->disable(hwc, hwc->idx); | |
287 | barrier(); /* why? */ | |
a737823d | 288 | armpmu_event_update(event, hwc, hwc->idx, 0); |
a4eaf7f1 PZ |
289 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
290 | } | |
1b8873a0 JI |
291 | } |
292 | ||
293 | static void | |
a4eaf7f1 | 294 | armpmu_start(struct perf_event *event, int flags) |
1b8873a0 | 295 | { |
8a16b34e | 296 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
297 | struct hw_perf_event *hwc = &event->hw; |
298 | ||
a4eaf7f1 PZ |
299 | /* |
300 | * ARM pmu always has to reprogram the period, so ignore | |
301 | * PERF_EF_RELOAD, see the comment below. | |
302 | */ | |
303 | if (flags & PERF_EF_RELOAD) | |
304 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
305 | ||
306 | hwc->state = 0; | |
1b8873a0 JI |
307 | /* |
308 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 309 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
310 | * may have been left counting. If we don't do this step then we may |
311 | * get an interrupt too soon or *way* too late if the overflow has | |
312 | * happened since disabling. | |
313 | */ | |
314 | armpmu_event_set_period(event, hwc, hwc->idx); | |
315 | armpmu->enable(hwc, hwc->idx); | |
316 | } | |
317 | ||
a4eaf7f1 PZ |
318 | static void |
319 | armpmu_del(struct perf_event *event, int flags) | |
320 | { | |
8a16b34e | 321 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
92f701e1 | 322 | struct cpu_hw_events *cpuc = armpmu->get_hw_events(); |
a4eaf7f1 PZ |
323 | struct hw_perf_event *hwc = &event->hw; |
324 | int idx = hwc->idx; | |
325 | ||
326 | WARN_ON(idx < 0); | |
327 | ||
a4eaf7f1 PZ |
328 | armpmu_stop(event, PERF_EF_UPDATE); |
329 | cpuc->events[idx] = NULL; | |
330 | clear_bit(idx, cpuc->used_mask); | |
331 | ||
332 | perf_event_update_userpage(event); | |
333 | } | |
334 | ||
1b8873a0 | 335 | static int |
a4eaf7f1 | 336 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 | 337 | { |
8a16b34e | 338 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
92f701e1 | 339 | struct cpu_hw_events *cpuc = armpmu->get_hw_events(); |
1b8873a0 JI |
340 | struct hw_perf_event *hwc = &event->hw; |
341 | int idx; | |
342 | int err = 0; | |
343 | ||
33696fc0 | 344 | perf_pmu_disable(event->pmu); |
24cd7f54 | 345 | |
1b8873a0 JI |
346 | /* If we don't have a space for the counter then finish early. */ |
347 | idx = armpmu->get_event_idx(cpuc, hwc); | |
348 | if (idx < 0) { | |
349 | err = idx; | |
350 | goto out; | |
351 | } | |
352 | ||
353 | /* | |
354 | * If there is an event in the counter we are going to use then make | |
355 | * sure it is disabled. | |
356 | */ | |
357 | event->hw.idx = idx; | |
358 | armpmu->disable(hwc, idx); | |
359 | cpuc->events[idx] = event; | |
1b8873a0 | 360 | |
a4eaf7f1 PZ |
361 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
362 | if (flags & PERF_EF_START) | |
363 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
364 | |
365 | /* Propagate our changes to the userspace mapping. */ | |
366 | perf_event_update_userpage(event); | |
367 | ||
368 | out: | |
33696fc0 | 369 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
370 | return err; |
371 | } | |
372 | ||
1b8873a0 JI |
373 | static int |
374 | validate_event(struct cpu_hw_events *cpuc, | |
375 | struct perf_event *event) | |
376 | { | |
8a16b34e | 377 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 378 | struct hw_perf_event fake_event = event->hw; |
7b9f72c6 | 379 | struct pmu *leader_pmu = event->group_leader->pmu; |
1b8873a0 | 380 | |
7b9f72c6 | 381 | if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF) |
65b4711f | 382 | return 1; |
1b8873a0 JI |
383 | |
384 | return armpmu->get_event_idx(cpuc, &fake_event) >= 0; | |
385 | } | |
386 | ||
387 | static int | |
388 | validate_group(struct perf_event *event) | |
389 | { | |
390 | struct perf_event *sibling, *leader = event->group_leader; | |
391 | struct cpu_hw_events fake_pmu; | |
392 | ||
393 | memset(&fake_pmu, 0, sizeof(fake_pmu)); | |
394 | ||
395 | if (!validate_event(&fake_pmu, leader)) | |
396 | return -ENOSPC; | |
397 | ||
398 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
399 | if (!validate_event(&fake_pmu, sibling)) | |
400 | return -ENOSPC; | |
401 | } | |
402 | ||
403 | if (!validate_event(&fake_pmu, event)) | |
404 | return -ENOSPC; | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
0e25a5c9 RV |
409 | static irqreturn_t armpmu_platform_irq(int irq, void *dev) |
410 | { | |
8a16b34e | 411 | struct arm_pmu *armpmu = (struct arm_pmu *) dev; |
a9356a04 MR |
412 | struct platform_device *plat_device = armpmu->plat_device; |
413 | struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev); | |
0e25a5c9 RV |
414 | |
415 | return plat->handle_irq(irq, dev, armpmu->handle_irq); | |
416 | } | |
417 | ||
0b390e21 | 418 | static void |
8a16b34e | 419 | armpmu_release_hardware(struct arm_pmu *armpmu) |
0b390e21 WD |
420 | { |
421 | int i, irq, irqs; | |
a9356a04 | 422 | struct platform_device *pmu_device = armpmu->plat_device; |
0b390e21 WD |
423 | |
424 | irqs = min(pmu_device->num_resources, num_possible_cpus()); | |
425 | ||
426 | for (i = 0; i < irqs; ++i) { | |
427 | if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs)) | |
428 | continue; | |
429 | irq = platform_get_irq(pmu_device, i); | |
430 | if (irq >= 0) | |
8a16b34e | 431 | free_irq(irq, armpmu); |
0b390e21 WD |
432 | } |
433 | ||
7ae18a57 | 434 | release_pmu(armpmu->type); |
0b390e21 WD |
435 | } |
436 | ||
1b8873a0 | 437 | static int |
8a16b34e | 438 | armpmu_reserve_hardware(struct arm_pmu *armpmu) |
1b8873a0 | 439 | { |
0e25a5c9 RV |
440 | struct arm_pmu_platdata *plat; |
441 | irq_handler_t handle_irq; | |
b0e89590 | 442 | int i, err, irq, irqs; |
a9356a04 | 443 | struct platform_device *pmu_device = armpmu->plat_device; |
1b8873a0 | 444 | |
7ae18a57 | 445 | err = reserve_pmu(armpmu->type); |
b0e89590 | 446 | if (err) { |
1b8873a0 | 447 | pr_warning("unable to reserve pmu\n"); |
b0e89590 | 448 | return err; |
1b8873a0 JI |
449 | } |
450 | ||
0e25a5c9 RV |
451 | plat = dev_get_platdata(&pmu_device->dev); |
452 | if (plat && plat->handle_irq) | |
453 | handle_irq = armpmu_platform_irq; | |
454 | else | |
455 | handle_irq = armpmu->handle_irq; | |
456 | ||
0b390e21 | 457 | irqs = min(pmu_device->num_resources, num_possible_cpus()); |
b0e89590 | 458 | if (irqs < 1) { |
1b8873a0 JI |
459 | pr_err("no irqs for PMUs defined\n"); |
460 | return -ENODEV; | |
461 | } | |
462 | ||
b0e89590 | 463 | for (i = 0; i < irqs; ++i) { |
0b390e21 | 464 | err = 0; |
49c006b9 WD |
465 | irq = platform_get_irq(pmu_device, i); |
466 | if (irq < 0) | |
467 | continue; | |
468 | ||
b0e89590 WD |
469 | /* |
470 | * If we have a single PMU interrupt that we can't shift, | |
471 | * assume that we're running on a uniprocessor machine and | |
0b390e21 | 472 | * continue. Otherwise, continue without this interrupt. |
b0e89590 | 473 | */ |
0b390e21 WD |
474 | if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { |
475 | pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", | |
476 | irq, i); | |
477 | continue; | |
b0e89590 WD |
478 | } |
479 | ||
0e25a5c9 | 480 | err = request_irq(irq, handle_irq, |
ddee87f2 | 481 | IRQF_DISABLED | IRQF_NOBALANCING, |
8a16b34e | 482 | "arm-pmu", armpmu); |
1b8873a0 | 483 | if (err) { |
b0e89590 WD |
484 | pr_err("unable to request IRQ%d for ARM PMU counters\n", |
485 | irq); | |
8a16b34e | 486 | armpmu_release_hardware(armpmu); |
0b390e21 | 487 | return err; |
1b8873a0 | 488 | } |
1b8873a0 | 489 | |
0b390e21 | 490 | cpumask_set_cpu(i, &armpmu->active_irqs); |
49c006b9 | 491 | } |
1b8873a0 | 492 | |
0b390e21 | 493 | return 0; |
1b8873a0 JI |
494 | } |
495 | ||
1b8873a0 JI |
496 | static void |
497 | hw_perf_event_destroy(struct perf_event *event) | |
498 | { | |
8a16b34e | 499 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
03b7898d MR |
500 | atomic_t *active_events = &armpmu->active_events; |
501 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; | |
502 | ||
503 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { | |
8a16b34e | 504 | armpmu_release_hardware(armpmu); |
03b7898d | 505 | mutex_unlock(pmu_reserve_mutex); |
1b8873a0 JI |
506 | } |
507 | } | |
508 | ||
05d22fde WD |
509 | static int |
510 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
511 | { | |
512 | return attr->exclude_idle || attr->exclude_user || | |
513 | attr->exclude_kernel || attr->exclude_hv; | |
514 | } | |
515 | ||
1b8873a0 JI |
516 | static int |
517 | __hw_perf_event_init(struct perf_event *event) | |
518 | { | |
8a16b34e | 519 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
520 | struct hw_perf_event *hwc = &event->hw; |
521 | int mapping, err; | |
522 | ||
e1f431b5 | 523 | mapping = armpmu->map_event(event); |
1b8873a0 JI |
524 | |
525 | if (mapping < 0) { | |
526 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
527 | event->attr.config); | |
528 | return mapping; | |
529 | } | |
530 | ||
05d22fde WD |
531 | /* |
532 | * We don't assign an index until we actually place the event onto | |
533 | * hardware. Use -1 to signify that we haven't decided where to put it | |
534 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
535 | * clever allocation or constraints checking at this point. | |
536 | */ | |
537 | hwc->idx = -1; | |
538 | hwc->config_base = 0; | |
539 | hwc->config = 0; | |
540 | hwc->event_base = 0; | |
541 | ||
1b8873a0 JI |
542 | /* |
543 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 544 | */ |
05d22fde WD |
545 | if ((!armpmu->set_event_filter || |
546 | armpmu->set_event_filter(hwc, &event->attr)) && | |
547 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
548 | pr_debug("ARM performance counters do not support " |
549 | "mode exclusion\n"); | |
550 | return -EPERM; | |
551 | } | |
552 | ||
553 | /* | |
05d22fde | 554 | * Store the event encoding into the config_base field. |
1b8873a0 | 555 | */ |
05d22fde | 556 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 JI |
557 | |
558 | if (!hwc->sample_period) { | |
559 | hwc->sample_period = armpmu->max_period; | |
560 | hwc->last_period = hwc->sample_period; | |
e7850595 | 561 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
562 | } |
563 | ||
564 | err = 0; | |
565 | if (event->group_leader != event) { | |
566 | err = validate_group(event); | |
567 | if (err) | |
568 | return -EINVAL; | |
569 | } | |
570 | ||
571 | return err; | |
572 | } | |
573 | ||
b0a873eb | 574 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 | 575 | { |
8a16b34e | 576 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 577 | int err = 0; |
03b7898d | 578 | atomic_t *active_events = &armpmu->active_events; |
1b8873a0 | 579 | |
e1f431b5 | 580 | if (armpmu->map_event(event) == -ENOENT) |
b0a873eb | 581 | return -ENOENT; |
b0a873eb | 582 | |
1b8873a0 JI |
583 | event->destroy = hw_perf_event_destroy; |
584 | ||
03b7898d MR |
585 | if (!atomic_inc_not_zero(active_events)) { |
586 | mutex_lock(&armpmu->reserve_mutex); | |
587 | if (atomic_read(active_events) == 0) | |
8a16b34e | 588 | err = armpmu_reserve_hardware(armpmu); |
1b8873a0 JI |
589 | |
590 | if (!err) | |
03b7898d MR |
591 | atomic_inc(active_events); |
592 | mutex_unlock(&armpmu->reserve_mutex); | |
1b8873a0 JI |
593 | } |
594 | ||
595 | if (err) | |
b0a873eb | 596 | return err; |
1b8873a0 JI |
597 | |
598 | err = __hw_perf_event_init(event); | |
599 | if (err) | |
600 | hw_perf_event_destroy(event); | |
601 | ||
b0a873eb | 602 | return err; |
1b8873a0 JI |
603 | } |
604 | ||
a4eaf7f1 | 605 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 | 606 | { |
8a16b34e | 607 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
1b8873a0 | 608 | /* Enable all of the perf events on hardware. */ |
f4f38430 | 609 | int idx, enabled = 0; |
92f701e1 | 610 | struct cpu_hw_events *cpuc = armpmu->get_hw_events(); |
1b8873a0 | 611 | |
ecf5a893 | 612 | for (idx = 0; idx < armpmu->num_events; ++idx) { |
1b8873a0 JI |
613 | struct perf_event *event = cpuc->events[idx]; |
614 | ||
615 | if (!event) | |
616 | continue; | |
617 | ||
618 | armpmu->enable(&event->hw, idx); | |
f4f38430 | 619 | enabled = 1; |
1b8873a0 JI |
620 | } |
621 | ||
f4f38430 WD |
622 | if (enabled) |
623 | armpmu->start(); | |
1b8873a0 JI |
624 | } |
625 | ||
a4eaf7f1 | 626 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 627 | { |
8a16b34e | 628 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
48957155 | 629 | armpmu->stop(); |
1b8873a0 JI |
630 | } |
631 | ||
03b7898d MR |
632 | static void __init armpmu_init(struct arm_pmu *armpmu) |
633 | { | |
634 | atomic_set(&armpmu->active_events, 0); | |
635 | mutex_init(&armpmu->reserve_mutex); | |
8a16b34e MR |
636 | |
637 | armpmu->pmu = (struct pmu) { | |
638 | .pmu_enable = armpmu_enable, | |
639 | .pmu_disable = armpmu_disable, | |
640 | .event_init = armpmu_event_init, | |
641 | .add = armpmu_add, | |
642 | .del = armpmu_del, | |
643 | .start = armpmu_start, | |
644 | .stop = armpmu_stop, | |
645 | .read = armpmu_read, | |
646 | }; | |
647 | } | |
648 | ||
649 | static int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type) | |
650 | { | |
651 | armpmu_init(armpmu); | |
652 | return perf_pmu_register(&armpmu->pmu, name, type); | |
03b7898d MR |
653 | } |
654 | ||
43eab878 WD |
655 | /* Include the PMU-specific implementations. */ |
656 | #include "perf_event_xscale.c" | |
657 | #include "perf_event_v6.c" | |
658 | #include "perf_event_v7.c" | |
49e6a32f | 659 | |
574b69cb WD |
660 | /* |
661 | * Ensure the PMU has sane values out of reset. | |
662 | * This requires SMP to be available, so exists as a separate initcall. | |
663 | */ | |
664 | static int __init | |
665 | armpmu_reset(void) | |
666 | { | |
667 | if (armpmu && armpmu->reset) | |
668 | return on_each_cpu(armpmu->reset, NULL, 1); | |
669 | return 0; | |
670 | } | |
671 | arch_initcall(armpmu_reset); | |
672 | ||
b0e89590 WD |
673 | /* |
674 | * PMU platform driver and devicetree bindings. | |
675 | */ | |
676 | static struct of_device_id armpmu_of_device_ids[] = { | |
677 | {.compatible = "arm,cortex-a9-pmu"}, | |
678 | {.compatible = "arm,cortex-a8-pmu"}, | |
679 | {.compatible = "arm,arm1136-pmu"}, | |
680 | {.compatible = "arm,arm1176-pmu"}, | |
681 | {}, | |
682 | }; | |
683 | ||
684 | static struct platform_device_id armpmu_plat_device_ids[] = { | |
685 | {.name = "arm-pmu"}, | |
686 | {}, | |
687 | }; | |
688 | ||
689 | static int __devinit armpmu_device_probe(struct platform_device *pdev) | |
690 | { | |
a9356a04 | 691 | armpmu->plat_device = pdev; |
b0e89590 WD |
692 | return 0; |
693 | } | |
694 | ||
695 | static struct platform_driver armpmu_driver = { | |
696 | .driver = { | |
697 | .name = "arm-pmu", | |
698 | .of_match_table = armpmu_of_device_ids, | |
699 | }, | |
700 | .probe = armpmu_device_probe, | |
701 | .id_table = armpmu_plat_device_ids, | |
702 | }; | |
703 | ||
704 | static int __init register_pmu_driver(void) | |
705 | { | |
706 | return platform_driver_register(&armpmu_driver); | |
707 | } | |
708 | device_initcall(register_pmu_driver); | |
709 | ||
92f701e1 MR |
710 | static struct cpu_hw_events *armpmu_get_cpu_events(void) |
711 | { | |
712 | return &__get_cpu_var(cpu_hw_events); | |
713 | } | |
714 | ||
715 | static void __init cpu_pmu_init(struct arm_pmu *armpmu) | |
716 | { | |
0f78d2d5 MR |
717 | int cpu; |
718 | for_each_possible_cpu(cpu) { | |
719 | struct cpu_hw_events *events = &per_cpu(cpu_hw_events, cpu); | |
3fc2c830 MR |
720 | events->events = per_cpu(hw_events, cpu); |
721 | events->used_mask = per_cpu(used_mask, cpu); | |
0f78d2d5 MR |
722 | raw_spin_lock_init(&events->pmu_lock); |
723 | } | |
92f701e1 | 724 | armpmu->get_hw_events = armpmu_get_cpu_events; |
7ae18a57 | 725 | armpmu->type = ARM_PMU_DEVICE_CPU; |
92f701e1 MR |
726 | } |
727 | ||
b0e89590 WD |
728 | /* |
729 | * CPU PMU identification and registration. | |
730 | */ | |
1b8873a0 JI |
731 | static int __init |
732 | init_hw_perf_events(void) | |
733 | { | |
734 | unsigned long cpuid = read_cpuid_id(); | |
735 | unsigned long implementor = (cpuid & 0xFF000000) >> 24; | |
736 | unsigned long part_number = (cpuid & 0xFFF0); | |
737 | ||
49e6a32f | 738 | /* ARM Ltd CPUs. */ |
1b8873a0 JI |
739 | if (0x41 == implementor) { |
740 | switch (part_number) { | |
741 | case 0xB360: /* ARM1136 */ | |
742 | case 0xB560: /* ARM1156 */ | |
743 | case 0xB760: /* ARM1176 */ | |
3cb314ba | 744 | armpmu = armv6pmu_init(); |
1b8873a0 JI |
745 | break; |
746 | case 0xB020: /* ARM11mpcore */ | |
3cb314ba | 747 | armpmu = armv6mpcore_pmu_init(); |
1b8873a0 | 748 | break; |
796d1295 | 749 | case 0xC080: /* Cortex-A8 */ |
3cb314ba | 750 | armpmu = armv7_a8_pmu_init(); |
796d1295 JP |
751 | break; |
752 | case 0xC090: /* Cortex-A9 */ | |
3cb314ba | 753 | armpmu = armv7_a9_pmu_init(); |
796d1295 | 754 | break; |
0c205cbe WD |
755 | case 0xC050: /* Cortex-A5 */ |
756 | armpmu = armv7_a5_pmu_init(); | |
757 | break; | |
14abd038 WD |
758 | case 0xC0F0: /* Cortex-A15 */ |
759 | armpmu = armv7_a15_pmu_init(); | |
760 | break; | |
49e6a32f WD |
761 | } |
762 | /* Intel CPUs [xscale]. */ | |
763 | } else if (0x69 == implementor) { | |
764 | part_number = (cpuid >> 13) & 0x7; | |
765 | switch (part_number) { | |
766 | case 1: | |
3cb314ba | 767 | armpmu = xscale1pmu_init(); |
49e6a32f WD |
768 | break; |
769 | case 2: | |
3cb314ba | 770 | armpmu = xscale2pmu_init(); |
49e6a32f | 771 | break; |
1b8873a0 JI |
772 | } |
773 | } | |
774 | ||
49e6a32f | 775 | if (armpmu) { |
796d1295 | 776 | pr_info("enabled with %s PMU driver, %d counters available\n", |
62994831 | 777 | armpmu->name, armpmu->num_events); |
92f701e1 | 778 | cpu_pmu_init(armpmu); |
8a16b34e | 779 | armpmu_register(armpmu, "cpu", PERF_TYPE_RAW); |
49e6a32f WD |
780 | } else { |
781 | pr_info("no hardware support available\n"); | |
49e6a32f | 782 | } |
1b8873a0 JI |
783 | |
784 | return 0; | |
785 | } | |
004417a6 | 786 | early_initcall(init_hw_perf_events); |
1b8873a0 JI |
787 | |
788 | /* | |
789 | * Callchain handling code. | |
790 | */ | |
1b8873a0 JI |
791 | |
792 | /* | |
793 | * The registers we're interested in are at the end of the variable | |
794 | * length saved register structure. The fp points at the end of this | |
795 | * structure so the address of this struct is: | |
796 | * (struct frame_tail *)(xxx->fp)-1 | |
797 | * | |
798 | * This code has been adapted from the ARM OProfile support. | |
799 | */ | |
800 | struct frame_tail { | |
4d6b7a77 WD |
801 | struct frame_tail __user *fp; |
802 | unsigned long sp; | |
803 | unsigned long lr; | |
1b8873a0 JI |
804 | } __attribute__((packed)); |
805 | ||
806 | /* | |
807 | * Get the return address for a single stackframe and return a pointer to the | |
808 | * next frame tail. | |
809 | */ | |
4d6b7a77 WD |
810 | static struct frame_tail __user * |
811 | user_backtrace(struct frame_tail __user *tail, | |
1b8873a0 JI |
812 | struct perf_callchain_entry *entry) |
813 | { | |
814 | struct frame_tail buftail; | |
815 | ||
816 | /* Also check accessibility of one struct frame_tail beyond */ | |
817 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | |
818 | return NULL; | |
819 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | |
820 | return NULL; | |
821 | ||
70791ce9 | 822 | perf_callchain_store(entry, buftail.lr); |
1b8873a0 JI |
823 | |
824 | /* | |
825 | * Frame pointers should strictly progress back up the stack | |
826 | * (towards higher addresses). | |
827 | */ | |
cb06199b | 828 | if (tail + 1 >= buftail.fp) |
1b8873a0 JI |
829 | return NULL; |
830 | ||
831 | return buftail.fp - 1; | |
832 | } | |
833 | ||
56962b44 FW |
834 | void |
835 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 | 836 | { |
4d6b7a77 | 837 | struct frame_tail __user *tail; |
1b8873a0 | 838 | |
1b8873a0 | 839 | |
4d6b7a77 | 840 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
1b8873a0 | 841 | |
860ad782 SR |
842 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
843 | tail && !((unsigned long)tail & 0x3)) | |
1b8873a0 JI |
844 | tail = user_backtrace(tail, entry); |
845 | } | |
846 | ||
847 | /* | |
848 | * Gets called by walk_stackframe() for every stackframe. This will be called | |
849 | * whist unwinding the stackframe and is like a subroutine return so we use | |
850 | * the PC. | |
851 | */ | |
852 | static int | |
853 | callchain_trace(struct stackframe *fr, | |
854 | void *data) | |
855 | { | |
856 | struct perf_callchain_entry *entry = data; | |
70791ce9 | 857 | perf_callchain_store(entry, fr->pc); |
1b8873a0 JI |
858 | return 0; |
859 | } | |
860 | ||
56962b44 FW |
861 | void |
862 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 JI |
863 | { |
864 | struct stackframe fr; | |
865 | ||
1b8873a0 JI |
866 | fr.fp = regs->ARM_fp; |
867 | fr.sp = regs->ARM_sp; | |
868 | fr.lr = regs->ARM_lr; | |
869 | fr.pc = regs->ARM_pc; | |
870 | walk_stackframe(&fr, callchain_trace, entry); | |
871 | } |