Commit | Line | Data |
---|---|---|
1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 JI |
9 | * This code is based on the sparc64 perf event code, which is in turn based |
10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | |
11 | * code. | |
12 | */ | |
13 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
14 | ||
7325eaec | 15 | #include <linux/bitmap.h> |
1b8873a0 JI |
16 | #include <linux/interrupt.h> |
17 | #include <linux/kernel.h> | |
ecea4ab6 | 18 | #include <linux/export.h> |
04236f9f | 19 | #include <linux/of.h> |
1b8873a0 | 20 | #include <linux/perf_event.h> |
49c006b9 | 21 | #include <linux/platform_device.h> |
1b8873a0 JI |
22 | #include <linux/spinlock.h> |
23 | #include <linux/uaccess.h> | |
7be2958e | 24 | #include <linux/pm_runtime.h> |
1b8873a0 JI |
25 | |
26 | #include <asm/cputype.h> | |
27 | #include <asm/irq.h> | |
28 | #include <asm/irq_regs.h> | |
29 | #include <asm/pmu.h> | |
30 | #include <asm/stacktrace.h> | |
31 | ||
6dbc0029 WD |
32 | /* Set at runtime when we know what CPU type we are. */ |
33 | static struct arm_pmu *cpu_pmu; | |
1b8873a0 | 34 | |
3fc2c830 MR |
35 | static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events); |
36 | static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask); | |
8be3f9a2 | 37 | static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events); |
181193f3 | 38 | |
6dbc0029 WD |
39 | /* |
40 | * Despite the names, these two functions are CPU-specific and are used | |
41 | * by the OProfile/perf code. | |
42 | */ | |
4295b898 | 43 | const char *perf_pmu_name(void) |
181193f3 | 44 | { |
4295b898 WD |
45 | if (!cpu_pmu) |
46 | return NULL; | |
181193f3 | 47 | |
4295b898 | 48 | return cpu_pmu->pmu.name; |
181193f3 | 49 | } |
4295b898 | 50 | EXPORT_SYMBOL_GPL(perf_pmu_name); |
181193f3 | 51 | |
feb45d06 | 52 | int perf_num_counters(void) |
929f5199 WD |
53 | { |
54 | int max_events = 0; | |
55 | ||
8be3f9a2 MR |
56 | if (cpu_pmu != NULL) |
57 | max_events = cpu_pmu->num_events; | |
929f5199 WD |
58 | |
59 | return max_events; | |
60 | } | |
3bf101ba MF |
61 | EXPORT_SYMBOL_GPL(perf_num_counters); |
62 | ||
1b8873a0 | 63 | static int |
e1f431b5 MR |
64 | armpmu_map_cache_event(const unsigned (*cache_map) |
65 | [PERF_COUNT_HW_CACHE_MAX] | |
66 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
67 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
68 | u64 config) | |
1b8873a0 JI |
69 | { |
70 | unsigned int cache_type, cache_op, cache_result, ret; | |
71 | ||
72 | cache_type = (config >> 0) & 0xff; | |
73 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
74 | return -EINVAL; | |
75 | ||
76 | cache_op = (config >> 8) & 0xff; | |
77 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
78 | return -EINVAL; | |
79 | ||
80 | cache_result = (config >> 16) & 0xff; | |
81 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
82 | return -EINVAL; | |
83 | ||
e1f431b5 | 84 | ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
85 | |
86 | if (ret == CACHE_OP_UNSUPPORTED) | |
87 | return -ENOENT; | |
88 | ||
89 | return ret; | |
90 | } | |
91 | ||
84fee97a | 92 | static int |
6dbc0029 | 93 | armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) |
84fee97a | 94 | { |
e1f431b5 MR |
95 | int mapping = (*event_map)[config]; |
96 | return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; | |
84fee97a WD |
97 | } |
98 | ||
99 | static int | |
e1f431b5 | 100 | armpmu_map_raw_event(u32 raw_event_mask, u64 config) |
84fee97a | 101 | { |
e1f431b5 MR |
102 | return (int)(config & raw_event_mask); |
103 | } | |
104 | ||
6dbc0029 WD |
105 | int |
106 | armpmu_map_event(struct perf_event *event, | |
107 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], | |
108 | const unsigned (*cache_map) | |
109 | [PERF_COUNT_HW_CACHE_MAX] | |
110 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
111 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
112 | u32 raw_event_mask) | |
e1f431b5 MR |
113 | { |
114 | u64 config = event->attr.config; | |
115 | ||
116 | switch (event->attr.type) { | |
117 | case PERF_TYPE_HARDWARE: | |
6dbc0029 | 118 | return armpmu_map_hw_event(event_map, config); |
e1f431b5 MR |
119 | case PERF_TYPE_HW_CACHE: |
120 | return armpmu_map_cache_event(cache_map, config); | |
121 | case PERF_TYPE_RAW: | |
122 | return armpmu_map_raw_event(raw_event_mask, config); | |
123 | } | |
124 | ||
125 | return -ENOENT; | |
84fee97a WD |
126 | } |
127 | ||
0ce47080 | 128 | int |
1b8873a0 JI |
129 | armpmu_event_set_period(struct perf_event *event, |
130 | struct hw_perf_event *hwc, | |
131 | int idx) | |
132 | { | |
8a16b34e | 133 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
e7850595 | 134 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
135 | s64 period = hwc->sample_period; |
136 | int ret = 0; | |
137 | ||
138 | if (unlikely(left <= -period)) { | |
139 | left = period; | |
e7850595 | 140 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
141 | hwc->last_period = period; |
142 | ret = 1; | |
143 | } | |
144 | ||
145 | if (unlikely(left <= 0)) { | |
146 | left += period; | |
e7850595 | 147 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
148 | hwc->last_period = period; |
149 | ret = 1; | |
150 | } | |
151 | ||
152 | if (left > (s64)armpmu->max_period) | |
153 | left = armpmu->max_period; | |
154 | ||
e7850595 | 155 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 JI |
156 | |
157 | armpmu->write_counter(idx, (u64)(-left) & 0xffffffff); | |
158 | ||
159 | perf_event_update_userpage(event); | |
160 | ||
161 | return ret; | |
162 | } | |
163 | ||
0ce47080 | 164 | u64 |
1b8873a0 JI |
165 | armpmu_event_update(struct perf_event *event, |
166 | struct hw_perf_event *hwc, | |
57273471 | 167 | int idx) |
1b8873a0 | 168 | { |
8a16b34e | 169 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
a737823d | 170 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
171 | |
172 | again: | |
e7850595 | 173 | prev_raw_count = local64_read(&hwc->prev_count); |
1b8873a0 JI |
174 | new_raw_count = armpmu->read_counter(idx); |
175 | ||
e7850595 | 176 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
177 | new_raw_count) != prev_raw_count) |
178 | goto again; | |
179 | ||
57273471 | 180 | delta = (new_raw_count - prev_raw_count) & armpmu->max_period; |
1b8873a0 | 181 | |
e7850595 PZ |
182 | local64_add(delta, &event->count); |
183 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
184 | |
185 | return new_raw_count; | |
186 | } | |
187 | ||
188 | static void | |
a4eaf7f1 | 189 | armpmu_read(struct perf_event *event) |
1b8873a0 | 190 | { |
1b8873a0 | 191 | struct hw_perf_event *hwc = &event->hw; |
1b8873a0 | 192 | |
a4eaf7f1 PZ |
193 | /* Don't read disabled counters! */ |
194 | if (hwc->idx < 0) | |
195 | return; | |
1b8873a0 | 196 | |
57273471 | 197 | armpmu_event_update(event, hwc, hwc->idx); |
1b8873a0 JI |
198 | } |
199 | ||
200 | static void | |
a4eaf7f1 | 201 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 | 202 | { |
8a16b34e | 203 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
204 | struct hw_perf_event *hwc = &event->hw; |
205 | ||
a4eaf7f1 PZ |
206 | /* |
207 | * ARM pmu always has to update the counter, so ignore | |
208 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
209 | */ | |
210 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
211 | armpmu->disable(hwc, hwc->idx); | |
57273471 | 212 | armpmu_event_update(event, hwc, hwc->idx); |
a4eaf7f1 PZ |
213 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
214 | } | |
1b8873a0 JI |
215 | } |
216 | ||
217 | static void | |
a4eaf7f1 | 218 | armpmu_start(struct perf_event *event, int flags) |
1b8873a0 | 219 | { |
8a16b34e | 220 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
221 | struct hw_perf_event *hwc = &event->hw; |
222 | ||
a4eaf7f1 PZ |
223 | /* |
224 | * ARM pmu always has to reprogram the period, so ignore | |
225 | * PERF_EF_RELOAD, see the comment below. | |
226 | */ | |
227 | if (flags & PERF_EF_RELOAD) | |
228 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
229 | ||
230 | hwc->state = 0; | |
1b8873a0 JI |
231 | /* |
232 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 233 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
234 | * may have been left counting. If we don't do this step then we may |
235 | * get an interrupt too soon or *way* too late if the overflow has | |
236 | * happened since disabling. | |
237 | */ | |
238 | armpmu_event_set_period(event, hwc, hwc->idx); | |
239 | armpmu->enable(hwc, hwc->idx); | |
240 | } | |
241 | ||
a4eaf7f1 PZ |
242 | static void |
243 | armpmu_del(struct perf_event *event, int flags) | |
244 | { | |
8a16b34e | 245 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 246 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
a4eaf7f1 PZ |
247 | struct hw_perf_event *hwc = &event->hw; |
248 | int idx = hwc->idx; | |
249 | ||
250 | WARN_ON(idx < 0); | |
251 | ||
a4eaf7f1 | 252 | armpmu_stop(event, PERF_EF_UPDATE); |
8be3f9a2 MR |
253 | hw_events->events[idx] = NULL; |
254 | clear_bit(idx, hw_events->used_mask); | |
a4eaf7f1 PZ |
255 | |
256 | perf_event_update_userpage(event); | |
257 | } | |
258 | ||
1b8873a0 | 259 | static int |
a4eaf7f1 | 260 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 | 261 | { |
8a16b34e | 262 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 263 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
1b8873a0 JI |
264 | struct hw_perf_event *hwc = &event->hw; |
265 | int idx; | |
266 | int err = 0; | |
267 | ||
33696fc0 | 268 | perf_pmu_disable(event->pmu); |
24cd7f54 | 269 | |
1b8873a0 | 270 | /* If we don't have a space for the counter then finish early. */ |
8be3f9a2 | 271 | idx = armpmu->get_event_idx(hw_events, hwc); |
1b8873a0 JI |
272 | if (idx < 0) { |
273 | err = idx; | |
274 | goto out; | |
275 | } | |
276 | ||
277 | /* | |
278 | * If there is an event in the counter we are going to use then make | |
279 | * sure it is disabled. | |
280 | */ | |
281 | event->hw.idx = idx; | |
282 | armpmu->disable(hwc, idx); | |
8be3f9a2 | 283 | hw_events->events[idx] = event; |
1b8873a0 | 284 | |
a4eaf7f1 PZ |
285 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
286 | if (flags & PERF_EF_START) | |
287 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
288 | |
289 | /* Propagate our changes to the userspace mapping. */ | |
290 | perf_event_update_userpage(event); | |
291 | ||
292 | out: | |
33696fc0 | 293 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
294 | return err; |
295 | } | |
296 | ||
1b8873a0 | 297 | static int |
8be3f9a2 | 298 | validate_event(struct pmu_hw_events *hw_events, |
1b8873a0 JI |
299 | struct perf_event *event) |
300 | { | |
8a16b34e | 301 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 302 | struct hw_perf_event fake_event = event->hw; |
7b9f72c6 | 303 | struct pmu *leader_pmu = event->group_leader->pmu; |
1b8873a0 | 304 | |
7b9f72c6 | 305 | if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF) |
65b4711f | 306 | return 1; |
1b8873a0 | 307 | |
8be3f9a2 | 308 | return armpmu->get_event_idx(hw_events, &fake_event) >= 0; |
1b8873a0 JI |
309 | } |
310 | ||
311 | static int | |
312 | validate_group(struct perf_event *event) | |
313 | { | |
314 | struct perf_event *sibling, *leader = event->group_leader; | |
8be3f9a2 | 315 | struct pmu_hw_events fake_pmu; |
bce34d14 | 316 | DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS); |
1b8873a0 | 317 | |
bce34d14 WD |
318 | /* |
319 | * Initialise the fake PMU. We only need to populate the | |
320 | * used_mask for the purposes of validation. | |
321 | */ | |
322 | memset(fake_used_mask, 0, sizeof(fake_used_mask)); | |
323 | fake_pmu.used_mask = fake_used_mask; | |
1b8873a0 JI |
324 | |
325 | if (!validate_event(&fake_pmu, leader)) | |
aa2bc1ad | 326 | return -EINVAL; |
1b8873a0 JI |
327 | |
328 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
329 | if (!validate_event(&fake_pmu, sibling)) | |
aa2bc1ad | 330 | return -EINVAL; |
1b8873a0 JI |
331 | } |
332 | ||
333 | if (!validate_event(&fake_pmu, event)) | |
aa2bc1ad | 334 | return -EINVAL; |
1b8873a0 JI |
335 | |
336 | return 0; | |
337 | } | |
338 | ||
0e25a5c9 RV |
339 | static irqreturn_t armpmu_platform_irq(int irq, void *dev) |
340 | { | |
8a16b34e | 341 | struct arm_pmu *armpmu = (struct arm_pmu *) dev; |
a9356a04 MR |
342 | struct platform_device *plat_device = armpmu->plat_device; |
343 | struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev); | |
0e25a5c9 RV |
344 | |
345 | return plat->handle_irq(irq, dev, armpmu->handle_irq); | |
346 | } | |
347 | ||
0b390e21 | 348 | static void |
8a16b34e | 349 | armpmu_release_hardware(struct arm_pmu *armpmu) |
0b390e21 WD |
350 | { |
351 | int i, irq, irqs; | |
a9356a04 | 352 | struct platform_device *pmu_device = armpmu->plat_device; |
0b390e21 WD |
353 | |
354 | irqs = min(pmu_device->num_resources, num_possible_cpus()); | |
355 | ||
356 | for (i = 0; i < irqs; ++i) { | |
357 | if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs)) | |
358 | continue; | |
359 | irq = platform_get_irq(pmu_device, i); | |
7be2958e | 360 | if (irq >= 0) |
8a16b34e | 361 | free_irq(irq, armpmu); |
0b390e21 WD |
362 | } |
363 | ||
7be2958e | 364 | pm_runtime_put_sync(&pmu_device->dev); |
0b390e21 WD |
365 | } |
366 | ||
1b8873a0 | 367 | static int |
8a16b34e | 368 | armpmu_reserve_hardware(struct arm_pmu *armpmu) |
1b8873a0 | 369 | { |
0e25a5c9 RV |
370 | struct arm_pmu_platdata *plat; |
371 | irq_handler_t handle_irq; | |
b0e89590 | 372 | int i, err, irq, irqs; |
a9356a04 | 373 | struct platform_device *pmu_device = armpmu->plat_device; |
1b8873a0 | 374 | |
e5a21327 WD |
375 | if (!pmu_device) |
376 | return -ENODEV; | |
377 | ||
0e25a5c9 RV |
378 | plat = dev_get_platdata(&pmu_device->dev); |
379 | if (plat && plat->handle_irq) | |
380 | handle_irq = armpmu_platform_irq; | |
381 | else | |
382 | handle_irq = armpmu->handle_irq; | |
383 | ||
0b390e21 | 384 | irqs = min(pmu_device->num_resources, num_possible_cpus()); |
b0e89590 | 385 | if (irqs < 1) { |
1b8873a0 JI |
386 | pr_err("no irqs for PMUs defined\n"); |
387 | return -ENODEV; | |
388 | } | |
389 | ||
7be2958e JH |
390 | pm_runtime_get_sync(&pmu_device->dev); |
391 | ||
b0e89590 | 392 | for (i = 0; i < irqs; ++i) { |
0b390e21 | 393 | err = 0; |
49c006b9 WD |
394 | irq = platform_get_irq(pmu_device, i); |
395 | if (irq < 0) | |
396 | continue; | |
397 | ||
b0e89590 WD |
398 | /* |
399 | * If we have a single PMU interrupt that we can't shift, | |
400 | * assume that we're running on a uniprocessor machine and | |
0b390e21 | 401 | * continue. Otherwise, continue without this interrupt. |
b0e89590 | 402 | */ |
0b390e21 WD |
403 | if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { |
404 | pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", | |
405 | irq, i); | |
406 | continue; | |
b0e89590 WD |
407 | } |
408 | ||
0e25a5c9 | 409 | err = request_irq(irq, handle_irq, |
ddee87f2 | 410 | IRQF_DISABLED | IRQF_NOBALANCING, |
8a16b34e | 411 | "arm-pmu", armpmu); |
1b8873a0 | 412 | if (err) { |
b0e89590 WD |
413 | pr_err("unable to request IRQ%d for ARM PMU counters\n", |
414 | irq); | |
8a16b34e | 415 | armpmu_release_hardware(armpmu); |
0b390e21 | 416 | return err; |
7be2958e | 417 | } |
1b8873a0 | 418 | |
0b390e21 | 419 | cpumask_set_cpu(i, &armpmu->active_irqs); |
49c006b9 | 420 | } |
1b8873a0 | 421 | |
0b390e21 | 422 | return 0; |
1b8873a0 JI |
423 | } |
424 | ||
1b8873a0 JI |
425 | static void |
426 | hw_perf_event_destroy(struct perf_event *event) | |
427 | { | |
8a16b34e | 428 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
03b7898d MR |
429 | atomic_t *active_events = &armpmu->active_events; |
430 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; | |
431 | ||
432 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { | |
8a16b34e | 433 | armpmu_release_hardware(armpmu); |
03b7898d | 434 | mutex_unlock(pmu_reserve_mutex); |
1b8873a0 JI |
435 | } |
436 | } | |
437 | ||
05d22fde WD |
438 | static int |
439 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
440 | { | |
441 | return attr->exclude_idle || attr->exclude_user || | |
442 | attr->exclude_kernel || attr->exclude_hv; | |
443 | } | |
444 | ||
1b8873a0 JI |
445 | static int |
446 | __hw_perf_event_init(struct perf_event *event) | |
447 | { | |
8a16b34e | 448 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
449 | struct hw_perf_event *hwc = &event->hw; |
450 | int mapping, err; | |
451 | ||
e1f431b5 | 452 | mapping = armpmu->map_event(event); |
1b8873a0 JI |
453 | |
454 | if (mapping < 0) { | |
455 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
456 | event->attr.config); | |
457 | return mapping; | |
458 | } | |
459 | ||
05d22fde WD |
460 | /* |
461 | * We don't assign an index until we actually place the event onto | |
462 | * hardware. Use -1 to signify that we haven't decided where to put it | |
463 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
464 | * clever allocation or constraints checking at this point. | |
465 | */ | |
466 | hwc->idx = -1; | |
467 | hwc->config_base = 0; | |
468 | hwc->config = 0; | |
469 | hwc->event_base = 0; | |
470 | ||
1b8873a0 JI |
471 | /* |
472 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 473 | */ |
05d22fde WD |
474 | if ((!armpmu->set_event_filter || |
475 | armpmu->set_event_filter(hwc, &event->attr)) && | |
476 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
477 | pr_debug("ARM performance counters do not support " |
478 | "mode exclusion\n"); | |
fdeb8e35 | 479 | return -EOPNOTSUPP; |
1b8873a0 JI |
480 | } |
481 | ||
482 | /* | |
05d22fde | 483 | * Store the event encoding into the config_base field. |
1b8873a0 | 484 | */ |
05d22fde | 485 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 JI |
486 | |
487 | if (!hwc->sample_period) { | |
57273471 WD |
488 | /* |
489 | * For non-sampling runs, limit the sample_period to half | |
490 | * of the counter width. That way, the new counter value | |
491 | * is far less likely to overtake the previous one unless | |
492 | * you have some serious IRQ latency issues. | |
493 | */ | |
494 | hwc->sample_period = armpmu->max_period >> 1; | |
1b8873a0 | 495 | hwc->last_period = hwc->sample_period; |
e7850595 | 496 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
497 | } |
498 | ||
499 | err = 0; | |
500 | if (event->group_leader != event) { | |
501 | err = validate_group(event); | |
502 | if (err) | |
503 | return -EINVAL; | |
504 | } | |
505 | ||
506 | return err; | |
507 | } | |
508 | ||
b0a873eb | 509 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 | 510 | { |
8a16b34e | 511 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 512 | int err = 0; |
03b7898d | 513 | atomic_t *active_events = &armpmu->active_events; |
1b8873a0 | 514 | |
2481c5fa SE |
515 | /* does not support taken branch sampling */ |
516 | if (has_branch_stack(event)) | |
517 | return -EOPNOTSUPP; | |
518 | ||
e1f431b5 | 519 | if (armpmu->map_event(event) == -ENOENT) |
b0a873eb | 520 | return -ENOENT; |
b0a873eb | 521 | |
1b8873a0 JI |
522 | event->destroy = hw_perf_event_destroy; |
523 | ||
03b7898d MR |
524 | if (!atomic_inc_not_zero(active_events)) { |
525 | mutex_lock(&armpmu->reserve_mutex); | |
526 | if (atomic_read(active_events) == 0) | |
8a16b34e | 527 | err = armpmu_reserve_hardware(armpmu); |
1b8873a0 JI |
528 | |
529 | if (!err) | |
03b7898d MR |
530 | atomic_inc(active_events); |
531 | mutex_unlock(&armpmu->reserve_mutex); | |
1b8873a0 JI |
532 | } |
533 | ||
534 | if (err) | |
b0a873eb | 535 | return err; |
1b8873a0 JI |
536 | |
537 | err = __hw_perf_event_init(event); | |
538 | if (err) | |
539 | hw_perf_event_destroy(event); | |
540 | ||
b0a873eb | 541 | return err; |
1b8873a0 JI |
542 | } |
543 | ||
a4eaf7f1 | 544 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 | 545 | { |
8be3f9a2 | 546 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
8be3f9a2 | 547 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
7325eaec | 548 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); |
1b8873a0 | 549 | |
f4f38430 WD |
550 | if (enabled) |
551 | armpmu->start(); | |
1b8873a0 JI |
552 | } |
553 | ||
a4eaf7f1 | 554 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 555 | { |
8a16b34e | 556 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
48957155 | 557 | armpmu->stop(); |
1b8873a0 JI |
558 | } |
559 | ||
7be2958e JH |
560 | #ifdef CONFIG_PM_RUNTIME |
561 | static int armpmu_runtime_resume(struct device *dev) | |
562 | { | |
563 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); | |
564 | ||
565 | if (plat && plat->runtime_resume) | |
566 | return plat->runtime_resume(dev); | |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
571 | static int armpmu_runtime_suspend(struct device *dev) | |
572 | { | |
573 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); | |
574 | ||
575 | if (plat && plat->runtime_suspend) | |
576 | return plat->runtime_suspend(dev); | |
577 | ||
578 | return 0; | |
579 | } | |
580 | #endif | |
581 | ||
6dbc0029 WD |
582 | const struct dev_pm_ops armpmu_dev_pm_ops = { |
583 | SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL) | |
584 | }; | |
585 | ||
03b7898d MR |
586 | static void __init armpmu_init(struct arm_pmu *armpmu) |
587 | { | |
588 | atomic_set(&armpmu->active_events, 0); | |
589 | mutex_init(&armpmu->reserve_mutex); | |
8a16b34e MR |
590 | |
591 | armpmu->pmu = (struct pmu) { | |
592 | .pmu_enable = armpmu_enable, | |
593 | .pmu_disable = armpmu_disable, | |
594 | .event_init = armpmu_event_init, | |
595 | .add = armpmu_add, | |
596 | .del = armpmu_del, | |
597 | .start = armpmu_start, | |
598 | .stop = armpmu_stop, | |
599 | .read = armpmu_read, | |
600 | }; | |
601 | } | |
602 | ||
04236f9f | 603 | int armpmu_register(struct arm_pmu *armpmu, char *name, int type) |
8a16b34e MR |
604 | { |
605 | armpmu_init(armpmu); | |
04236f9f WD |
606 | pr_info("enabled with %s PMU driver, %d counters available\n", |
607 | armpmu->name, armpmu->num_events); | |
8a16b34e | 608 | return perf_pmu_register(&armpmu->pmu, name, type); |
03b7898d MR |
609 | } |
610 | ||
43eab878 WD |
611 | /* Include the PMU-specific implementations. */ |
612 | #include "perf_event_xscale.c" | |
613 | #include "perf_event_v6.c" | |
614 | #include "perf_event_v7.c" | |
49e6a32f | 615 | |
6dbc0029 | 616 | static struct pmu_hw_events *cpu_pmu_get_cpu_events(void) |
92f701e1 MR |
617 | { |
618 | return &__get_cpu_var(cpu_hw_events); | |
619 | } | |
620 | ||
04236f9f | 621 | static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu) |
92f701e1 | 622 | { |
0f78d2d5 MR |
623 | int cpu; |
624 | for_each_possible_cpu(cpu) { | |
8be3f9a2 | 625 | struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu); |
3fc2c830 MR |
626 | events->events = per_cpu(hw_events, cpu); |
627 | events->used_mask = per_cpu(used_mask, cpu); | |
0f78d2d5 MR |
628 | raw_spin_lock_init(&events->pmu_lock); |
629 | } | |
6dbc0029 | 630 | cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events; |
04236f9f WD |
631 | |
632 | /* Ensure the PMU has sane values out of reset. */ | |
633 | if (cpu_pmu && cpu_pmu->reset) | |
634 | on_each_cpu(cpu_pmu->reset, NULL, 1); | |
92f701e1 MR |
635 | } |
636 | ||
a0feb6db LP |
637 | /* |
638 | * PMU hardware loses all context when a CPU goes offline. | |
639 | * When a CPU is hotplugged back in, since some hardware registers are | |
640 | * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading | |
641 | * junk values out of them. | |
642 | */ | |
6dbc0029 WD |
643 | static int __cpuinit cpu_pmu_notify(struct notifier_block *b, |
644 | unsigned long action, void *hcpu) | |
a0feb6db LP |
645 | { |
646 | if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING) | |
647 | return NOTIFY_DONE; | |
648 | ||
649 | if (cpu_pmu && cpu_pmu->reset) | |
650 | cpu_pmu->reset(NULL); | |
651 | ||
652 | return NOTIFY_OK; | |
653 | } | |
654 | ||
6dbc0029 WD |
655 | static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = { |
656 | .notifier_call = cpu_pmu_notify, | |
04236f9f WD |
657 | }; |
658 | ||
659 | /* | |
660 | * PMU platform driver and devicetree bindings. | |
661 | */ | |
662 | static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = { | |
663 | {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init}, | |
664 | {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init}, | |
665 | {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init}, | |
666 | {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init}, | |
667 | {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init}, | |
668 | {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init}, | |
669 | {.compatible = "arm,arm1176-pmu", .data = armv6pmu_init}, | |
670 | {.compatible = "arm,arm1136-pmu", .data = armv6pmu_init}, | |
671 | {}, | |
672 | }; | |
673 | ||
674 | static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = { | |
675 | {.name = "arm-pmu"}, | |
676 | {}, | |
677 | }; | |
678 | ||
b0e89590 | 679 | /* |
04236f9f | 680 | * CPU PMU identification and probing. |
b0e89590 | 681 | */ |
04236f9f | 682 | static struct arm_pmu *__devinit probe_current_pmu(void) |
1b8873a0 | 683 | { |
04236f9f WD |
684 | struct arm_pmu *pmu = NULL; |
685 | int cpu = get_cpu(); | |
1b8873a0 JI |
686 | unsigned long cpuid = read_cpuid_id(); |
687 | unsigned long implementor = (cpuid & 0xFF000000) >> 24; | |
688 | unsigned long part_number = (cpuid & 0xFFF0); | |
689 | ||
04236f9f WD |
690 | pr_info("probing PMU on CPU %d\n", cpu); |
691 | ||
49e6a32f | 692 | /* ARM Ltd CPUs. */ |
1b8873a0 JI |
693 | if (0x41 == implementor) { |
694 | switch (part_number) { | |
695 | case 0xB360: /* ARM1136 */ | |
696 | case 0xB560: /* ARM1156 */ | |
697 | case 0xB760: /* ARM1176 */ | |
04236f9f | 698 | pmu = armv6pmu_init(); |
1b8873a0 JI |
699 | break; |
700 | case 0xB020: /* ARM11mpcore */ | |
04236f9f | 701 | pmu = armv6mpcore_pmu_init(); |
1b8873a0 | 702 | break; |
796d1295 | 703 | case 0xC080: /* Cortex-A8 */ |
04236f9f | 704 | pmu = armv7_a8_pmu_init(); |
796d1295 JP |
705 | break; |
706 | case 0xC090: /* Cortex-A9 */ | |
04236f9f | 707 | pmu = armv7_a9_pmu_init(); |
796d1295 | 708 | break; |
0c205cbe | 709 | case 0xC050: /* Cortex-A5 */ |
04236f9f | 710 | pmu = armv7_a5_pmu_init(); |
0c205cbe | 711 | break; |
14abd038 | 712 | case 0xC0F0: /* Cortex-A15 */ |
04236f9f | 713 | pmu = armv7_a15_pmu_init(); |
14abd038 | 714 | break; |
d33c88c6 | 715 | case 0xC070: /* Cortex-A7 */ |
04236f9f | 716 | pmu = armv7_a7_pmu_init(); |
d33c88c6 | 717 | break; |
49e6a32f WD |
718 | } |
719 | /* Intel CPUs [xscale]. */ | |
720 | } else if (0x69 == implementor) { | |
721 | part_number = (cpuid >> 13) & 0x7; | |
722 | switch (part_number) { | |
723 | case 1: | |
04236f9f | 724 | pmu = xscale1pmu_init(); |
49e6a32f WD |
725 | break; |
726 | case 2: | |
04236f9f | 727 | pmu = xscale2pmu_init(); |
49e6a32f | 728 | break; |
1b8873a0 JI |
729 | } |
730 | } | |
731 | ||
04236f9f WD |
732 | put_cpu(); |
733 | return pmu; | |
734 | } | |
735 | ||
736 | static int __devinit cpu_pmu_device_probe(struct platform_device *pdev) | |
737 | { | |
738 | const struct of_device_id *of_id; | |
739 | struct arm_pmu *(*init_fn)(void); | |
740 | struct device_node *node = pdev->dev.of_node; | |
741 | ||
8be3f9a2 | 742 | if (cpu_pmu) { |
04236f9f WD |
743 | pr_info("attempt to register multiple PMU devices!"); |
744 | return -ENOSPC; | |
745 | } | |
746 | ||
747 | if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) { | |
748 | init_fn = of_id->data; | |
749 | cpu_pmu = init_fn(); | |
49e6a32f | 750 | } else { |
04236f9f | 751 | cpu_pmu = probe_current_pmu(); |
49e6a32f | 752 | } |
1b8873a0 | 753 | |
04236f9f WD |
754 | if (!cpu_pmu) |
755 | return -ENODEV; | |
756 | ||
757 | cpu_pmu->plat_device = pdev; | |
758 | cpu_pmu_init(cpu_pmu); | |
6dbc0029 | 759 | register_cpu_notifier(&cpu_pmu_hotplug_notifier); |
04236f9f WD |
760 | armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW); |
761 | ||
1b8873a0 JI |
762 | return 0; |
763 | } | |
04236f9f WD |
764 | |
765 | static struct platform_driver cpu_pmu_driver = { | |
766 | .driver = { | |
767 | .name = "arm-pmu", | |
768 | .pm = &armpmu_dev_pm_ops, | |
769 | .of_match_table = cpu_pmu_of_device_ids, | |
770 | }, | |
771 | .probe = cpu_pmu_device_probe, | |
772 | .id_table = cpu_pmu_plat_device_ids, | |
773 | }; | |
774 | ||
775 | static int __init register_pmu_driver(void) | |
776 | { | |
777 | return platform_driver_register(&cpu_pmu_driver); | |
778 | } | |
779 | device_initcall(register_pmu_driver); | |
1b8873a0 JI |
780 | |
781 | /* | |
782 | * Callchain handling code. | |
783 | */ | |
1b8873a0 JI |
784 | |
785 | /* | |
786 | * The registers we're interested in are at the end of the variable | |
787 | * length saved register structure. The fp points at the end of this | |
788 | * structure so the address of this struct is: | |
789 | * (struct frame_tail *)(xxx->fp)-1 | |
790 | * | |
791 | * This code has been adapted from the ARM OProfile support. | |
792 | */ | |
793 | struct frame_tail { | |
4d6b7a77 WD |
794 | struct frame_tail __user *fp; |
795 | unsigned long sp; | |
796 | unsigned long lr; | |
1b8873a0 JI |
797 | } __attribute__((packed)); |
798 | ||
799 | /* | |
800 | * Get the return address for a single stackframe and return a pointer to the | |
801 | * next frame tail. | |
802 | */ | |
4d6b7a77 WD |
803 | static struct frame_tail __user * |
804 | user_backtrace(struct frame_tail __user *tail, | |
1b8873a0 JI |
805 | struct perf_callchain_entry *entry) |
806 | { | |
807 | struct frame_tail buftail; | |
808 | ||
809 | /* Also check accessibility of one struct frame_tail beyond */ | |
810 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | |
811 | return NULL; | |
812 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | |
813 | return NULL; | |
814 | ||
70791ce9 | 815 | perf_callchain_store(entry, buftail.lr); |
1b8873a0 JI |
816 | |
817 | /* | |
818 | * Frame pointers should strictly progress back up the stack | |
819 | * (towards higher addresses). | |
820 | */ | |
cb06199b | 821 | if (tail + 1 >= buftail.fp) |
1b8873a0 JI |
822 | return NULL; |
823 | ||
824 | return buftail.fp - 1; | |
825 | } | |
826 | ||
56962b44 FW |
827 | void |
828 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 | 829 | { |
4d6b7a77 | 830 | struct frame_tail __user *tail; |
1b8873a0 | 831 | |
1b8873a0 | 832 | |
4d6b7a77 | 833 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
1b8873a0 | 834 | |
860ad782 SR |
835 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
836 | tail && !((unsigned long)tail & 0x3)) | |
1b8873a0 JI |
837 | tail = user_backtrace(tail, entry); |
838 | } | |
839 | ||
840 | /* | |
841 | * Gets called by walk_stackframe() for every stackframe. This will be called | |
842 | * whist unwinding the stackframe and is like a subroutine return so we use | |
843 | * the PC. | |
844 | */ | |
845 | static int | |
846 | callchain_trace(struct stackframe *fr, | |
847 | void *data) | |
848 | { | |
849 | struct perf_callchain_entry *entry = data; | |
70791ce9 | 850 | perf_callchain_store(entry, fr->pc); |
1b8873a0 JI |
851 | return 0; |
852 | } | |
853 | ||
56962b44 FW |
854 | void |
855 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 JI |
856 | { |
857 | struct stackframe fr; | |
858 | ||
1b8873a0 JI |
859 | fr.fp = regs->ARM_fp; |
860 | fr.sp = regs->ARM_sp; | |
861 | fr.lr = regs->ARM_lr; | |
862 | fr.pc = regs->ARM_pc; | |
863 | walk_stackframe(&fr, callchain_trace, entry); | |
864 | } |