[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9260.c

/*
 * arch/arm/mach-at91/at91sam9260.c
 *
 *  Copyright (C) 2006 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>
#include <linux/clk/at91_pmc.h>

#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9260.h>
#include <mach/hardware.h>

#include "at91_aic.h"
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
#include "sam9_smc.h"
#include "pm.h"

#if defined(CONFIG_OLD_CLK_AT91)
#include "clock.h"
/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk adc_clk = {
	.name		= "adc_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_ADC,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk adc_op_clk = {
	.name		= "adc_op_clk",
	.type		= CLK_TYPE_PERIPHERAL,
	.rate_hz	= 5000000,
};

static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
	.name		= "mci_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_MCI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
	.name		= "udc_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_UDP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
	.name		= "twi_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TWI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc_clk = {
	.name		= "ssc_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_SSC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
	.name		= "tc0_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
	.name		= "tc1_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
	.name		= "tc2_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
	.name		= "ohci_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_UHP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
	.name		= "pclk",
	.pmc_mask	= 1 << AT91SAM9260_ID_EMAC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
	.name		= "isi_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_ISI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_US3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart4_clk = {
	.name		= "usart4_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_US4,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart5_clk = {
	.name		= "usart5_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_US5,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc3_clk = {
	.name		= "tc3_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TC3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc4_clk = {
	.name		= "tc4_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TC4,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc5_clk = {
	.name		= "tc5_clk",
	.pmc_mask	= 1 << AT91SAM9260_ID_TC5,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&adc_clk,
	&adc_op_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&mmc_clk,
	&udc_clk,
	&twi_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc_clk,
	&tc0_clk,
	&tc1_clk,
	&tc2_clk,
	&ohci_clk,
	&macb_clk,
	&isi_clk,
	&usart3_clk,
	&usart4_clk,
	&usart5_clk,
	&tc3_clk,
	&tc4_clk,
	&tc5_clk,
	// irq0 .. irq2
};

static struct clk_lookup periph_clocks_lookups[] = {
	/* One additional fake clock for macb_hclk */
	CLKDEV_CON_ID("hclk", &macb_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
	CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
	/* more usart lookup table for DT entries */
	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
	CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
	CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
	/* more tc lookup table for DT entries */
	CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
	CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
	/* fake hclk clock */
	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
	CLKDEV_CON_ID("pioA", &pioA_clk),
	CLKDEV_CON_ID("pioB", &pioB_clk),
	CLKDEV_CON_ID("pioC", &pioC_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
};

/*
 * The two programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};

static void __init at91sam9260_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
}
#else
#define at91sam9260_register_clocks NULL
#endif

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
	{
		.id		= AT91SAM9260_ID_PIOA,
		.regbase	= AT91SAM9260_BASE_PIOA,
	}, {
		.id		= AT91SAM9260_ID_PIOB,
		.regbase	= AT91SAM9260_BASE_PIOB,
	}, {
		.id		= AT91SAM9260_ID_PIOC,
		.regbase	= AT91SAM9260_BASE_PIOC,
	}
};

/* --------------------------------------------------------------------
 *  AT91SAM9260 processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9xe_map_io(void)
{
	unsigned long sram_size;

	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
		case AT91_CIDR_SRAMSIZ_32K:
			sram_size = 2 * SZ_16K;
			break;
		case AT91_CIDR_SRAMSIZ_16K:
		default:
			sram_size = SZ_16K;
	}

	at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
}

static void __init at91sam9260_map_io(void)
{
	if (cpu_is_at91sam9xe())
		at91sam9xe_map_io();
	else if (cpu_is_at91sam9g20())
		at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
	else
		at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
}

static void __init at91sam9260_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
	at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
	at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
	at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
	at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
	at91_pm_set_standby(at91sam9_sdram_standby);
}

static void __init at91sam9260_initialize(void)
{
	arm_pm_idle = at91sam9_idle;
	arm_pm_restart = at91sam9_alt_restart;

	at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9260_gpio, 3);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	0,	/* Analog-to-Digital Converter */
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	0,	/* Multimedia Card Interface */
	2,	/* USB Device Port */
	6,	/* Two-Wire Interface */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	5,	/* Serial Synchronous Controller */
	0,
	0,
	0,	/* Timer Counter 0 */
	0,	/* Timer Counter 1 */
	0,	/* Timer Counter 2 */
	2,	/* USB Host port */
	3,	/* Ethernet */
	0,	/* Image Sensor Interface */
	5,	/* USART 3 */
	5,	/* USART 4 */
	5,	/* USART 5 */
	0,	/* Timer Counter 3 */
	0,	/* Timer Counter 4 */
	0,	/* Timer Counter 5 */
	0,	/* Advanced Interrupt Controller */
	0,	/* Advanced Interrupt Controller */
	0,	/* Advanced Interrupt Controller */
};

AT91_SOC_START(at91sam9260)
	.map_io = at91sam9260_map_io,
	.default_irq_priority = at91sam9260_default_irq_priority,
	.extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
		    | (1 << AT91SAM9260_ID_IRQ2),
	.ioremap_registers = at91sam9260_ioremap_registers,
	.register_clocks = at91sam9260_register_clocks,
	.init = at91sam9260_initialize,
AT91_SOC_END
Commit	Line	Data
62c1660d	1	/*
9d041268	2	* arch/arm/mach-at91/at91sam9260.c
62c1660d AV	3	*
	4	* Copyright (C) 2006 SAN People
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
2edb90ae	14	#include <linux/clk/at91_pmc.h>
62c1660d	15
c9dfafba	16	#include <asm/proc-fns.h>
80b02c17	17	#include <asm/irq.h>
62c1660d AV	18	#include <asm/mach/arch.h>
62c1660d AV	19	#include <asm/mach/map.h>
9f97da78	20	#include <asm/system_misc.h>
a09e64fb	21	#include <mach/cpu.h>
8c3583b6	22	#include <mach/at91_dbgu.h>
a09e64fb	23	#include <mach/at91sam9260.h>
ac11a1d4	24	#include <mach/hardware.h>
62c1660d	25
a510b9ba	26	#include "at91_aic.h"
f0995d08	27	#include "at91_rstc.h"
21d08b9d	28	#include "soc.h"
62c1660d	29	#include "generic.h"
faee0cc3	30	#include "sam9_smc.h"
5ad945ea	31	#include "pm.h"
62c1660d	32
57b37ed5 AB	33	#if defined(CONFIG_OLD_CLK_AT91)
57b37ed5 AB	34	#include "clock.h"
62c1660d AV	35	/* --------------------------------------------------------------------
	36	* Clocks
	37	* -------------------------------------------------------------------- */
	38
	39	/*
	40	* The peripheral clocks.
	41	*/
	42	static struct clk pioA_clk = {
	43	.name = "pioA_clk",
	44	.pmc_mask = 1 << AT91SAM9260_ID_PIOA,
	45	.type = CLK_TYPE_PERIPHERAL,
	46	};
	47	static struct clk pioB_clk = {
	48	.name = "pioB_clk",
	49	.pmc_mask = 1 << AT91SAM9260_ID_PIOB,
	50	.type = CLK_TYPE_PERIPHERAL,
	51	};
	52	static struct clk pioC_clk = {
	53	.name = "pioC_clk",
	54	.pmc_mask = 1 << AT91SAM9260_ID_PIOC,
	55	.type = CLK_TYPE_PERIPHERAL,
	56	};
	57	static struct clk adc_clk = {
	58	.name = "adc_clk",
	59	.pmc_mask = 1 << AT91SAM9260_ID_ADC,
	60	.type = CLK_TYPE_PERIPHERAL,
	61	};
67b5d7b3 MR	62
	63	static struct clk adc_op_clk = {
	64	.name = "adc_op_clk",
	65	.type = CLK_TYPE_PERIPHERAL,
	66	.rate_hz = 5000000,
	67	};
	68
62c1660d AV	69	static struct clk usart0_clk = {
	70	.name = "usart0_clk",
	71	.pmc_mask = 1 << AT91SAM9260_ID_US0,
	72	.type = CLK_TYPE_PERIPHERAL,
	73	};
	74	static struct clk usart1_clk = {
	75	.name = "usart1_clk",
	76	.pmc_mask = 1 << AT91SAM9260_ID_US1,
	77	.type = CLK_TYPE_PERIPHERAL,
	78	};
	79	static struct clk usart2_clk = {
	80	.name = "usart2_clk",
	81	.pmc_mask = 1 << AT91SAM9260_ID_US2,
	82	.type = CLK_TYPE_PERIPHERAL,
	83	};
	84	static struct clk mmc_clk = {
	85	.name = "mci_clk",
	86	.pmc_mask = 1 << AT91SAM9260_ID_MCI,
	87	.type = CLK_TYPE_PERIPHERAL,
	88	};
	89	static struct clk udc_clk = {
	90	.name = "udc_clk",
	91	.pmc_mask = 1 << AT91SAM9260_ID_UDP,
	92	.type = CLK_TYPE_PERIPHERAL,
	93	};
	94	static struct clk twi_clk = {
	95	.name = "twi_clk",
	96	.pmc_mask = 1 << AT91SAM9260_ID_TWI,
	97	.type = CLK_TYPE_PERIPHERAL,
	98	};
	99	static struct clk spi0_clk = {
	100	.name = "spi0_clk",
	101	.pmc_mask = 1 << AT91SAM9260_ID_SPI0,
	102	.type = CLK_TYPE_PERIPHERAL,
	103	};
	104	static struct clk spi1_clk = {
	105	.name = "spi1_clk",
	106	.pmc_mask = 1 << AT91SAM9260_ID_SPI1,
	107	.type = CLK_TYPE_PERIPHERAL,
	108	};
e8788bab AV	109	static struct clk ssc_clk = {
	110	.name = "ssc_clk",
	111	.pmc_mask = 1 << AT91SAM9260_ID_SSC,
	112	.type = CLK_TYPE_PERIPHERAL,
	113	};
c177a1e7 AV	114	static struct clk tc0_clk = {
	115	.name = "tc0_clk",
	116	.pmc_mask = 1 << AT91SAM9260_ID_TC0,
	117	.type = CLK_TYPE_PERIPHERAL,
	118	};
	119	static struct clk tc1_clk = {
	120	.name = "tc1_clk",
	121	.pmc_mask = 1 << AT91SAM9260_ID_TC1,
	122	.type = CLK_TYPE_PERIPHERAL,
	123	};
	124	static struct clk tc2_clk = {
	125	.name = "tc2_clk",
	126	.pmc_mask = 1 << AT91SAM9260_ID_TC2,
	127	.type = CLK_TYPE_PERIPHERAL,
	128	};
62c1660d AV	129	static struct clk ohci_clk = {
	130	.name = "ohci_clk",
	131	.pmc_mask = 1 << AT91SAM9260_ID_UHP,
	132	.type = CLK_TYPE_PERIPHERAL,
	133	};
69b2e99c	134	static struct clk macb_clk = {
865d605e	135	.name = "pclk",
62c1660d AV	136	.pmc_mask = 1 << AT91SAM9260_ID_EMAC,
	137	.type = CLK_TYPE_PERIPHERAL,
	138	};
	139	static struct clk isi_clk = {
	140	.name = "isi_clk",
	141	.pmc_mask = 1 << AT91SAM9260_ID_ISI,
	142	.type = CLK_TYPE_PERIPHERAL,
	143	};
	144	static struct clk usart3_clk = {
	145	.name = "usart3_clk",
	146	.pmc_mask = 1 << AT91SAM9260_ID_US3,
	147	.type = CLK_TYPE_PERIPHERAL,
	148	};
	149	static struct clk usart4_clk = {
	150	.name = "usart4_clk",
	151	.pmc_mask = 1 << AT91SAM9260_ID_US4,
	152	.type = CLK_TYPE_PERIPHERAL,
	153	};
	154	static struct clk usart5_clk = {
	155	.name = "usart5_clk",
	156	.pmc_mask = 1 << AT91SAM9260_ID_US5,
	157	.type = CLK_TYPE_PERIPHERAL,
	158	};
c177a1e7 AV	159	static struct clk tc3_clk = {
	160	.name = "tc3_clk",
	161	.pmc_mask = 1 << AT91SAM9260_ID_TC3,
	162	.type = CLK_TYPE_PERIPHERAL,
	163	};
	164	static struct clk tc4_clk = {
	165	.name = "tc4_clk",
	166	.pmc_mask = 1 << AT91SAM9260_ID_TC4,
	167	.type = CLK_TYPE_PERIPHERAL,
	168	};
	169	static struct clk tc5_clk = {
	170	.name = "tc5_clk",
	171	.pmc_mask = 1 << AT91SAM9260_ID_TC5,
	172	.type = CLK_TYPE_PERIPHERAL,
	173	};
62c1660d AV	174
	175	static struct clk *periph_clocks[] __initdata = {
	176	&pioA_clk,
	177	&pioB_clk,
	178	&pioC_clk,
	179	&adc_clk,
67b5d7b3	180	&adc_op_clk,
62c1660d AV	181	&usart0_clk,
	182	&usart1_clk,
	183	&usart2_clk,
	184	&mmc_clk,
	185	&udc_clk,
	186	&twi_clk,
	187	&spi0_clk,
	188	&spi1_clk,
e8788bab	189	&ssc_clk,
c177a1e7 AV	190	&tc0_clk,
	191	&tc1_clk,
	192	&tc2_clk,
62c1660d	193	&ohci_clk,
69b2e99c	194	&macb_clk,
62c1660d AV	195	&isi_clk,
	196	&usart3_clk,
	197	&usart4_clk,
	198	&usart5_clk,
c177a1e7 AV	199	&tc3_clk,
	200	&tc4_clk,
	201	&tc5_clk,
62c1660d AV	202	// irq0 .. irq2
	203	};
	204
bd602995	205	static struct clk_lookup periph_clocks_lookups[] = {
865d605e JI	206	/* One additional fake clock for macb_hclk */
865d605e JI	207	CLKDEV_CON_ID("hclk", &macb_clk),
bd602995 JCPV	208	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	209	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	210	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	211	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	212	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
1808958d JCPV	213	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
	214	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
	215	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
636036d2	216	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
099343c6	217	CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
302090a6 BS	218	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
302090a6 BS	219	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
fea3158c JCPV	220	/* more usart lookup table for DT entries */
	221	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	222	CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
	223	CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
	224	CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
	225	CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
	226	CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
	227	CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
f7d19b90	228	CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
3a61a5da NF	229	/* more tc lookup table for DT entries */
	230	CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
	231	CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
	232	CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
	233	CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
	234	CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
	235	CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
6a062459	236	CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
23e3b24f	237	CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
f0db66a5 RG	238	CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
f0db66a5 RG	239	CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
0af4316b JCPV	240	/* fake hclk clock */
0af4316b JCPV	241	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
619d4a4b JCPV	242	CLKDEV_CON_ID("pioA", &pioA_clk),
	243	CLKDEV_CON_ID("pioB", &pioB_clk),
	244	CLKDEV_CON_ID("pioC", &pioC_clk),
5314ec8e JCPV	245	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
	246	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
	247	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
bd602995 JCPV	248	};
	249
	250	static struct clk_lookup usart_clocks_lookups[] = {
	251	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	252	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	253	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	254	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	255	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
	256	CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
	257	CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
	258	};
	259
62c1660d AV	260	/*
	261	* The two programmable clocks.
	262	* You must configure pin multiplexing to bring these signals out.
	263	*/
	264	static struct clk pck0 = {
	265	.name = "pck0",
	266	.pmc_mask = AT91_PMC_PCK0,
	267	.type = CLK_TYPE_PROGRAMMABLE,
	268	.id = 0,
	269	};
	270	static struct clk pck1 = {
	271	.name = "pck1",
	272	.pmc_mask = AT91_PMC_PCK1,
	273	.type = CLK_TYPE_PROGRAMMABLE,
	274	.id = 1,
	275	};
	276
	277	static void __init at91sam9260_register_clocks(void)
	278	{
	279	int i;
	280
	281	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	282	clk_register(periph_clocks[i]);
	283
bd602995 JCPV	284	clkdev_add_table(periph_clocks_lookups,
	285	ARRAY_SIZE(periph_clocks_lookups));
	286	clkdev_add_table(usart_clocks_lookups,
	287	ARRAY_SIZE(usart_clocks_lookups));
	288
62c1660d AV	289	clk_register(&pck0);
	290	clk_register(&pck1);
	291	}
57b37ed5 AB	292	#else
	293	#define at91sam9260_register_clocks NULL
	294	#endif
62c1660d AV	295
	296	/* --------------------------------------------------------------------
	297	* GPIO
	298	* -------------------------------------------------------------------- */
	299
1a2d9156	300	static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
62c1660d AV	301	{
62c1660d AV	302	.id = AT91SAM9260_ID_PIOA,
80e91cb8	303	.regbase = AT91SAM9260_BASE_PIOA,
62c1660d AV	304	}, {
62c1660d AV	305	.id = AT91SAM9260_ID_PIOB,
80e91cb8	306	.regbase = AT91SAM9260_BASE_PIOB,
62c1660d AV	307	}, {
62c1660d AV	308	.id = AT91SAM9260_ID_PIOC,
80e91cb8	309	.regbase = AT91SAM9260_BASE_PIOC,
62c1660d AV	310	}
	311	};
	312
62c1660d AV	313	/* --------------------------------------------------------------------
	314	* AT91SAM9260 processor initialization
	315	* -------------------------------------------------------------------- */
	316
1b021a3b	317	static void __init at91sam9xe_map_io(void)
f7eee89b	318	{
8c3583b6	319	unsigned long sram_size;
f7eee89b	320
8c3583b6	321	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
f7eee89b AV	322	case AT91_CIDR_SRAMSIZ_32K:
	323	sram_size = 2 * SZ_16K;
	324	break;
	325	case AT91_CIDR_SRAMSIZ_16K:
	326	default:
	327	sram_size = SZ_16K;
	328	}
	329
f0051d82	330	at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
f7eee89b AV	331	}
f7eee89b AV	332
21d08b9d	333	static void __init at91sam9260_map_io(void)
62c1660d	334	{
c9b1e3ff	335	if (cpu_is_at91sam9xe())
1b021a3b	336	at91sam9xe_map_io();
c9b1e3ff JCPV	337	else if (cpu_is_at91sam9g20())
	338	at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
	339	else
	340	at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
1b021a3b	341	}
f7eee89b	342
cfa5a1fe JCPV	343	static void __init at91sam9260_ioremap_registers(void)
cfa5a1fe JCPV	344	{
f22deee5	345	at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
e9f68b5c	346	at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
f363c407	347	at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
4ab0c599	348	at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
faee0cc3	349	at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
4342d647	350	at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
6b625891	351	at91_pm_set_standby(at91sam9_sdram_standby);
cfa5a1fe JCPV	352	}
cfa5a1fe JCPV	353
46539374	354	static void __init at91sam9260_initialize(void)
1b021a3b	355	{
0d781716	356	arm_pm_idle = at91sam9_idle;
1b2073e7	357	arm_pm_restart = at91sam9_alt_restart;
62c1660d	358
94c4c79f JH	359	at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
94c4c79f JH	360
62c1660d AV	361	/* Register GPIO subsystem */
	362	at91_gpio_init(at91sam9260_gpio, 3);
	363	}
	364
	365	/* --------------------------------------------------------------------
	366	* Interrupt initialization
	367	* -------------------------------------------------------------------- */
	368
	369	/*
	370	* The default interrupt priority levels (0 = lowest, 7 = highest).
	371	*/
	372	static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
	373	7, /* Advanced Interrupt Controller */
	374	7, /* System Peripherals */
7cbed2b5 AV	375	1, /* Parallel IO Controller A */
	376	1, /* Parallel IO Controller B */
	377	1, /* Parallel IO Controller C */
62c1660d	378	0, /* Analog-to-Digital Converter */
7cbed2b5 AV	379	5, /* USART 0 */
	380	5, /* USART 1 */
	381	5, /* USART 2 */
62c1660d	382	0, /* Multimedia Card Interface */
7cbed2b5 AV	383	2, /* USB Device Port */
	384	6, /* Two-Wire Interface */
	385	5, /* Serial Peripheral Interface 0 */
	386	5, /* Serial Peripheral Interface 1 */
62c1660d AV	387	5, /* Serial Synchronous Controller */
	388	0,
	389	0,
	390	0, /* Timer Counter 0 */
	391	0, /* Timer Counter 1 */
	392	0, /* Timer Counter 2 */
7cbed2b5	393	2, /* USB Host port */
62c1660d AV	394	3, /* Ethernet */
62c1660d AV	395	0, /* Image Sensor Interface */
7cbed2b5 AV	396	5, /* USART 3 */
	397	5, /* USART 4 */
	398	5, /* USART 5 */
62c1660d AV	399	0, /* Timer Counter 3 */
	400	0, /* Timer Counter 4 */
	401	0, /* Timer Counter 5 */
	402	0, /* Advanced Interrupt Controller */
	403	0, /* Advanced Interrupt Controller */
	404	0, /* Advanced Interrupt Controller */
	405	};
	406
84ddb087	407	AT91_SOC_START(at91sam9260)
21d08b9d	408	.map_io = at91sam9260_map_io,
92100c12	409	.default_irq_priority = at91sam9260_default_irq_priority,
546c830c JCPV	410	.extern_irq = (1 << AT91SAM9260_ID_IRQ0) \| (1 << AT91SAM9260_ID_IRQ1)
546c830c JCPV	411	\| (1 << AT91SAM9260_ID_IRQ2),
cfa5a1fe	412	.ioremap_registers = at91sam9260_ioremap_registers,
51ddec76	413	.register_clocks = at91sam9260_register_clocks,
21d08b9d	414	.init = at91sam9260_initialize,
8d39e0fd	415	AT91_SOC_END