[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9261.c

/*
 * arch/arm/mach-at91/at91sam9261.c
 *
 *  Copyright (C) 2005 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>
#include <linux/pm.h>

#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/cpu.h>
#include <mach/at91sam9261.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>

#include "soc.h"
#include "generic.h"
#include "clock.h"

static struct map_desc at91sam9261_sram_desc[] __initdata = {
	{
		.virtual	= AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
		.pfn		= __phys_to_pfn(AT91SAM9261_SRAM_BASE),
		.length		= AT91SAM9261_SRAM_SIZE,
		.type		= MT_DEVICE,
	},
};

static struct map_desc at91sam9g10_sram_desc[] __initdata = {
	{
		.virtual	= AT91_IO_VIRT_BASE - AT91SAM9G10_SRAM_SIZE,
		.pfn		= __phys_to_pfn(AT91SAM9G10_SRAM_BASE),
		.length		= AT91SAM9G10_SRAM_SIZE,
		.type		= MT_DEVICE,
	},
};

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
	.name		= "mci_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_MCI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
	.name		= "udc_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_UDP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
	.name		= "twi_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_TWI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc2_clk = {
	.name		= "ssc2_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SSC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
	.name		= "tc0_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_TC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
	.name		= "tc1_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_TC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
	.name		= "tc2_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_TC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
	.name		= "ohci_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_UHP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&mmc_clk,
	&udc_clk,
	&twi_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc0_clk,
	&ssc1_clk,
	&ssc2_clk,
	&tc0_clk,
	&tc1_clk,
	&tc2_clk,
	&ohci_clk,
	&lcdc_clk,
	// irq0 .. irq2
};

static struct clk_lookup periph_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc1_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
};

/*
 * The four programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};
static struct clk pck2 = {
	.name		= "pck2",
	.pmc_mask	= AT91_PMC_PCK2,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 2,
};
static struct clk pck3 = {
	.name		= "pck3",
	.pmc_mask	= AT91_PMC_PCK3,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 3,
};

/* HClocks */
static struct clk hck0 = {
	.name		= "hck0",
	.pmc_mask	= AT91_PMC_HCK0,
	.type		= CLK_TYPE_SYSTEM,
	.id		= 0,
};
static struct clk hck1 = {
	.name		= "hck1",
	.pmc_mask	= AT91_PMC_HCK1,
	.type		= CLK_TYPE_SYSTEM,
	.id		= 1,
};

static void __init at91sam9261_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
	clk_register(&pck2);
	clk_register(&pck3);

	clk_register(&hck0);
	clk_register(&hck1);
}

static struct clk_lookup console_clock_lookup;

void __init at91sam9261_set_console_clock(int id)
{
	if (id >= ARRAY_SIZE(usart_clocks_lookups))
		return;

	console_clock_lookup.con_id = "usart";
	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	clkdev_add(&console_clock_lookup);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9261_gpio[] = {
	{
		.id		= AT91SAM9261_ID_PIOA,
		.offset		= AT91_PIOA,
		.clock		= &pioA_clk,
	}, {
		.id		= AT91SAM9261_ID_PIOB,
		.offset		= AT91_PIOB,
		.clock		= &pioB_clk,
	}, {
		.id		= AT91SAM9261_ID_PIOC,
		.offset		= AT91_PIOC,
		.clock		= &pioC_clk,
	}
};

static void at91sam9261_poweroff(void)
{
	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}


/* --------------------------------------------------------------------
 *  AT91SAM9261 processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9261_map_io(void)
{
	if (cpu_is_at91sam9g10())
		iotable_init(at91sam9g10_sram_desc, ARRAY_SIZE(at91sam9g10_sram_desc));
	else
		iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc));
}

static void __init at91sam9261_initialize(void)
{
	at91_arch_reset = at91sam9_alt_reset;
	pm_power_off = at91sam9261_poweroff;
	at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
			| (1 << AT91SAM9261_ID_IRQ2);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9261_gpio, 3);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	0,
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	0,	/* Multimedia Card Interface */
	2,	/* USB Device Port */
	6,	/* Two-Wire Interface */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	4,	/* Serial Synchronous Controller 2 */
	0,	/* Timer Counter 0 */
	0,	/* Timer Counter 1 */
	0,	/* Timer Counter 2 */
	2,	/* USB Host port */
	3,	/* LCD Controller */
	0,
	0,
	0,
	0,
	0,
	0,
	0,
	0,	/* Advanced Interrupt Controller */
	0,	/* Advanced Interrupt Controller */
	0,	/* Advanced Interrupt Controller */
};

struct at91_init_soc __initdata at91sam9261_soc = {
	.map_io = at91sam9261_map_io,
	.default_irq_priority = at91sam9261_default_irq_priority,
	.register_clocks = at91sam9261_register_clocks,
	.init = at91sam9261_initialize,
};
Commit	Line	Data
62c1660d	1	/*
9d041268	2	* arch/arm/mach-at91/at91sam9261.c
62c1660d AV	3	*
	4	* Copyright (C) 2005 SAN People
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
3ef2fb42	14	#include <linux/pm.h>
62c1660d	15
80b02c17	16	#include <asm/irq.h>
62c1660d AV	17	#include <asm/mach/arch.h>
62c1660d AV	18	#include <asm/mach/map.h>
b319ff80	19	#include <mach/cpu.h>
a09e64fb RK	20	#include <mach/at91sam9261.h>
	21	#include <mach/at91_pmc.h>
	22	#include <mach/at91_rstc.h>
	23	#include <mach/at91_shdwc.h>
62c1660d	24
21d08b9d	25	#include "soc.h"
62c1660d AV	26	#include "generic.h"
	27	#include "clock.h"
	28
b319ff80 NF	29	static struct map_desc at91sam9261_sram_desc[] __initdata = {
b319ff80 NF	30	{
62c1660d AV	31	.virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
	32	.pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
	33	.length = AT91SAM9261_SRAM_SIZE,
	34	.type = MT_DEVICE,
	35	},
	36	};
	37
b319ff80 NF	38	static struct map_desc at91sam9g10_sram_desc[] __initdata = {
	39	{
	40	.virtual = AT91_IO_VIRT_BASE - AT91SAM9G10_SRAM_SIZE,
	41	.pfn = __phys_to_pfn(AT91SAM9G10_SRAM_BASE),
	42	.length = AT91SAM9G10_SRAM_SIZE,
	43	.type = MT_DEVICE,
	44	},
	45	};
	46
62c1660d AV	47	/* --------------------------------------------------------------------
	48	* Clocks
	49	* -------------------------------------------------------------------- */
	50
	51	/*
	52	* The peripheral clocks.
	53	*/
	54	static struct clk pioA_clk = {
	55	.name = "pioA_clk",
	56	.pmc_mask = 1 << AT91SAM9261_ID_PIOA,
	57	.type = CLK_TYPE_PERIPHERAL,
	58	};
	59	static struct clk pioB_clk = {
	60	.name = "pioB_clk",
	61	.pmc_mask = 1 << AT91SAM9261_ID_PIOB,
	62	.type = CLK_TYPE_PERIPHERAL,
	63	};
	64	static struct clk pioC_clk = {
	65	.name = "pioC_clk",
	66	.pmc_mask = 1 << AT91SAM9261_ID_PIOC,
	67	.type = CLK_TYPE_PERIPHERAL,
	68	};
	69	static struct clk usart0_clk = {
	70	.name = "usart0_clk",
	71	.pmc_mask = 1 << AT91SAM9261_ID_US0,
	72	.type = CLK_TYPE_PERIPHERAL,
	73	};
	74	static struct clk usart1_clk = {
	75	.name = "usart1_clk",
	76	.pmc_mask = 1 << AT91SAM9261_ID_US1,
	77	.type = CLK_TYPE_PERIPHERAL,
	78	};
	79	static struct clk usart2_clk = {
	80	.name = "usart2_clk",
	81	.pmc_mask = 1 << AT91SAM9261_ID_US2,
	82	.type = CLK_TYPE_PERIPHERAL,
	83	};
	84	static struct clk mmc_clk = {
	85	.name = "mci_clk",
	86	.pmc_mask = 1 << AT91SAM9261_ID_MCI,
	87	.type = CLK_TYPE_PERIPHERAL,
	88	};
	89	static struct clk udc_clk = {
	90	.name = "udc_clk",
	91	.pmc_mask = 1 << AT91SAM9261_ID_UDP,
	92	.type = CLK_TYPE_PERIPHERAL,
	93	};
	94	static struct clk twi_clk = {
	95	.name = "twi_clk",
	96	.pmc_mask = 1 << AT91SAM9261_ID_TWI,
	97	.type = CLK_TYPE_PERIPHERAL,
	98	};
	99	static struct clk spi0_clk = {
	100	.name = "spi0_clk",
	101	.pmc_mask = 1 << AT91SAM9261_ID_SPI0,
	102	.type = CLK_TYPE_PERIPHERAL,
	103	};
	104	static struct clk spi1_clk = {
	105	.name = "spi1_clk",
	106	.pmc_mask = 1 << AT91SAM9261_ID_SPI1,
	107	.type = CLK_TYPE_PERIPHERAL,
	108	};
e8788bab AV	109	static struct clk ssc0_clk = {
	110	.name = "ssc0_clk",
	111	.pmc_mask = 1 << AT91SAM9261_ID_SSC0,
	112	.type = CLK_TYPE_PERIPHERAL,
	113	};
	114	static struct clk ssc1_clk = {
	115	.name = "ssc1_clk",
	116	.pmc_mask = 1 << AT91SAM9261_ID_SSC1,
	117	.type = CLK_TYPE_PERIPHERAL,
	118	};
	119	static struct clk ssc2_clk = {
	120	.name = "ssc2_clk",
	121	.pmc_mask = 1 << AT91SAM9261_ID_SSC2,
	122	.type = CLK_TYPE_PERIPHERAL,
	123	};
c177a1e7 AV	124	static struct clk tc0_clk = {
	125	.name = "tc0_clk",
	126	.pmc_mask = 1 << AT91SAM9261_ID_TC0,
	127	.type = CLK_TYPE_PERIPHERAL,
	128	};
	129	static struct clk tc1_clk = {
	130	.name = "tc1_clk",
	131	.pmc_mask = 1 << AT91SAM9261_ID_TC1,
	132	.type = CLK_TYPE_PERIPHERAL,
	133	};
	134	static struct clk tc2_clk = {
	135	.name = "tc2_clk",
	136	.pmc_mask = 1 << AT91SAM9261_ID_TC2,
	137	.type = CLK_TYPE_PERIPHERAL,
	138	};
62c1660d AV	139	static struct clk ohci_clk = {
	140	.name = "ohci_clk",
	141	.pmc_mask = 1 << AT91SAM9261_ID_UHP,
	142	.type = CLK_TYPE_PERIPHERAL,
	143	};
	144	static struct clk lcdc_clk = {
	145	.name = "lcdc_clk",
	146	.pmc_mask = 1 << AT91SAM9261_ID_LCDC,
	147	.type = CLK_TYPE_PERIPHERAL,
	148	};
	149
	150	static struct clk *periph_clocks[] __initdata = {
	151	&pioA_clk,
	152	&pioB_clk,
	153	&pioC_clk,
	154	&usart0_clk,
	155	&usart1_clk,
	156	&usart2_clk,
	157	&mmc_clk,
	158	&udc_clk,
	159	&twi_clk,
	160	&spi0_clk,
	161	&spi1_clk,
e8788bab AV	162	&ssc0_clk,
	163	&ssc1_clk,
	164	&ssc2_clk,
c177a1e7 AV	165	&tc0_clk,
	166	&tc1_clk,
	167	&tc2_clk,
62c1660d AV	168	&ohci_clk,
	169	&lcdc_clk,
	170	// irq0 .. irq2
	171	};
	172
bd602995 JCPV	173	static struct clk_lookup periph_clocks_lookups[] = {
	174	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	175	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	176	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	177	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	178	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc1_clk),
	179	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	180	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
	181	CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
	182	};
	183
	184	static struct clk_lookup usart_clocks_lookups[] = {
	185	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	186	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	187	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	188	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	189	};
	190
62c1660d AV	191	/*
	192	* The four programmable clocks.
	193	* You must configure pin multiplexing to bring these signals out.
	194	*/
	195	static struct clk pck0 = {
	196	.name = "pck0",
	197	.pmc_mask = AT91_PMC_PCK0,
	198	.type = CLK_TYPE_PROGRAMMABLE,
	199	.id = 0,
	200	};
	201	static struct clk pck1 = {
	202	.name = "pck1",
	203	.pmc_mask = AT91_PMC_PCK1,
	204	.type = CLK_TYPE_PROGRAMMABLE,
	205	.id = 1,
	206	};
	207	static struct clk pck2 = {
	208	.name = "pck2",
	209	.pmc_mask = AT91_PMC_PCK2,
	210	.type = CLK_TYPE_PROGRAMMABLE,
	211	.id = 2,
	212	};
	213	static struct clk pck3 = {
	214	.name = "pck3",
	215	.pmc_mask = AT91_PMC_PCK3,
	216	.type = CLK_TYPE_PROGRAMMABLE,
	217	.id = 3,
	218	};
	219
	220	/* HClocks */
	221	static struct clk hck0 = {
	222	.name = "hck0",
	223	.pmc_mask = AT91_PMC_HCK0,
	224	.type = CLK_TYPE_SYSTEM,
	225	.id = 0,
	226	};
	227	static struct clk hck1 = {
	228	.name = "hck1",
	229	.pmc_mask = AT91_PMC_HCK1,
	230	.type = CLK_TYPE_SYSTEM,
	231	.id = 1,
	232	};
	233
	234	static void __init at91sam9261_register_clocks(void)
	235	{
	236	int i;
	237
	238	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	239	clk_register(periph_clocks[i]);
	240
bd602995 JCPV	241	clkdev_add_table(periph_clocks_lookups,
	242	ARRAY_SIZE(periph_clocks_lookups));
	243	clkdev_add_table(usart_clocks_lookups,
	244	ARRAY_SIZE(usart_clocks_lookups));
	245
62c1660d AV	246	clk_register(&pck0);
	247	clk_register(&pck1);
	248	clk_register(&pck2);
	249	clk_register(&pck3);
	250
	251	clk_register(&hck0);
	252	clk_register(&hck1);
	253	}
	254
bd602995 JCPV	255	static struct clk_lookup console_clock_lookup;
	256
	257	void __init at91sam9261_set_console_clock(int id)
	258	{
	259	if (id >= ARRAY_SIZE(usart_clocks_lookups))
	260	return;
	261
	262	console_clock_lookup.con_id = "usart";
	263	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	264	clkdev_add(&console_clock_lookup);
	265	}
	266
62c1660d AV	267	/* --------------------------------------------------------------------
	268	* GPIO
	269	* -------------------------------------------------------------------- */
	270
	271	static struct at91_gpio_bank at91sam9261_gpio[] = {
	272	{
	273	.id = AT91SAM9261_ID_PIOA,
	274	.offset = AT91_PIOA,
	275	.clock = &pioA_clk,
	276	}, {
	277	.id = AT91SAM9261_ID_PIOB,
	278	.offset = AT91_PIOB,
	279	.clock = &pioB_clk,
	280	}, {
	281	.id = AT91SAM9261_ID_PIOC,
	282	.offset = AT91_PIOC,
	283	.clock = &pioC_clk,
	284	}
	285	};
	286
3ef2fb42 AV	287	static void at91sam9261_poweroff(void)
	288	{
	289	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY \| AT91_SHDW_SHDW);
	290	}
	291
62c1660d AV	292
	293	/* --------------------------------------------------------------------
	294	* AT91SAM9261 processor initialization
	295	* -------------------------------------------------------------------- */
	296
21d08b9d	297	static void __init at91sam9261_map_io(void)
62c1660d	298	{
b319ff80 NF	299	if (cpu_is_at91sam9g10())
	300	iotable_init(at91sam9g10_sram_desc, ARRAY_SIZE(at91sam9g10_sram_desc));
	301	else
	302	iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc));
1b021a3b	303	}
b319ff80	304
46539374	305	static void __init at91sam9261_initialize(void)
1b021a3b	306	{
bb413db5	307	at91_arch_reset = at91sam9_alt_reset;
3ef2fb42	308	pm_power_off = at91sam9261_poweroff;
62c1660d AV	309	at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) \| (1 << AT91SAM9261_ID_IRQ1)
	310	\| (1 << AT91SAM9261_ID_IRQ2);
	311
62c1660d AV	312	/* Register GPIO subsystem */
	313	at91_gpio_init(at91sam9261_gpio, 3);
	314	}
	315
	316	/* --------------------------------------------------------------------
	317	* Interrupt initialization
	318	* -------------------------------------------------------------------- */
	319
	320	/*
	321	* The default interrupt priority levels (0 = lowest, 7 = highest).
	322	*/
	323	static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
	324	7, /* Advanced Interrupt Controller */
	325	7, /* System Peripherals */
7cbed2b5 AV	326	1, /* Parallel IO Controller A */
	327	1, /* Parallel IO Controller B */
	328	1, /* Parallel IO Controller C */
62c1660d	329	0,
7cbed2b5 AV	330	5, /* USART 0 */
	331	5, /* USART 1 */
	332	5, /* USART 2 */
62c1660d	333	0, /* Multimedia Card Interface */
7cbed2b5 AV	334	2, /* USB Device Port */
	335	6, /* Two-Wire Interface */
	336	5, /* Serial Peripheral Interface 0 */
	337	5, /* Serial Peripheral Interface 1 */
	338	4, /* Serial Synchronous Controller 0 */
	339	4, /* Serial Synchronous Controller 1 */
	340	4, /* Serial Synchronous Controller 2 */
62c1660d AV	341	0, /* Timer Counter 0 */
	342	0, /* Timer Counter 1 */
	343	0, /* Timer Counter 2 */
7cbed2b5	344	2, /* USB Host port */
62c1660d AV	345	3, /* LCD Controller */
	346	0,
	347	0,
	348	0,
	349	0,
	350	0,
	351	0,
	352	0,
	353	0, /* Advanced Interrupt Controller */
	354	0, /* Advanced Interrupt Controller */
	355	0, /* Advanced Interrupt Controller */
	356	};
	357
8c3583b6	358	struct at91_init_soc __initdata at91sam9261_soc = {
21d08b9d	359	.map_io = at91sam9261_map_io,
92100c12	360	.default_irq_priority = at91sam9261_default_irq_priority,
51ddec76	361	.register_clocks = at91sam9261_register_clocks,
21d08b9d JCPV	362	.init = at91sam9261_initialize,
21d08b9d JCPV	363	};