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789b23bc NF |
1 | /* |
2 | * Chip-specific setup code for the AT91SAM9G45 family | |
3 | * | |
4 | * Copyright (C) 2009 Atmel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/pm.h> | |
15 | ||
16 | #include <asm/irq.h> | |
17 | #include <asm/mach/arch.h> | |
18 | #include <asm/mach/map.h> | |
19 | #include <mach/at91sam9g45.h> | |
20 | #include <mach/at91_pmc.h> | |
21 | #include <mach/at91_rstc.h> | |
22 | #include <mach/at91_shdwc.h> | |
5f9f0a41 | 23 | #include <mach/cpu.h> |
789b23bc | 24 | |
21d08b9d | 25 | #include "soc.h" |
789b23bc NF |
26 | #include "generic.h" |
27 | #include "clock.h" | |
28 | ||
21d08b9d | 29 | static struct map_desc at91sam9g45_sram_desc[] __initdata = { |
789b23bc | 30 | { |
789b23bc NF |
31 | .virtual = AT91_IO_VIRT_BASE - AT91SAM9G45_SRAM_SIZE, |
32 | .pfn = __phys_to_pfn(AT91SAM9G45_SRAM_BASE), | |
33 | .length = AT91SAM9G45_SRAM_SIZE, | |
34 | .type = MT_DEVICE, | |
35 | } | |
36 | }; | |
37 | ||
38 | /* -------------------------------------------------------------------- | |
39 | * Clocks | |
40 | * -------------------------------------------------------------------- */ | |
41 | ||
42 | /* | |
43 | * The peripheral clocks. | |
44 | */ | |
45 | static struct clk pioA_clk = { | |
46 | .name = "pioA_clk", | |
47 | .pmc_mask = 1 << AT91SAM9G45_ID_PIOA, | |
48 | .type = CLK_TYPE_PERIPHERAL, | |
49 | }; | |
50 | static struct clk pioB_clk = { | |
51 | .name = "pioB_clk", | |
52 | .pmc_mask = 1 << AT91SAM9G45_ID_PIOB, | |
53 | .type = CLK_TYPE_PERIPHERAL, | |
54 | }; | |
55 | static struct clk pioC_clk = { | |
56 | .name = "pioC_clk", | |
57 | .pmc_mask = 1 << AT91SAM9G45_ID_PIOC, | |
58 | .type = CLK_TYPE_PERIPHERAL, | |
59 | }; | |
60 | static struct clk pioDE_clk = { | |
61 | .name = "pioDE_clk", | |
62 | .pmc_mask = 1 << AT91SAM9G45_ID_PIODE, | |
63 | .type = CLK_TYPE_PERIPHERAL, | |
64 | }; | |
65 | static struct clk usart0_clk = { | |
66 | .name = "usart0_clk", | |
67 | .pmc_mask = 1 << AT91SAM9G45_ID_US0, | |
68 | .type = CLK_TYPE_PERIPHERAL, | |
69 | }; | |
70 | static struct clk usart1_clk = { | |
71 | .name = "usart1_clk", | |
72 | .pmc_mask = 1 << AT91SAM9G45_ID_US1, | |
73 | .type = CLK_TYPE_PERIPHERAL, | |
74 | }; | |
75 | static struct clk usart2_clk = { | |
76 | .name = "usart2_clk", | |
77 | .pmc_mask = 1 << AT91SAM9G45_ID_US2, | |
78 | .type = CLK_TYPE_PERIPHERAL, | |
79 | }; | |
80 | static struct clk usart3_clk = { | |
81 | .name = "usart3_clk", | |
82 | .pmc_mask = 1 << AT91SAM9G45_ID_US3, | |
83 | .type = CLK_TYPE_PERIPHERAL, | |
84 | }; | |
85 | static struct clk mmc0_clk = { | |
86 | .name = "mci0_clk", | |
87 | .pmc_mask = 1 << AT91SAM9G45_ID_MCI0, | |
88 | .type = CLK_TYPE_PERIPHERAL, | |
89 | }; | |
90 | static struct clk twi0_clk = { | |
91 | .name = "twi0_clk", | |
92 | .pmc_mask = 1 << AT91SAM9G45_ID_TWI0, | |
93 | .type = CLK_TYPE_PERIPHERAL, | |
94 | }; | |
95 | static struct clk twi1_clk = { | |
96 | .name = "twi1_clk", | |
97 | .pmc_mask = 1 << AT91SAM9G45_ID_TWI1, | |
98 | .type = CLK_TYPE_PERIPHERAL, | |
99 | }; | |
100 | static struct clk spi0_clk = { | |
101 | .name = "spi0_clk", | |
102 | .pmc_mask = 1 << AT91SAM9G45_ID_SPI0, | |
103 | .type = CLK_TYPE_PERIPHERAL, | |
104 | }; | |
105 | static struct clk spi1_clk = { | |
106 | .name = "spi1_clk", | |
107 | .pmc_mask = 1 << AT91SAM9G45_ID_SPI1, | |
108 | .type = CLK_TYPE_PERIPHERAL, | |
109 | }; | |
110 | static struct clk ssc0_clk = { | |
111 | .name = "ssc0_clk", | |
112 | .pmc_mask = 1 << AT91SAM9G45_ID_SSC0, | |
113 | .type = CLK_TYPE_PERIPHERAL, | |
114 | }; | |
115 | static struct clk ssc1_clk = { | |
116 | .name = "ssc1_clk", | |
117 | .pmc_mask = 1 << AT91SAM9G45_ID_SSC1, | |
118 | .type = CLK_TYPE_PERIPHERAL, | |
119 | }; | |
ab64511c FG |
120 | static struct clk tcb0_clk = { |
121 | .name = "tcb0_clk", | |
789b23bc NF |
122 | .pmc_mask = 1 << AT91SAM9G45_ID_TCB, |
123 | .type = CLK_TYPE_PERIPHERAL, | |
124 | }; | |
125 | static struct clk pwm_clk = { | |
126 | .name = "pwm_clk", | |
127 | .pmc_mask = 1 << AT91SAM9G45_ID_PWMC, | |
128 | .type = CLK_TYPE_PERIPHERAL, | |
129 | }; | |
130 | static struct clk tsc_clk = { | |
131 | .name = "tsc_clk", | |
132 | .pmc_mask = 1 << AT91SAM9G45_ID_TSC, | |
133 | .type = CLK_TYPE_PERIPHERAL, | |
134 | }; | |
135 | static struct clk dma_clk = { | |
136 | .name = "dma_clk", | |
137 | .pmc_mask = 1 << AT91SAM9G45_ID_DMA, | |
138 | .type = CLK_TYPE_PERIPHERAL, | |
139 | }; | |
140 | static struct clk uhphs_clk = { | |
141 | .name = "uhphs_clk", | |
142 | .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS, | |
143 | .type = CLK_TYPE_PERIPHERAL, | |
144 | }; | |
145 | static struct clk lcdc_clk = { | |
146 | .name = "lcdc_clk", | |
147 | .pmc_mask = 1 << AT91SAM9G45_ID_LCDC, | |
148 | .type = CLK_TYPE_PERIPHERAL, | |
149 | }; | |
150 | static struct clk ac97_clk = { | |
151 | .name = "ac97_clk", | |
152 | .pmc_mask = 1 << AT91SAM9G45_ID_AC97C, | |
153 | .type = CLK_TYPE_PERIPHERAL, | |
154 | }; | |
155 | static struct clk macb_clk = { | |
156 | .name = "macb_clk", | |
157 | .pmc_mask = 1 << AT91SAM9G45_ID_EMAC, | |
158 | .type = CLK_TYPE_PERIPHERAL, | |
159 | }; | |
160 | static struct clk isi_clk = { | |
161 | .name = "isi_clk", | |
162 | .pmc_mask = 1 << AT91SAM9G45_ID_ISI, | |
163 | .type = CLK_TYPE_PERIPHERAL, | |
164 | }; | |
165 | static struct clk udphs_clk = { | |
166 | .name = "udphs_clk", | |
167 | .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS, | |
168 | .type = CLK_TYPE_PERIPHERAL, | |
169 | }; | |
170 | static struct clk mmc1_clk = { | |
171 | .name = "mci1_clk", | |
172 | .pmc_mask = 1 << AT91SAM9G45_ID_MCI1, | |
173 | .type = CLK_TYPE_PERIPHERAL, | |
174 | }; | |
175 | ||
5f9f0a41 NF |
176 | /* Video decoder clock - Only for sam9m10/sam9m11 */ |
177 | static struct clk vdec_clk = { | |
178 | .name = "vdec_clk", | |
179 | .pmc_mask = 1 << AT91SAM9G45_ID_VDEC, | |
180 | .type = CLK_TYPE_PERIPHERAL, | |
181 | }; | |
182 | ||
789b23bc NF |
183 | static struct clk *periph_clocks[] __initdata = { |
184 | &pioA_clk, | |
185 | &pioB_clk, | |
186 | &pioC_clk, | |
187 | &pioDE_clk, | |
188 | &usart0_clk, | |
189 | &usart1_clk, | |
190 | &usart2_clk, | |
191 | &usart3_clk, | |
192 | &mmc0_clk, | |
193 | &twi0_clk, | |
194 | &twi1_clk, | |
195 | &spi0_clk, | |
196 | &spi1_clk, | |
197 | &ssc0_clk, | |
198 | &ssc1_clk, | |
ab64511c | 199 | &tcb0_clk, |
789b23bc NF |
200 | &pwm_clk, |
201 | &tsc_clk, | |
202 | &dma_clk, | |
203 | &uhphs_clk, | |
204 | &lcdc_clk, | |
205 | &ac97_clk, | |
206 | &macb_clk, | |
207 | &isi_clk, | |
208 | &udphs_clk, | |
209 | &mmc1_clk, | |
210 | // irq0 | |
bd602995 JCPV |
211 | }; |
212 | ||
213 | static struct clk_lookup periph_clocks_lookups[] = { | |
214 | /* One additional fake clock for ohci */ | |
215 | CLKDEV_CON_ID("ohci_clk", &uhphs_clk), | |
9d87159e JCPV |
216 | CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk), |
217 | CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), | |
218 | CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), | |
219 | CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk), | |
220 | CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk), | |
bd602995 JCPV |
221 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), |
222 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), | |
223 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk), | |
224 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), | |
225 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), | |
226 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), | |
227 | }; | |
228 | ||
229 | static struct clk_lookup usart_clocks_lookups[] = { | |
230 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), | |
231 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), | |
232 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), | |
233 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), | |
234 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk), | |
789b23bc NF |
235 | }; |
236 | ||
237 | /* | |
238 | * The two programmable clocks. | |
239 | * You must configure pin multiplexing to bring these signals out. | |
240 | */ | |
241 | static struct clk pck0 = { | |
242 | .name = "pck0", | |
243 | .pmc_mask = AT91_PMC_PCK0, | |
244 | .type = CLK_TYPE_PROGRAMMABLE, | |
245 | .id = 0, | |
246 | }; | |
247 | static struct clk pck1 = { | |
248 | .name = "pck1", | |
249 | .pmc_mask = AT91_PMC_PCK1, | |
250 | .type = CLK_TYPE_PROGRAMMABLE, | |
251 | .id = 1, | |
252 | }; | |
253 | ||
254 | static void __init at91sam9g45_register_clocks(void) | |
255 | { | |
256 | int i; | |
257 | ||
258 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) | |
259 | clk_register(periph_clocks[i]); | |
260 | ||
bd602995 JCPV |
261 | clkdev_add_table(periph_clocks_lookups, |
262 | ARRAY_SIZE(periph_clocks_lookups)); | |
263 | clkdev_add_table(usart_clocks_lookups, | |
264 | ARRAY_SIZE(usart_clocks_lookups)); | |
265 | ||
5f9f0a41 NF |
266 | if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) |
267 | clk_register(&vdec_clk); | |
268 | ||
789b23bc NF |
269 | clk_register(&pck0); |
270 | clk_register(&pck1); | |
271 | } | |
272 | ||
bd602995 JCPV |
273 | static struct clk_lookup console_clock_lookup; |
274 | ||
275 | void __init at91sam9g45_set_console_clock(int id) | |
276 | { | |
277 | if (id >= ARRAY_SIZE(usart_clocks_lookups)) | |
278 | return; | |
279 | ||
280 | console_clock_lookup.con_id = "usart"; | |
281 | console_clock_lookup.clk = usart_clocks_lookups[id].clk; | |
282 | clkdev_add(&console_clock_lookup); | |
283 | } | |
284 | ||
789b23bc NF |
285 | /* -------------------------------------------------------------------- |
286 | * GPIO | |
287 | * -------------------------------------------------------------------- */ | |
288 | ||
289 | static struct at91_gpio_bank at91sam9g45_gpio[] = { | |
290 | { | |
291 | .id = AT91SAM9G45_ID_PIOA, | |
292 | .offset = AT91_PIOA, | |
293 | .clock = &pioA_clk, | |
294 | }, { | |
295 | .id = AT91SAM9G45_ID_PIOB, | |
296 | .offset = AT91_PIOB, | |
297 | .clock = &pioB_clk, | |
298 | }, { | |
299 | .id = AT91SAM9G45_ID_PIOC, | |
300 | .offset = AT91_PIOC, | |
301 | .clock = &pioC_clk, | |
302 | }, { | |
303 | .id = AT91SAM9G45_ID_PIODE, | |
304 | .offset = AT91_PIOD, | |
305 | .clock = &pioDE_clk, | |
306 | }, { | |
307 | .id = AT91SAM9G45_ID_PIODE, | |
308 | .offset = AT91_PIOE, | |
309 | .clock = &pioDE_clk, | |
310 | } | |
311 | }; | |
312 | ||
313 | static void at91sam9g45_reset(void) | |
314 | { | |
315 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); | |
316 | } | |
317 | ||
318 | static void at91sam9g45_poweroff(void) | |
319 | { | |
320 | at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); | |
321 | } | |
322 | ||
323 | ||
324 | /* -------------------------------------------------------------------- | |
325 | * AT91SAM9G45 processor initialization | |
326 | * -------------------------------------------------------------------- */ | |
327 | ||
21d08b9d | 328 | static void __init at91sam9g45_map_io(void) |
789b23bc | 329 | { |
21d08b9d | 330 | iotable_init(at91sam9g45_sram_desc, ARRAY_SIZE(at91sam9g45_sram_desc)); |
1b021a3b | 331 | } |
789b23bc | 332 | |
21d08b9d | 333 | static void __init at91sam9g45_initialize(unsigned long main_clock) |
1b021a3b | 334 | { |
789b23bc NF |
335 | at91_arch_reset = at91sam9g45_reset; |
336 | pm_power_off = at91sam9g45_poweroff; | |
337 | at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0); | |
338 | ||
339 | /* Init clock subsystem */ | |
340 | at91_clock_init(main_clock); | |
341 | ||
342 | /* Register the processor-specific clocks */ | |
343 | at91sam9g45_register_clocks(); | |
344 | ||
345 | /* Register GPIO subsystem */ | |
346 | at91_gpio_init(at91sam9g45_gpio, 5); | |
347 | } | |
348 | ||
349 | /* -------------------------------------------------------------------- | |
350 | * Interrupt initialization | |
351 | * -------------------------------------------------------------------- */ | |
352 | ||
353 | /* | |
354 | * The default interrupt priority levels (0 = lowest, 7 = highest). | |
355 | */ | |
356 | static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = { | |
357 | 7, /* Advanced Interrupt Controller (FIQ) */ | |
358 | 7, /* System Peripherals */ | |
359 | 1, /* Parallel IO Controller A */ | |
360 | 1, /* Parallel IO Controller B */ | |
361 | 1, /* Parallel IO Controller C */ | |
362 | 1, /* Parallel IO Controller D and E */ | |
363 | 0, | |
364 | 5, /* USART 0 */ | |
365 | 5, /* USART 1 */ | |
366 | 5, /* USART 2 */ | |
367 | 5, /* USART 3 */ | |
368 | 0, /* Multimedia Card Interface 0 */ | |
369 | 6, /* Two-Wire Interface 0 */ | |
370 | 6, /* Two-Wire Interface 1 */ | |
371 | 5, /* Serial Peripheral Interface 0 */ | |
372 | 5, /* Serial Peripheral Interface 1 */ | |
373 | 4, /* Serial Synchronous Controller 0 */ | |
374 | 4, /* Serial Synchronous Controller 1 */ | |
375 | 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */ | |
376 | 0, /* Pulse Width Modulation Controller */ | |
377 | 0, /* Touch Screen Controller */ | |
378 | 0, /* DMA Controller */ | |
379 | 2, /* USB Host High Speed port */ | |
380 | 3, /* LDC Controller */ | |
381 | 5, /* AC97 Controller */ | |
382 | 3, /* Ethernet */ | |
383 | 0, /* Image Sensor Interface */ | |
384 | 2, /* USB Device High speed port */ | |
385 | 0, | |
386 | 0, /* Multimedia Card Interface 1 */ | |
387 | 0, | |
388 | 0, /* Advanced Interrupt Controller (IRQ0) */ | |
389 | }; | |
390 | ||
21d08b9d JCPV |
391 | struct at91_soc __initdata at91sam9g45_soc = { |
392 | .map_io = at91sam9g45_map_io, | |
92100c12 | 393 | .default_irq_priority = at91sam9g45_default_irq_priority, |
21d08b9d JCPV |
394 | .init = at91sam9g45_initialize, |
395 | }; |