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USB: ehci-atmel: add needed of.h header file
[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9rl_devices.c
CommitLineData
877d7720
AV		 1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9#include <asm/mach/arch.h>
10#include <asm/mach/map.h>
11
c6686ff9 12#include <linux/dma-mapping.h>
2f8163ba 13#include <linux/gpio.h>
877d7720 14#include <linux/platform_device.h>
f230d3f5 15#include <linux/i2c-gpio.h>
877d7720 16
f230d3f5 17#include <linux/fb.h>
877d7720
AV		 18#include <video/atmel_lcdc.h>
19
a09e64fb 20#include <mach/board.h>
a09e64fb
RK		 21#include <mach/at91sam9rl.h>
22#include <mach/at91sam9rl_matrix.h>
4342d647 23#include <mach/at91_matrix.h>
a09e64fb 24#include <mach/at91sam9_smc.h>
6ff89e9d 25#include <mach/at_hdmac.h>
877d7720
AV		 26
27#include "generic.h"
28
877d7720 29
6ff89e9d
NF		 30/* --------------------------------------------------------------------
31 * HDMAC - AHB DMA Controller
32 * -------------------------------------------------------------------- */
33
34#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
35static u64 hdmac_dmamask = DMA_BIT_MASK(32);
36
6ff89e9d
NF		 37static struct resource hdmac_resources[] = {
38 [0] = {
9627b200
JCPV		 39 .start = AT91SAM9RL_BASE_DMA,
40 .end = AT91SAM9RL_BASE_DMA + SZ_512 - 1,
6ff89e9d
NF		 41 .flags = IORESOURCE_MEM,
42 },
43 [2] = {
44 .start = AT91SAM9RL_ID_DMA,
45 .end = AT91SAM9RL_ID_DMA,
46 .flags = IORESOURCE_IRQ,
47 },
48};
49
50static struct platform_device at_hdmac_device = {
bdad0b9a 51 .name = "at91sam9rl_dma",
6ff89e9d
NF		 52 .id = -1,
53 .dev = {
54 .dma_mask = &hdmac_dmamask,
55 .coherent_dma_mask = DMA_BIT_MASK(32),
6ff89e9d
NF		 56 },
57 .resource = hdmac_resources,
58 .num_resources = ARRAY_SIZE(hdmac_resources),
59};
60
61void __init at91_add_device_hdmac(void)
62{
6ff89e9d
NF		 63 platform_device_register(&at_hdmac_device);
64}
65#else
66void __init at91_add_device_hdmac(void) {}
67#endif
68
ba45ca43
NF		 69/* --------------------------------------------------------------------
70 * USB HS Device (Gadget)
71 * -------------------------------------------------------------------- */
72
dd0b3825 73#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
ba45ca43
NF		 74
75static struct resource usba_udc_resources[] = {
76 [0] = {
77 .start = AT91SAM9RL_UDPHS_FIFO,
78 .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
79 .flags = IORESOURCE_MEM,
80 },
81 [1] = {
82 .start = AT91SAM9RL_BASE_UDPHS,
83 .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
84 .flags = IORESOURCE_MEM,
85 },
86 [2] = {
87 .start = AT91SAM9RL_ID_UDPHS,
88 .end = AT91SAM9RL_ID_UDPHS,
89 .flags = IORESOURCE_IRQ,
90 },
91};
92
93#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
94 [idx] = { \
95 .name = nam, \
96 .index = idx, \
97 .fifo_size = maxpkt, \
98 .nr_banks = maxbk, \
99 .can_dma = dma, \
100 .can_isoc = isoc, \
101 }
102
103static struct usba_ep_data usba_udc_ep[] __initdata = {
104 EP("ep0", 0, 64, 1, 0, 0),
105 EP("ep1", 1, 1024, 2, 1, 1),
106 EP("ep2", 2, 1024, 2, 1, 1),
107 EP("ep3", 3, 1024, 3, 1, 0),
108 EP("ep4", 4, 1024, 3, 1, 0),
109 EP("ep5", 5, 1024, 3, 1, 1),
110 EP("ep6", 6, 1024, 3, 1, 1),
111};
112
113#undef EP
114
115/*
116 * pdata doesn't have room for any endpoints, so we need to
117 * append room for the ones we need right after it.
118 */
119static struct {
120 struct usba_platform_data pdata;
121 struct usba_ep_data ep[7];
122} usba_udc_data;
123
124static struct platform_device at91_usba_udc_device = {
125 .name = "atmel_usba_udc",
126 .id = -1,
127 .dev = {
128 .platform_data = &usba_udc_data.pdata,
129 },
130 .resource = usba_udc_resources,
131 .num_resources = ARRAY_SIZE(usba_udc_resources),
132};
133
134void __init at91_add_device_usba(struct usba_platform_data *data)
135{
136 /*
137 * Invalid pins are 0 on AT91, but the usba driver is shared
138 * with AVR32, which use negative values instead. Once/if
139 * gpio_is_valid() is ported to AT91, revisit this code.
140 */
141 usba_udc_data.pdata.vbus_pin = -EINVAL;
142 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
6eab04a8 143 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
ba45ca43 144
cc9f9aef 145 if (data && gpio_is_valid(data->vbus_pin)) {
ba45ca43
NF		 146 at91_set_gpio_input(data->vbus_pin, 0);
147 at91_set_deglitch(data->vbus_pin, 1);
148 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
149 }
150
151 /* Pullup pin is handled internally by USB device peripheral */
152
ba45ca43
NF		 153 platform_device_register(&at91_usba_udc_device);
154}
155#else
156void __init at91_add_device_usba(struct usba_platform_data *data) {}
157#endif
158
159
877d7720
AV		 160/* --------------------------------------------------------------------
161 * MMC / SD
162 * -------------------------------------------------------------------- */
163
164#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
c6686ff9 165static u64 mmc_dmamask = DMA_BIT_MASK(32);
877d7720
AV		 166static struct at91_mmc_data mmc_data;
167
168static struct resource mmc_resources[] = {
169 [0] = {
170 .start = AT91SAM9RL_BASE_MCI,
171 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
172 .flags = IORESOURCE_MEM,
173 },
174 [1] = {
175 .start = AT91SAM9RL_ID_MCI,
176 .end = AT91SAM9RL_ID_MCI,
177 .flags = IORESOURCE_IRQ,
178 },
179};
180
181static struct platform_device at91sam9rl_mmc_device = {
182 .name = "at91_mci",
183 .id = -1,
184 .dev = {
185 .dma_mask = &mmc_dmamask,
c6686ff9 186 .coherent_dma_mask = DMA_BIT_MASK(32),
877d7720
AV		 187 .platform_data = &mmc_data,
188 },
189 .resource = mmc_resources,
190 .num_resources = ARRAY_SIZE(mmc_resources),
191};
192
193void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
194{
195 if (!data)
196 return;
197
198 /* input/irq */
cc9f9aef 199 if (gpio_is_valid(data->det_pin)) {
877d7720
AV		 200 at91_set_gpio_input(data->det_pin, 1);
201 at91_set_deglitch(data->det_pin, 1);
202 }
cc9f9aef 203 if (gpio_is_valid(data->wp_pin))
877d7720 204 at91_set_gpio_input(data->wp_pin, 1);
cc9f9aef 205 if (gpio_is_valid(data->vcc_pin))
877d7720
AV		 206 at91_set_gpio_output(data->vcc_pin, 0);
207
208 /* CLK */
209 at91_set_A_periph(AT91_PIN_PA2, 0);
210
211 /* CMD */
212 at91_set_A_periph(AT91_PIN_PA1, 1);
213
214 /* DAT0, maybe DAT1..DAT3 */
215 at91_set_A_periph(AT91_PIN_PA0, 1);
216 if (data->wire4) {
217 at91_set_A_periph(AT91_PIN_PA3, 1);
218 at91_set_A_periph(AT91_PIN_PA4, 1);
219 at91_set_A_periph(AT91_PIN_PA5, 1);
220 }
221
222 mmc_data = *data;
223 platform_device_register(&at91sam9rl_mmc_device);
224}
225#else
226void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
227#endif
228
229
230/* --------------------------------------------------------------------
231 * NAND / SmartMedia
232 * -------------------------------------------------------------------- */
233
f6ed6f78 234#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
3c3796cc 235static struct atmel_nand_data nand_data;
877d7720
AV		 236
237#define NAND_BASE AT91_CHIPSELECT_3
238
239static struct resource nand_resources[] = {
d7a2415f 240 [0] = {
877d7720
AV		 241 .start = NAND_BASE,
242 .end = NAND_BASE + SZ_256M - 1,
243 .flags = IORESOURCE_MEM,
d7a2415f
AV		 244 },
245 [1] = {
d28edd1b
JCPV		 246 .start = AT91SAM9RL_BASE_ECC,
247 .end = AT91SAM9RL_BASE_ECC + SZ_512 - 1,
d7a2415f 248 .flags = IORESOURCE_MEM,
877d7720
AV		 249 }
250};
251
3c3796cc
HS		 252static struct platform_device atmel_nand_device = {
253 .name = "atmel_nand",
877d7720
AV		 254 .id = -1,
255 .dev = {
256 .platform_data = &nand_data,
257 },
258 .resource = nand_resources,
259 .num_resources = ARRAY_SIZE(nand_resources),
260};
261
3c3796cc 262void __init at91_add_device_nand(struct atmel_nand_data *data)
877d7720
AV		 263{
264 unsigned long csa;
265
266 if (!data)
267 return;
268
4342d647
JCPV		 269 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
270 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
877d7720 271
877d7720 272 /* enable pin */
cc9f9aef 273 if (gpio_is_valid(data->enable_pin))
877d7720
AV		 274 at91_set_gpio_output(data->enable_pin, 1);
275
276 /* ready/busy pin */
cc9f9aef 277 if (gpio_is_valid(data->rdy_pin))
877d7720
AV		 278 at91_set_gpio_input(data->rdy_pin, 1);
279
280 /* card detect pin */
cc9f9aef 281 if (gpio_is_valid(data->det_pin))
877d7720
AV		 282 at91_set_gpio_input(data->det_pin, 1);
283
284 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
285 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
286
287 nand_data = *data;
3c3796cc 288 platform_device_register(&atmel_nand_device);
877d7720
AV		 289}
290
291#else
3c3796cc 292void __init at91_add_device_nand(struct atmel_nand_data *data) {}
877d7720
AV		 293#endif
294
295
296/* --------------------------------------------------------------------
297 * TWI (i2c)
298 * -------------------------------------------------------------------- */
299
f230d3f5
AV		 300/*
301 * Prefer the GPIO code since the TWI controller isn't robust
302 * (gets overruns and underruns under load) and can only issue
303 * repeated STARTs in one scenario (the driver doesn't yet handle them).
304 */
305#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
306
307static struct i2c_gpio_platform_data pdata = {
308 .sda_pin = AT91_PIN_PA23,
309 .sda_is_open_drain = 1,
310 .scl_pin = AT91_PIN_PA24,
311 .scl_is_open_drain = 1,
312 .udelay = 2, /* ~100 kHz */
313};
314
315static struct platform_device at91sam9rl_twi_device = {
316 .name = "i2c-gpio",
317 .id = -1,
318 .dev.platform_data = &pdata,
319};
320
321void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
322{
323 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
324 at91_set_multi_drive(AT91_PIN_PA23, 1);
325
326 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
327 at91_set_multi_drive(AT91_PIN_PA24, 1);
328
329 i2c_register_board_info(0, devices, nr_devices);
330 platform_device_register(&at91sam9rl_twi_device);
331}
332
333#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
877d7720
AV		 334
335static struct resource twi_resources[] = {
336 [0] = {
337 .start = AT91SAM9RL_BASE_TWI0,
338 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
339 .flags = IORESOURCE_MEM,
340 },
341 [1] = {
342 .start = AT91SAM9RL_ID_TWI0,
343 .end = AT91SAM9RL_ID_TWI0,
344 .flags = IORESOURCE_IRQ,
345 },
346};
347
348static struct platform_device at91sam9rl_twi_device = {
349 .name = "at91_i2c",
350 .id = -1,
351 .resource = twi_resources,
352 .num_resources = ARRAY_SIZE(twi_resources),
353};
354
f230d3f5 355void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
877d7720
AV		 356{
357 /* pins used for TWI interface */
358 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
359 at91_set_multi_drive(AT91_PIN_PA23, 1);
360
361 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
362 at91_set_multi_drive(AT91_PIN_PA24, 1);
363
f230d3f5 364 i2c_register_board_info(0, devices, nr_devices);
877d7720
AV		 365 platform_device_register(&at91sam9rl_twi_device);
366}
367#else
f230d3f5 368void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
877d7720
AV		 369#endif
370
371
372/* --------------------------------------------------------------------
373 * SPI
374 * -------------------------------------------------------------------- */
375
376#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 377static u64 spi_dmamask = DMA_BIT_MASK(32);
877d7720
AV		 378
379static struct resource spi_resources[] = {
380 [0] = {
381 .start = AT91SAM9RL_BASE_SPI,
382 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
383 .flags = IORESOURCE_MEM,
384 },
385 [1] = {
386 .start = AT91SAM9RL_ID_SPI,
387 .end = AT91SAM9RL_ID_SPI,
388 .flags = IORESOURCE_IRQ,
389 },
390};
391
392static struct platform_device at91sam9rl_spi_device = {
393 .name = "atmel_spi",
394 .id = 0,
395 .dev = {
396 .dma_mask = &spi_dmamask,
c6686ff9 397 .coherent_dma_mask = DMA_BIT_MASK(32),
877d7720
AV		 398 },
399 .resource = spi_resources,
400 .num_resources = ARRAY_SIZE(spi_resources),
401};
402
403static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
404
405
406void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
407{
408 int i;
409 unsigned long cs_pin;
410
411 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
412 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
413 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
414
415 /* Enable SPI chip-selects */
416 for (i = 0; i < nr_devices; i++) {
417 if (devices[i].controller_data)
418 cs_pin = (unsigned long) devices[i].controller_data;
419 else
420 cs_pin = spi_standard_cs[devices[i].chip_select];
421
422 /* enable chip-select pin */
423 at91_set_gpio_output(cs_pin, 1);
424
425 /* pass chip-select pin to driver */
426 devices[i].controller_data = (void *) cs_pin;
427 }
428
429 spi_register_board_info(devices, nr_devices);
430 platform_device_register(&at91sam9rl_spi_device);
431}
432#else
433void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
434#endif
435
436
439a3307
NF		 437/* --------------------------------------------------------------------
438 * AC97
439 * -------------------------------------------------------------------- */
440
441#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
442static u64 ac97_dmamask = DMA_BIT_MASK(32);
443static struct ac97c_platform_data ac97_data;
444
445static struct resource ac97_resources[] = {
446 [0] = {
447 .start = AT91SAM9RL_BASE_AC97C,
448 .end = AT91SAM9RL_BASE_AC97C + SZ_16K - 1,
449 .flags = IORESOURCE_MEM,
450 },
451 [1] = {
452 .start = AT91SAM9RL_ID_AC97C,
453 .end = AT91SAM9RL_ID_AC97C,
454 .flags = IORESOURCE_IRQ,
455 },
456};
457
458static struct platform_device at91sam9rl_ac97_device = {
459 .name = "atmel_ac97c",
460 .id = 0,
461 .dev = {
462 .dma_mask = &ac97_dmamask,
463 .coherent_dma_mask = DMA_BIT_MASK(32),
464 .platform_data = &ac97_data,
465 },
466 .resource = ac97_resources,
467 .num_resources = ARRAY_SIZE(ac97_resources),
468};
469
470void __init at91_add_device_ac97(struct ac97c_platform_data *data)
471{
472 if (!data)
473 return;
474
475 at91_set_A_periph(AT91_PIN_PD1, 0); /* AC97FS */
476 at91_set_A_periph(AT91_PIN_PD2, 0); /* AC97CK */
477 at91_set_A_periph(AT91_PIN_PD3, 0); /* AC97TX */
478 at91_set_A_periph(AT91_PIN_PD4, 0); /* AC97RX */
479
480 /* reset */
cc9f9aef 481 if (gpio_is_valid(data->reset_pin))
439a3307
NF		 482 at91_set_gpio_output(data->reset_pin, 0);
483
484 ac97_data = *data;
485 platform_device_register(&at91sam9rl_ac97_device);
486}
487#else
488void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
489#endif
490
491
877d7720
AV		 492/* --------------------------------------------------------------------
493 * LCD Controller
494 * -------------------------------------------------------------------- */
495
496#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
c6686ff9 497static u64 lcdc_dmamask = DMA_BIT_MASK(32);
877d7720
AV		 498static struct atmel_lcdfb_info lcdc_data;
499
500static struct resource lcdc_resources[] = {
501 [0] = {
502 .start = AT91SAM9RL_LCDC_BASE,
503 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
504 .flags = IORESOURCE_MEM,
505 },
506 [1] = {
507 .start = AT91SAM9RL_ID_LCDC,
508 .end = AT91SAM9RL_ID_LCDC,
509 .flags = IORESOURCE_IRQ,
510 },
877d7720
AV		 511};
512
513static struct platform_device at91_lcdc_device = {
514 .name = "atmel_lcdfb",
515 .id = 0,
516 .dev = {
517 .dma_mask = &lcdc_dmamask,
c6686ff9 518 .coherent_dma_mask = DMA_BIT_MASK(32),
877d7720
AV		 519 .platform_data = &lcdc_data,
520 },
521 .resource = lcdc_resources,
522 .num_resources = ARRAY_SIZE(lcdc_resources),
523};
524
525void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
526{
527 if (!data) {
528 return;
529 }
530
531 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
532 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
533 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
534 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
535 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
536 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
537 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
538 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
539 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
540 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
541 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
542 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
543 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
544 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
545 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
546 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
547 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
548 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
549 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
550 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
551 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
552
553 lcdc_data = *data;
554 platform_device_register(&at91_lcdc_device);
555}
556#else
557void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
558#endif
559
560
e5f40bfa
AV		 561/* --------------------------------------------------------------------
562 * Timer/Counter block
563 * -------------------------------------------------------------------- */
564
565#ifdef CONFIG_ATMEL_TCLIB
566
567static struct resource tcb_resources[] = {
568 [0] = {
569 .start = AT91SAM9RL_BASE_TCB0,
570 .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
571 .flags = IORESOURCE_MEM,
572 },
573 [1] = {
574 .start = AT91SAM9RL_ID_TC0,
575 .end = AT91SAM9RL_ID_TC0,
576 .flags = IORESOURCE_IRQ,
577 },
578 [2] = {
579 .start = AT91SAM9RL_ID_TC1,
580 .end = AT91SAM9RL_ID_TC1,
581 .flags = IORESOURCE_IRQ,
582 },
583 [3] = {
584 .start = AT91SAM9RL_ID_TC2,
585 .end = AT91SAM9RL_ID_TC2,
586 .flags = IORESOURCE_IRQ,
587 },
588};
589
590static struct platform_device at91sam9rl_tcb_device = {
591 .name = "atmel_tcb",
592 .id = 0,
593 .resource = tcb_resources,
594 .num_resources = ARRAY_SIZE(tcb_resources),
595};
596
597static void __init at91_add_device_tc(void)
598{
e5f40bfa
AV		 599 platform_device_register(&at91sam9rl_tcb_device);
600}
601#else
602static void __init at91_add_device_tc(void) { }
603#endif
604
605
f7647e63
AV		 606/* --------------------------------------------------------------------
607 * Touchscreen
608 * -------------------------------------------------------------------- */
609
610#if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
611static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
423c9b0d 612static struct at91_tsadcc_data tsadcc_data;
f7647e63
AV		 613
614static struct resource tsadcc_resources[] = {
615 [0] = {
616 .start = AT91SAM9RL_BASE_TSC,
617 .end = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
618 .flags = IORESOURCE_MEM,
619 },
620 [1] = {
621 .start = AT91SAM9RL_ID_TSC,
622 .end = AT91SAM9RL_ID_TSC,
623 .flags = IORESOURCE_IRQ,
624 }
625};
626
627static struct platform_device at91sam9rl_tsadcc_device = {
628 .name = "atmel_tsadcc",
629 .id = -1,
630 .dev = {
631 .dma_mask = &tsadcc_dmamask,
632 .coherent_dma_mask = DMA_BIT_MASK(32),
423c9b0d 633 .platform_data = &tsadcc_data,
f7647e63
AV		 634 },
635 .resource = tsadcc_resources,
636 .num_resources = ARRAY_SIZE(tsadcc_resources),
637};
638
423c9b0d 639void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
f7647e63 640{
423c9b0d
NF		 641 if (!data)
642 return;
643
f7647e63
AV		 644 at91_set_A_periph(AT91_PIN_PA17, 0); /* AD0_XR */
645 at91_set_A_periph(AT91_PIN_PA18, 0); /* AD1_XL */
646 at91_set_A_periph(AT91_PIN_PA19, 0); /* AD2_YT */
647 at91_set_A_periph(AT91_PIN_PA20, 0); /* AD3_TB */
648
423c9b0d 649 tsadcc_data = *data;
f7647e63
AV		 650 platform_device_register(&at91sam9rl_tsadcc_device);
651}
652#else
423c9b0d 653void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
f7647e63
AV		 654#endif
655
656
884f5a6a
AV		 657/* --------------------------------------------------------------------
658 * RTC
659 * -------------------------------------------------------------------- */
660
661#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
662static struct platform_device at91sam9rl_rtc_device = {
663 .name = "at91_rtc",
664 .id = -1,
665 .num_resources = 0,
666};
667
668static void __init at91_add_device_rtc(void)
669{
670 platform_device_register(&at91sam9rl_rtc_device);
671}
672#else
673static void __init at91_add_device_rtc(void) {}
674#endif
675
676
677/* --------------------------------------------------------------------
678 * RTT
679 * -------------------------------------------------------------------- */
680
681static struct resource rtt_resources[] = {
682 {
eab5fd67
JCPV		 683 .start = AT91SAM9RL_BASE_RTT,
684 .end = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
884f5a6a 685 .flags = IORESOURCE_MEM,
b3af8b49
JCPV		 686 }, {
687 .flags = IORESOURCE_MEM,
884f5a6a
AV		 688 }
689};
690
691static struct platform_device at91sam9rl_rtt_device = {
692 .name = "at91_rtt",
4fd9212c 693 .id = 0,
884f5a6a 694 .resource = rtt_resources,
884f5a6a
AV		 695};
696
205056a3
JCPV		 697#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
698static void __init at91_add_device_rtt_rtc(void)
699{
700 at91sam9rl_rtt_device.name = "rtc-at91sam9";
b3af8b49
JCPV		 701 /*
702 * The second resource is needed:
703 * GPBR will serve as the storage for RTC time offset
704 */
705 at91sam9rl_rtt_device.num_resources = 2;
706 rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
707 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
708 rtt_resources[1].end = rtt_resources[1].start + 3;
205056a3
JCPV		 709}
710#else
b3af8b49
JCPV		 711static void __init at91_add_device_rtt_rtc(void)
712{
713 /* Only one resource is needed: RTT not used as RTC */
714 at91sam9rl_rtt_device.num_resources = 1;
715}
205056a3
JCPV		 716#endif
717
884f5a6a
AV		 718static void __init at91_add_device_rtt(void)
719{
205056a3 720 at91_add_device_rtt_rtc();
884f5a6a
AV		 721 platform_device_register(&at91sam9rl_rtt_device);
722}
723
724
725/* --------------------------------------------------------------------
726 * Watchdog
727 * -------------------------------------------------------------------- */
728
2af29b78 729#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
c1c30a29
JCPV		 730static struct resource wdt_resources[] = {
731 {
732 .start = AT91SAM9RL_BASE_WDT,
733 .end = AT91SAM9RL_BASE_WDT + SZ_16 - 1,
734 .flags = IORESOURCE_MEM,
735 }
736};
737
884f5a6a
AV		 738static struct platform_device at91sam9rl_wdt_device = {
739 .name = "at91_wdt",
740 .id = -1,
c1c30a29
JCPV		 741 .resource = wdt_resources,
742 .num_resources = ARRAY_SIZE(wdt_resources),
884f5a6a
AV		 743};
744
745static void __init at91_add_device_watchdog(void)
746{
747 platform_device_register(&at91sam9rl_wdt_device);
748}
749#else
750static void __init at91_add_device_watchdog(void) {}
751#endif
752
753
bb1ad68b
AV		 754/* --------------------------------------------------------------------
755 * PWM
756 * --------------------------------------------------------------------*/
757
758#if defined(CONFIG_ATMEL_PWM)
759static u32 pwm_mask;
760
761static struct resource pwm_resources[] = {
762 [0] = {
763 .start = AT91SAM9RL_BASE_PWMC,
764 .end = AT91SAM9RL_BASE_PWMC + SZ_16K - 1,
765 .flags = IORESOURCE_MEM,
766 },
767 [1] = {
768 .start = AT91SAM9RL_ID_PWMC,
769 .end = AT91SAM9RL_ID_PWMC,
770 .flags = IORESOURCE_IRQ,
771 },
772};
773
774static struct platform_device at91sam9rl_pwm0_device = {
775 .name = "atmel_pwm",
776 .id = -1,
777 .dev = {
778 .platform_data = &pwm_mask,
779 },
780 .resource = pwm_resources,
781 .num_resources = ARRAY_SIZE(pwm_resources),
782};
783
784void __init at91_add_device_pwm(u32 mask)
785{
786 if (mask & (1 << AT91_PWM0))
787 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM0 */
788
789 if (mask & (1 << AT91_PWM1))
790 at91_set_B_periph(AT91_PIN_PB9, 1); /* enable PWM1 */
791
792 if (mask & (1 << AT91_PWM2))
793 at91_set_B_periph(AT91_PIN_PD5, 1); /* enable PWM2 */
794
795 if (mask & (1 << AT91_PWM3))
796 at91_set_B_periph(AT91_PIN_PD8, 1); /* enable PWM3 */
797
798 pwm_mask = mask;
799
800 platform_device_register(&at91sam9rl_pwm0_device);
801}
802#else
803void __init at91_add_device_pwm(u32 mask) {}
804#endif
805
806
bfbc3266
AV		 807/* --------------------------------------------------------------------
808 * SSC -- Synchronous Serial Controller
809 * -------------------------------------------------------------------- */
810
811#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
812static u64 ssc0_dmamask = DMA_BIT_MASK(32);
813
814static struct resource ssc0_resources[] = {
815 [0] = {
816 .start = AT91SAM9RL_BASE_SSC0,
817 .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
818 .flags = IORESOURCE_MEM,
819 },
820 [1] = {
821 .start = AT91SAM9RL_ID_SSC0,
822 .end = AT91SAM9RL_ID_SSC0,
823 .flags = IORESOURCE_IRQ,
824 },
825};
826
827static struct platform_device at91sam9rl_ssc0_device = {
828 .name = "ssc",
829 .id = 0,
830 .dev = {
831 .dma_mask = &ssc0_dmamask,
832 .coherent_dma_mask = DMA_BIT_MASK(32),
833 },
834 .resource = ssc0_resources,
835 .num_resources = ARRAY_SIZE(ssc0_resources),
836};
837
838static inline void configure_ssc0_pins(unsigned pins)
839{
840 if (pins & ATMEL_SSC_TF)
841 at91_set_A_periph(AT91_PIN_PC0, 1);
842 if (pins & ATMEL_SSC_TK)
843 at91_set_A_periph(AT91_PIN_PC1, 1);
844 if (pins & ATMEL_SSC_TD)
845 at91_set_A_periph(AT91_PIN_PA15, 1);
846 if (pins & ATMEL_SSC_RD)
847 at91_set_A_periph(AT91_PIN_PA16, 1);
848 if (pins & ATMEL_SSC_RK)
849 at91_set_B_periph(AT91_PIN_PA10, 1);
850 if (pins & ATMEL_SSC_RF)
851 at91_set_B_periph(AT91_PIN_PA22, 1);
852}
853
854static u64 ssc1_dmamask = DMA_BIT_MASK(32);
855
856static struct resource ssc1_resources[] = {
857 [0] = {
858 .start = AT91SAM9RL_BASE_SSC1,
859 .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
860 .flags = IORESOURCE_MEM,
861 },
862 [1] = {
863 .start = AT91SAM9RL_ID_SSC1,
864 .end = AT91SAM9RL_ID_SSC1,
865 .flags = IORESOURCE_IRQ,
866 },
867};
868
869static struct platform_device at91sam9rl_ssc1_device = {
870 .name = "ssc",
871 .id = 1,
872 .dev = {
873 .dma_mask = &ssc1_dmamask,
874 .coherent_dma_mask = DMA_BIT_MASK(32),
875 },
876 .resource = ssc1_resources,
877 .num_resources = ARRAY_SIZE(ssc1_resources),
878};
879
880static inline void configure_ssc1_pins(unsigned pins)
881{
882 if (pins & ATMEL_SSC_TF)
883 at91_set_B_periph(AT91_PIN_PA29, 1);
884 if (pins & ATMEL_SSC_TK)
885 at91_set_B_periph(AT91_PIN_PA30, 1);
886 if (pins & ATMEL_SSC_TD)
887 at91_set_B_periph(AT91_PIN_PA13, 1);
888 if (pins & ATMEL_SSC_RD)
889 at91_set_B_periph(AT91_PIN_PA14, 1);
890 if (pins & ATMEL_SSC_RK)
891 at91_set_B_periph(AT91_PIN_PA9, 1);
892 if (pins & ATMEL_SSC_RF)
893 at91_set_B_periph(AT91_PIN_PA8, 1);
894}
895
896/*
bfbc3266
AV		 897 * SSC controllers are accessed through library code, instead of any
898 * kind of all-singing/all-dancing driver. For example one could be
899 * used by a particular I2S audio codec's driver, while another one
900 * on the same system might be used by a custom data capture driver.
901 */
902void __init at91_add_device_ssc(unsigned id, unsigned pins)
903{
904 struct platform_device *pdev;
905
906 /*
907 * NOTE: caller is responsible for passing information matching
908 * "pins" to whatever will be using each particular controller.
909 */
910 switch (id) {
911 case AT91SAM9RL_ID_SSC0:
912 pdev = &at91sam9rl_ssc0_device;
913 configure_ssc0_pins(pins);
bfbc3266
AV		 914 break;
915 case AT91SAM9RL_ID_SSC1:
916 pdev = &at91sam9rl_ssc1_device;
917 configure_ssc1_pins(pins);
bfbc3266
AV		 918 break;
919 default:
920 return;
921 }
922
923 platform_device_register(pdev);
924}
925
926#else
927void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
928#endif
929
930
877d7720
AV		 931/* --------------------------------------------------------------------
932 * UART
933 * -------------------------------------------------------------------- */
934
935#if defined(CONFIG_SERIAL_ATMEL)
936static struct resource dbgu_resources[] = {
937 [0] = {
13079a73
JCPV		 938 .start = AT91SAM9RL_BASE_DBGU,
939 .end = AT91SAM9RL_BASE_DBGU + SZ_512 - 1,
877d7720
AV		 940 .flags = IORESOURCE_MEM,
941 },
942 [1] = {
943 .start = AT91_ID_SYS,
944 .end = AT91_ID_SYS,
945 .flags = IORESOURCE_IRQ,
946 },
947};
948
949static struct atmel_uart_data dbgu_data = {
950 .use_dma_tx = 0,
951 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
877d7720
AV		 952};
953
c6686ff9
AV		 954static u64 dbgu_dmamask = DMA_BIT_MASK(32);
955
877d7720
AV		 956static struct platform_device at91sam9rl_dbgu_device = {
957 .name = "atmel_usart",
958 .id = 0,
959 .dev = {
c6686ff9
AV		 960 .dma_mask = &dbgu_dmamask,
961 .coherent_dma_mask = DMA_BIT_MASK(32),
962 .platform_data = &dbgu_data,
877d7720
AV		 963 },
964 .resource = dbgu_resources,
965 .num_resources = ARRAY_SIZE(dbgu_resources),
966};
967
968static inline void configure_dbgu_pins(void)
969{
970 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
971 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
972}
973
974static struct resource uart0_resources[] = {
975 [0] = {
976 .start = AT91SAM9RL_BASE_US0,
977 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
978 .flags = IORESOURCE_MEM,
979 },
980 [1] = {
981 .start = AT91SAM9RL_ID_US0,
982 .end = AT91SAM9RL_ID_US0,
983 .flags = IORESOURCE_IRQ,
984 },
985};
986
987static struct atmel_uart_data uart0_data = {
988 .use_dma_tx = 1,
989 .use_dma_rx = 1,
990};
991
c6686ff9
AV		 992static u64 uart0_dmamask = DMA_BIT_MASK(32);
993
877d7720
AV		 994static struct platform_device at91sam9rl_uart0_device = {
995 .name = "atmel_usart",
996 .id = 1,
997 .dev = {
c6686ff9
AV		 998 .dma_mask = &uart0_dmamask,
999 .coherent_dma_mask = DMA_BIT_MASK(32),
1000 .platform_data = &uart0_data,
877d7720
AV		 1001 },
1002 .resource = uart0_resources,
1003 .num_resources = ARRAY_SIZE(uart0_resources),
1004};
1005
c8f385a6 1006static inline void configure_usart0_pins(unsigned pins)
877d7720
AV		 1007{
1008 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
1009 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
c8f385a6
AV		 1010
1011 if (pins & ATMEL_UART_RTS)
1012 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
1013 if (pins & ATMEL_UART_CTS)
1014 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
1015 if (pins & ATMEL_UART_DSR)
1016 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */
1017 if (pins & ATMEL_UART_DTR)
1018 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */
1019 if (pins & ATMEL_UART_DCD)
1020 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */
1021 if (pins & ATMEL_UART_RI)
1022 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */
877d7720
AV		 1023}
1024
1025static struct resource uart1_resources[] = {
1026 [0] = {
1027 .start = AT91SAM9RL_BASE_US1,
1028 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
1029 .flags = IORESOURCE_MEM,
1030 },
1031 [1] = {
1032 .start = AT91SAM9RL_ID_US1,
1033 .end = AT91SAM9RL_ID_US1,
1034 .flags = IORESOURCE_IRQ,
1035 },
1036};
1037
1038static struct atmel_uart_data uart1_data = {
1039 .use_dma_tx = 1,
1040 .use_dma_rx = 1,
1041};
1042
c6686ff9
AV		 1043static u64 uart1_dmamask = DMA_BIT_MASK(32);
1044
877d7720
AV		 1045static struct platform_device at91sam9rl_uart1_device = {
1046 .name = "atmel_usart",
1047 .id = 2,
1048 .dev = {
c6686ff9
AV		 1049 .dma_mask = &uart1_dmamask,
1050 .coherent_dma_mask = DMA_BIT_MASK(32),
1051 .platform_data = &uart1_data,
877d7720
AV		 1052 },
1053 .resource = uart1_resources,
1054 .num_resources = ARRAY_SIZE(uart1_resources),
1055};
1056
c8f385a6 1057static inline void configure_usart1_pins(unsigned pins)
877d7720
AV		 1058{
1059 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
1060 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
c8f385a6
AV		 1061
1062 if (pins & ATMEL_UART_RTS)
1063 at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */
1064 if (pins & ATMEL_UART_CTS)
1065 at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */
877d7720
AV		 1066}
1067
1068static struct resource uart2_resources[] = {
1069 [0] = {
1070 .start = AT91SAM9RL_BASE_US2,
1071 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
1072 .flags = IORESOURCE_MEM,
1073 },
1074 [1] = {
1075 .start = AT91SAM9RL_ID_US2,
1076 .end = AT91SAM9RL_ID_US2,
1077 .flags = IORESOURCE_IRQ,
1078 },
1079};
1080
1081static struct atmel_uart_data uart2_data = {
1082 .use_dma_tx = 1,
1083 .use_dma_rx = 1,
1084};
1085
c6686ff9
AV		 1086static u64 uart2_dmamask = DMA_BIT_MASK(32);
1087
877d7720
AV		 1088static struct platform_device at91sam9rl_uart2_device = {
1089 .name = "atmel_usart",
1090 .id = 3,
1091 .dev = {
c6686ff9
AV		 1092 .dma_mask = &uart2_dmamask,
1093 .coherent_dma_mask = DMA_BIT_MASK(32),
1094 .platform_data = &uart2_data,
877d7720
AV		 1095 },
1096 .resource = uart2_resources,
1097 .num_resources = ARRAY_SIZE(uart2_resources),
1098};
1099
c8f385a6 1100static inline void configure_usart2_pins(unsigned pins)
877d7720
AV		 1101{
1102 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
1103 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
c8f385a6
AV		 1104
1105 if (pins & ATMEL_UART_RTS)
1106 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */
1107 if (pins & ATMEL_UART_CTS)
1108 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */
877d7720
AV		 1109}
1110
1111static struct resource uart3_resources[] = {
1112 [0] = {
1113 .start = AT91SAM9RL_BASE_US3,
1114 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
1115 .flags = IORESOURCE_MEM,
1116 },
1117 [1] = {
1118 .start = AT91SAM9RL_ID_US3,
1119 .end = AT91SAM9RL_ID_US3,
1120 .flags = IORESOURCE_IRQ,
1121 },
1122};
1123
1124static struct atmel_uart_data uart3_data = {
1125 .use_dma_tx = 1,
1126 .use_dma_rx = 1,
1127};
1128
c6686ff9
AV		 1129static u64 uart3_dmamask = DMA_BIT_MASK(32);
1130
877d7720
AV		 1131static struct platform_device at91sam9rl_uart3_device = {
1132 .name = "atmel_usart",
1133 .id = 4,
1134 .dev = {
c6686ff9
AV		 1135 .dma_mask = &uart3_dmamask,
1136 .coherent_dma_mask = DMA_BIT_MASK(32),
1137 .platform_data = &uart3_data,
877d7720
AV		 1138 },
1139 .resource = uart3_resources,
1140 .num_resources = ARRAY_SIZE(uart3_resources),
1141};
1142
c8f385a6 1143static inline void configure_usart3_pins(unsigned pins)
877d7720
AV		 1144{
1145 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
1146 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
c8f385a6
AV		 1147
1148 if (pins & ATMEL_UART_RTS)
1149 at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */
1150 if (pins & ATMEL_UART_CTS)
1151 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
877d7720
AV		 1152}
1153
11aadac4 1154static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
877d7720 1155
c8f385a6
AV		 1156void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1157{
1158 struct platform_device *pdev;
2b348e2f 1159 struct atmel_uart_data *pdata;
c8f385a6
AV		 1160
1161 switch (id) {
1162 case 0: /* DBGU */
1163 pdev = &at91sam9rl_dbgu_device;
1164 configure_dbgu_pins();
c8f385a6
AV		 1165 break;
1166 case AT91SAM9RL_ID_US0:
1167 pdev = &at91sam9rl_uart0_device;
1168 configure_usart0_pins(pins);
c8f385a6
AV		 1169 break;
1170 case AT91SAM9RL_ID_US1:
1171 pdev = &at91sam9rl_uart1_device;
1172 configure_usart1_pins(pins);
c8f385a6
AV		 1173 break;
1174 case AT91SAM9RL_ID_US2:
1175 pdev = &at91sam9rl_uart2_device;
1176 configure_usart2_pins(pins);
c8f385a6
AV		 1177 break;
1178 case AT91SAM9RL_ID_US3:
1179 pdev = &at91sam9rl_uart3_device;
1180 configure_usart3_pins(pins);
c8f385a6
AV		 1181 break;
1182 default:
1183 return;
1184 }
2b348e2f
JCPV		 1185 pdata = pdev->dev.platform_data;
1186 pdata->num = portnr; /* update to mapped ID */
c8f385a6
AV		 1187
1188 if (portnr < ATMEL_MAX_UART)
1189 at91_uarts[portnr] = pdev;
1190}
1191
1192void __init at91_set_serial_console(unsigned portnr)
1193{
bd602995 1194 if (portnr < ATMEL_MAX_UART) {
c8f385a6 1195 atmel_default_console_device = at91_uarts[portnr];
5c1f9668 1196 at91sam9rl_set_console_clock(at91_uarts[portnr]->id);
bd602995 1197 }
c8f385a6
AV		 1198}
1199
877d7720
AV		 1200void __init at91_add_device_serial(void)
1201{
1202 int i;
1203
1204 for (i = 0; i < ATMEL_MAX_UART; i++) {
1205 if (at91_uarts[i])
1206 platform_device_register(at91_uarts[i]);
1207 }
11aadac4
AV		 1208
1209 if (!atmel_default_console_device)
1210 printk(KERN_INFO "AT91: No default serial console defined.\n");
877d7720
AV		 1211}
1212#else
c8f385a6
AV		 1213void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1214void __init at91_set_serial_console(unsigned portnr) {}
877d7720
AV		 1215void __init at91_add_device_serial(void) {}
1216#endif
1217
1218
1219/* -------------------------------------------------------------------- */
1220
1221/*
1222 * These devices are always present and don't need any board-specific
1223 * setup.
1224 */
1225static int __init at91_add_standard_devices(void)
1226{
6ff89e9d 1227 at91_add_device_hdmac();
884f5a6a
AV		 1228 at91_add_device_rtc();
1229 at91_add_device_rtt();
1230 at91_add_device_watchdog();
e5f40bfa 1231 at91_add_device_tc();
877d7720
AV		 1232 return 0;
1233}
1234
1235arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
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