Commit | Line | Data |
---|---|---|
73a59c1c | 1 | /* |
9d041268 | 2 | * linux/arch/arm/mach-at91/gpio.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2005 HP Labs | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
f2173834 | 12 | #include <linux/clk.h> |
73a59c1c | 13 | #include <linux/errno.h> |
2f8163ba | 14 | #include <linux/gpio.h> |
07d265dd TG |
15 | #include <linux/interrupt.h> |
16 | #include <linux/irq.h> | |
b66545e7 AV |
17 | #include <linux/debugfs.h> |
18 | #include <linux/seq_file.h> | |
73a59c1c SP |
19 | #include <linux/kernel.h> |
20 | #include <linux/list.h> | |
21 | #include <linux/module.h> | |
fced80c7 | 22 | #include <linux/io.h> |
21f81872 NF |
23 | #include <linux/irqdomain.h> |
24 | #include <linux/of_address.h> | |
25 | #include <linux/of_irq.h> | |
73a59c1c | 26 | |
a09e64fb RK |
27 | #include <mach/hardware.h> |
28 | #include <mach/at91_pio.h> | |
73a59c1c | 29 | |
f2173834 AV |
30 | #include "generic.h" |
31 | ||
f373e8c0 RM |
32 | struct at91_gpio_chip { |
33 | struct gpio_chip chip; | |
34 | struct at91_gpio_chip *next; /* Bank sharing same clock */ | |
4340cde5 | 35 | int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ |
21f81872 | 36 | int pioc_idx; /* PIO bank index */ |
4340cde5 | 37 | void __iomem *regbase; /* PIO bank virtual address */ |
619d4a4b | 38 | struct clk *clock; /* associated clock */ |
21f81872 | 39 | struct irq_domain *domain; /* associated irq domain */ |
f373e8c0 | 40 | }; |
f2173834 | 41 | |
f373e8c0 RM |
42 | #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) |
43 | ||
44 | static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip); | |
45 | static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val); | |
46 | static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset); | |
47 | static int at91_gpiolib_direction_output(struct gpio_chip *chip, | |
48 | unsigned offset, int val); | |
49 | static int at91_gpiolib_direction_input(struct gpio_chip *chip, | |
50 | unsigned offset); | |
f373e8c0 RM |
51 | |
52 | #define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \ | |
53 | { \ | |
54 | .chip = { \ | |
55 | .label = name, \ | |
f373e8c0 RM |
56 | .direction_input = at91_gpiolib_direction_input, \ |
57 | .direction_output = at91_gpiolib_direction_output, \ | |
58 | .get = at91_gpiolib_get, \ | |
59 | .set = at91_gpiolib_set, \ | |
60 | .dbg_show = at91_gpiolib_dbg_show, \ | |
61 | .base = base_gpio, \ | |
62 | .ngpio = nr_gpio, \ | |
63 | }, \ | |
64 | } | |
f2173834 | 65 | |
f373e8c0 | 66 | static struct at91_gpio_chip gpio_chip[] = { |
d0fbda9a JCPV |
67 | AT91_GPIO_CHIP("pioA", 0x00, 32), |
68 | AT91_GPIO_CHIP("pioB", 0x20, 32), | |
69 | AT91_GPIO_CHIP("pioC", 0x40, 32), | |
70 | AT91_GPIO_CHIP("pioD", 0x60, 32), | |
71 | AT91_GPIO_CHIP("pioE", 0x80, 32), | |
f373e8c0 RM |
72 | }; |
73 | ||
74 | static int gpio_banks; | |
73a59c1c SP |
75 | |
76 | static inline void __iomem *pin_to_controller(unsigned pin) | |
77 | { | |
73a59c1c | 78 | pin /= 32; |
f2173834 | 79 | if (likely(pin < gpio_banks)) |
f373e8c0 | 80 | return gpio_chip[pin].regbase; |
73a59c1c SP |
81 | |
82 | return NULL; | |
83 | } | |
84 | ||
85 | static inline unsigned pin_to_mask(unsigned pin) | |
86 | { | |
73a59c1c SP |
87 | return 1 << (pin % 32); |
88 | } | |
89 | ||
90 | ||
91 | /*--------------------------------------------------------------------------*/ | |
92 | ||
93 | /* Not all hardware capabilities are exposed through these calls; they | |
94 | * only encapsulate the most common features and modes. (So if you | |
95 | * want to change signals in groups, do it directly.) | |
96 | * | |
97 | * Bootloaders will usually handle some of the pin multiplexing setup. | |
98 | * The intent is certainly that by the time Linux is fully booted, all | |
99 | * pins should have been fully initialized. These setup calls should | |
100 | * only be used by board setup routines, or possibly in driver probe(). | |
101 | * | |
102 | * For bootloaders doing all that setup, these calls could be inlined | |
103 | * as NOPs so Linux won't duplicate any setup code | |
104 | */ | |
105 | ||
106 | ||
a31c4eea DB |
107 | /* |
108 | * mux the pin to the "GPIO" peripheral role. | |
109 | */ | |
110 | int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup) | |
111 | { | |
112 | void __iomem *pio = pin_to_controller(pin); | |
113 | unsigned mask = pin_to_mask(pin); | |
114 | ||
115 | if (!pio) | |
116 | return -EINVAL; | |
117 | __raw_writel(mask, pio + PIO_IDR); | |
118 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
119 | __raw_writel(mask, pio + PIO_PER); | |
120 | return 0; | |
121 | } | |
122 | EXPORT_SYMBOL(at91_set_GPIO_periph); | |
123 | ||
124 | ||
73a59c1c SP |
125 | /* |
126 | * mux the pin to the "A" internal peripheral role. | |
127 | */ | |
128 | int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup) | |
129 | { | |
130 | void __iomem *pio = pin_to_controller(pin); | |
131 | unsigned mask = pin_to_mask(pin); | |
132 | ||
133 | if (!pio) | |
134 | return -EINVAL; | |
135 | ||
136 | __raw_writel(mask, pio + PIO_IDR); | |
137 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
138 | __raw_writel(mask, pio + PIO_ASR); | |
139 | __raw_writel(mask, pio + PIO_PDR); | |
140 | return 0; | |
141 | } | |
142 | EXPORT_SYMBOL(at91_set_A_periph); | |
143 | ||
144 | ||
145 | /* | |
146 | * mux the pin to the "B" internal peripheral role. | |
147 | */ | |
148 | int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup) | |
149 | { | |
150 | void __iomem *pio = pin_to_controller(pin); | |
151 | unsigned mask = pin_to_mask(pin); | |
152 | ||
153 | if (!pio) | |
154 | return -EINVAL; | |
155 | ||
156 | __raw_writel(mask, pio + PIO_IDR); | |
157 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
158 | __raw_writel(mask, pio + PIO_BSR); | |
159 | __raw_writel(mask, pio + PIO_PDR); | |
160 | return 0; | |
161 | } | |
162 | EXPORT_SYMBOL(at91_set_B_periph); | |
163 | ||
164 | ||
165 | /* | |
166 | * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and | |
167 | * configure it for an input. | |
168 | */ | |
169 | int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup) | |
170 | { | |
171 | void __iomem *pio = pin_to_controller(pin); | |
172 | unsigned mask = pin_to_mask(pin); | |
173 | ||
174 | if (!pio) | |
175 | return -EINVAL; | |
176 | ||
177 | __raw_writel(mask, pio + PIO_IDR); | |
178 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
179 | __raw_writel(mask, pio + PIO_ODR); | |
180 | __raw_writel(mask, pio + PIO_PER); | |
181 | return 0; | |
182 | } | |
183 | EXPORT_SYMBOL(at91_set_gpio_input); | |
184 | ||
185 | ||
186 | /* | |
187 | * mux the pin to the gpio controller (instead of "A" or "B" peripheral), | |
188 | * and configure it for an output. | |
189 | */ | |
190 | int __init_or_module at91_set_gpio_output(unsigned pin, int value) | |
191 | { | |
192 | void __iomem *pio = pin_to_controller(pin); | |
193 | unsigned mask = pin_to_mask(pin); | |
194 | ||
195 | if (!pio) | |
196 | return -EINVAL; | |
197 | ||
198 | __raw_writel(mask, pio + PIO_IDR); | |
199 | __raw_writel(mask, pio + PIO_PUDR); | |
200 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); | |
201 | __raw_writel(mask, pio + PIO_OER); | |
202 | __raw_writel(mask, pio + PIO_PER); | |
203 | return 0; | |
204 | } | |
205 | EXPORT_SYMBOL(at91_set_gpio_output); | |
206 | ||
207 | ||
208 | /* | |
209 | * enable/disable the glitch filter; mostly used with IRQ handling. | |
210 | */ | |
211 | int __init_or_module at91_set_deglitch(unsigned pin, int is_on) | |
212 | { | |
213 | void __iomem *pio = pin_to_controller(pin); | |
214 | unsigned mask = pin_to_mask(pin); | |
215 | ||
216 | if (!pio) | |
217 | return -EINVAL; | |
218 | __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); | |
219 | return 0; | |
220 | } | |
221 | EXPORT_SYMBOL(at91_set_deglitch); | |
222 | ||
df666b9c AV |
223 | /* |
224 | * enable/disable the multi-driver; This is only valid for output and | |
225 | * allows the output pin to run as an open collector output. | |
226 | */ | |
227 | int __init_or_module at91_set_multi_drive(unsigned pin, int is_on) | |
228 | { | |
229 | void __iomem *pio = pin_to_controller(pin); | |
230 | unsigned mask = pin_to_mask(pin); | |
231 | ||
232 | if (!pio) | |
233 | return -EINVAL; | |
234 | ||
235 | __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR)); | |
236 | return 0; | |
237 | } | |
238 | EXPORT_SYMBOL(at91_set_multi_drive); | |
239 | ||
73a59c1c SP |
240 | /* |
241 | * assuming the pin is muxed as a gpio output, set its value. | |
242 | */ | |
243 | int at91_set_gpio_value(unsigned pin, int value) | |
244 | { | |
245 | void __iomem *pio = pin_to_controller(pin); | |
246 | unsigned mask = pin_to_mask(pin); | |
247 | ||
248 | if (!pio) | |
249 | return -EINVAL; | |
250 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); | |
251 | return 0; | |
252 | } | |
253 | EXPORT_SYMBOL(at91_set_gpio_value); | |
254 | ||
255 | ||
256 | /* | |
257 | * read the pin's value (works even if it's not muxed as a gpio). | |
258 | */ | |
259 | int at91_get_gpio_value(unsigned pin) | |
260 | { | |
261 | void __iomem *pio = pin_to_controller(pin); | |
262 | unsigned mask = pin_to_mask(pin); | |
263 | u32 pdsr; | |
264 | ||
265 | if (!pio) | |
266 | return -EINVAL; | |
267 | pdsr = __raw_readl(pio + PIO_PDSR); | |
268 | return (pdsr & mask) != 0; | |
269 | } | |
270 | EXPORT_SYMBOL(at91_get_gpio_value); | |
271 | ||
272 | /*--------------------------------------------------------------------------*/ | |
273 | ||
814138ff AV |
274 | #ifdef CONFIG_PM |
275 | ||
f2173834 AV |
276 | static u32 wakeups[MAX_GPIO_BANKS]; |
277 | static u32 backups[MAX_GPIO_BANKS]; | |
814138ff | 278 | |
da0f9403 | 279 | static int gpio_irq_set_wake(struct irq_data *d, unsigned state) |
814138ff | 280 | { |
21f81872 NF |
281 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); |
282 | unsigned mask = 1 << d->hwirq; | |
283 | unsigned bank = at91_gpio->pioc_idx; | |
814138ff | 284 | |
3ea163e4 | 285 | if (unlikely(bank >= MAX_GPIO_BANKS)) |
814138ff AV |
286 | return -EINVAL; |
287 | ||
288 | if (state) | |
3ea163e4 | 289 | wakeups[bank] |= mask; |
814138ff | 290 | else |
3ea163e4 AV |
291 | wakeups[bank] &= ~mask; |
292 | ||
4340cde5 | 293 | irq_set_irq_wake(gpio_chip[bank].pioc_hwirq, state); |
814138ff AV |
294 | |
295 | return 0; | |
296 | } | |
297 | ||
298 | void at91_gpio_suspend(void) | |
299 | { | |
300 | int i; | |
301 | ||
f2173834 | 302 | for (i = 0; i < gpio_banks; i++) { |
f373e8c0 | 303 | void __iomem *pio = gpio_chip[i].regbase; |
814138ff | 304 | |
e83aff58 DB |
305 | backups[i] = __raw_readl(pio + PIO_IMR); |
306 | __raw_writel(backups[i], pio + PIO_IDR); | |
307 | __raw_writel(wakeups[i], pio + PIO_IER); | |
814138ff | 308 | |
21f81872 NF |
309 | if (!wakeups[i]) { |
310 | clk_unprepare(gpio_chip[i].clock); | |
619d4a4b | 311 | clk_disable(gpio_chip[i].clock); |
21f81872 | 312 | } else { |
814138ff | 313 | #ifdef CONFIG_PM_DEBUG |
3ea163e4 | 314 | printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); |
814138ff AV |
315 | #endif |
316 | } | |
317 | } | |
318 | } | |
319 | ||
320 | void at91_gpio_resume(void) | |
321 | { | |
322 | int i; | |
323 | ||
f2173834 | 324 | for (i = 0; i < gpio_banks; i++) { |
f373e8c0 | 325 | void __iomem *pio = gpio_chip[i].regbase; |
814138ff | 326 | |
21f81872 NF |
327 | if (!wakeups[i]) { |
328 | if (clk_prepare(gpio_chip[i].clock) == 0) | |
329 | clk_enable(gpio_chip[i].clock); | |
330 | } | |
3ea163e4 | 331 | |
e83aff58 DB |
332 | __raw_writel(wakeups[i], pio + PIO_IDR); |
333 | __raw_writel(backups[i], pio + PIO_IER); | |
f2173834 | 334 | } |
814138ff AV |
335 | } |
336 | ||
337 | #else | |
338 | #define gpio_irq_set_wake NULL | |
339 | #endif | |
340 | ||
73a59c1c SP |
341 | |
342 | /* Several AIC controller irqs are dispatched through this GPIO handler. | |
343 | * To use any AT91_PIN_* as an externally triggered IRQ, first call | |
344 | * at91_set_gpio_input() then maybe enable its glitch filter. | |
345 | * Then just request_irq() with the pin ID; it works like any ARM IRQ | |
346 | * handler, though it always triggers on rising and falling edges. | |
347 | * | |
348 | * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after | |
349 | * configuring them with at91_set_a_periph() or at91_set_b_periph(). | |
350 | * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. | |
351 | */ | |
352 | ||
da0f9403 | 353 | static void gpio_irq_mask(struct irq_data *d) |
73a59c1c | 354 | { |
21f81872 NF |
355 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); |
356 | void __iomem *pio = at91_gpio->regbase; | |
357 | unsigned mask = 1 << d->hwirq; | |
73a59c1c SP |
358 | |
359 | if (pio) | |
360 | __raw_writel(mask, pio + PIO_IDR); | |
361 | } | |
362 | ||
da0f9403 | 363 | static void gpio_irq_unmask(struct irq_data *d) |
73a59c1c | 364 | { |
21f81872 NF |
365 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); |
366 | void __iomem *pio = at91_gpio->regbase; | |
367 | unsigned mask = 1 << d->hwirq; | |
73a59c1c SP |
368 | |
369 | if (pio) | |
370 | __raw_writel(mask, pio + PIO_IER); | |
371 | } | |
372 | ||
da0f9403 | 373 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
73a59c1c | 374 | { |
e83aff58 DB |
375 | switch (type) { |
376 | case IRQ_TYPE_NONE: | |
377 | case IRQ_TYPE_EDGE_BOTH: | |
378 | return 0; | |
379 | default: | |
380 | return -EINVAL; | |
381 | } | |
73a59c1c SP |
382 | } |
383 | ||
38c677cb DB |
384 | static struct irq_chip gpio_irqchip = { |
385 | .name = "GPIO", | |
ac93cdbd | 386 | .irq_disable = gpio_irq_mask, |
da0f9403 LB |
387 | .irq_mask = gpio_irq_mask, |
388 | .irq_unmask = gpio_irq_unmask, | |
389 | .irq_set_type = gpio_irq_type, | |
390 | .irq_set_wake = gpio_irq_set_wake, | |
73a59c1c SP |
391 | }; |
392 | ||
10dd5ce2 | 393 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
73a59c1c | 394 | { |
21f81872 | 395 | unsigned virq; |
ac93cdbd TG |
396 | struct irq_data *idata = irq_desc_get_irq_data(desc); |
397 | struct irq_chip *chip = irq_data_get_irq_chip(idata); | |
398 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); | |
399 | void __iomem *pio = at91_gpio->regbase; | |
73a59c1c SP |
400 | u32 isr; |
401 | ||
73a59c1c | 402 | /* temporarily mask (level sensitive) parent IRQ */ |
ac93cdbd | 403 | chip->irq_ack(idata); |
73a59c1c | 404 | for (;;) { |
e83aff58 DB |
405 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. |
406 | * When there none are pending, we're finished unless we need | |
407 | * to process multiple banks (like ID_PIOCDE on sam9263). | |
408 | */ | |
73a59c1c | 409 | isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); |
e83aff58 | 410 | if (!isr) { |
f373e8c0 | 411 | if (!at91_gpio->next) |
e83aff58 | 412 | break; |
f373e8c0 RM |
413 | at91_gpio = at91_gpio->next; |
414 | pio = at91_gpio->regbase; | |
e83aff58 DB |
415 | continue; |
416 | } | |
73a59c1c | 417 | |
21f81872 | 418 | virq = gpio_to_irq(at91_gpio->chip.base); |
73a59c1c SP |
419 | |
420 | while (isr) { | |
ac93cdbd | 421 | if (isr & 1) |
21f81872 NF |
422 | generic_handle_irq(virq); |
423 | virq++; | |
73a59c1c SP |
424 | isr >>= 1; |
425 | } | |
426 | } | |
ac93cdbd | 427 | chip->irq_unmask(idata); |
73a59c1c SP |
428 | /* now it may re-trigger */ |
429 | } | |
430 | ||
f2173834 AV |
431 | /*--------------------------------------------------------------------------*/ |
432 | ||
b66545e7 AV |
433 | #ifdef CONFIG_DEBUG_FS |
434 | ||
435 | static int at91_gpio_show(struct seq_file *s, void *unused) | |
436 | { | |
437 | int bank, j; | |
438 | ||
439 | /* print heading */ | |
440 | seq_printf(s, "Pin\t"); | |
441 | for (bank = 0; bank < gpio_banks; bank++) { | |
442 | seq_printf(s, "PIO%c\t", 'A' + bank); | |
443 | }; | |
444 | seq_printf(s, "\n\n"); | |
445 | ||
446 | /* print pin status */ | |
447 | for (j = 0; j < 32; j++) { | |
448 | seq_printf(s, "%i:\t", j); | |
449 | ||
450 | for (bank = 0; bank < gpio_banks; bank++) { | |
d0fbda9a | 451 | unsigned pin = (32 * bank) + j; |
b66545e7 AV |
452 | void __iomem *pio = pin_to_controller(pin); |
453 | unsigned mask = pin_to_mask(pin); | |
454 | ||
455 | if (__raw_readl(pio + PIO_PSR) & mask) | |
456 | seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0"); | |
457 | else | |
458 | seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A"); | |
459 | ||
460 | seq_printf(s, "\t"); | |
461 | } | |
462 | ||
463 | seq_printf(s, "\n"); | |
464 | } | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
469 | static int at91_gpio_open(struct inode *inode, struct file *file) | |
470 | { | |
471 | return single_open(file, at91_gpio_show, NULL); | |
472 | } | |
473 | ||
474 | static const struct file_operations at91_gpio_operations = { | |
475 | .open = at91_gpio_open, | |
476 | .read = seq_read, | |
477 | .llseek = seq_lseek, | |
478 | .release = single_release, | |
479 | }; | |
480 | ||
481 | static int __init at91_gpio_debugfs_init(void) | |
482 | { | |
483 | /* /sys/kernel/debug/at91_gpio */ | |
484 | (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations); | |
485 | return 0; | |
486 | } | |
487 | postcore_initcall(at91_gpio_debugfs_init); | |
488 | ||
489 | #endif | |
490 | ||
491 | /*--------------------------------------------------------------------------*/ | |
492 | ||
21f81872 NF |
493 | /* |
494 | * irqdomain initialization: pile up irqdomains on top of AIC range | |
495 | */ | |
496 | static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio) | |
497 | { | |
498 | int irq_base; | |
5bc067b7 NF |
499 | #if defined(CONFIG_OF) |
500 | struct device_node *of_node = at91_gpio->chip.of_node; | |
501 | #else | |
502 | struct device_node *of_node = NULL; | |
503 | #endif | |
21f81872 NF |
504 | |
505 | irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0); | |
506 | if (irq_base < 0) | |
507 | panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n", | |
508 | at91_gpio->pioc_idx, irq_base); | |
5bc067b7 | 509 | at91_gpio->domain = irq_domain_add_legacy(of_node, |
21f81872 NF |
510 | at91_gpio->chip.ngpio, |
511 | irq_base, 0, | |
512 | &irq_domain_simple_ops, NULL); | |
513 | if (!at91_gpio->domain) | |
514 | panic("at91_gpio.%d: couldn't allocate irq domain.\n", | |
515 | at91_gpio->pioc_idx); | |
516 | } | |
517 | ||
2b768b6c AV |
518 | /* |
519 | * This lock class tells lockdep that GPIO irqs are in a different | |
37aca70c DB |
520 | * category than their parents, so it won't report false recursion. |
521 | */ | |
522 | static struct lock_class_key gpio_lock_class; | |
523 | ||
f2173834 AV |
524 | /* |
525 | * Called from the processor-specific init to enable GPIO interrupt support. | |
526 | */ | |
527 | void __init at91_gpio_irq_setup(void) | |
73a59c1c | 528 | { |
21f81872 NF |
529 | unsigned pioc; |
530 | int gpio_irqnbr = 0; | |
f373e8c0 | 531 | struct at91_gpio_chip *this, *prev; |
73a59c1c | 532 | |
d0fbda9a | 533 | for (pioc = 0, this = gpio_chip, prev = NULL; |
e83aff58 DB |
534 | pioc++ < gpio_banks; |
535 | prev = this, this++) { | |
4340cde5 | 536 | unsigned pioc_hwirq = this->pioc_hwirq; |
21f81872 | 537 | int offset; |
73a59c1c | 538 | |
e83aff58 | 539 | __raw_writel(~0, this->regbase + PIO_IDR); |
73a59c1c | 540 | |
21f81872 NF |
541 | /* setup irq domain for this GPIO controller */ |
542 | at91_gpio_irqdomain(this); | |
543 | ||
544 | for (offset = 0; offset < this->chip.ngpio; offset++) { | |
545 | unsigned int virq = irq_find_mapping(this->domain, offset); | |
546 | irq_set_lockdep_class(virq, &gpio_lock_class); | |
37aca70c | 547 | |
814138ff AV |
548 | /* |
549 | * Can use the "simple" and not "edge" handler since it's | |
3a4fa0a2 | 550 | * shorter, and the AIC handles interrupts sanely. |
814138ff | 551 | */ |
21f81872 | 552 | irq_set_chip_and_handler(virq, &gpio_irqchip, |
f38c02f3 | 553 | handle_simple_irq); |
21f81872 NF |
554 | set_irq_flags(virq, IRQF_VALID); |
555 | irq_set_chip_data(virq, this); | |
556 | ||
557 | gpio_irqnbr++; | |
73a59c1c SP |
558 | } |
559 | ||
e83aff58 | 560 | /* The toplevel handler handles one bank of GPIOs, except |
4340cde5 NF |
561 | * on some SoC it can handles up to three... |
562 | * We only set up the handler for the first of the list. | |
e83aff58 DB |
563 | */ |
564 | if (prev && prev->next == this) | |
565 | continue; | |
566 | ||
4340cde5 NF |
567 | irq_set_chip_data(pioc_hwirq, this); |
568 | irq_set_chained_handler(pioc_hwirq, gpio_irq_handler); | |
73a59c1c | 569 | } |
21f81872 | 570 | pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks); |
f2173834 AV |
571 | } |
572 | ||
f373e8c0 RM |
573 | /* gpiolib support */ |
574 | static int at91_gpiolib_direction_input(struct gpio_chip *chip, | |
575 | unsigned offset) | |
576 | { | |
577 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
578 | void __iomem *pio = at91_gpio->regbase; | |
579 | unsigned mask = 1 << offset; | |
580 | ||
581 | __raw_writel(mask, pio + PIO_ODR); | |
582 | return 0; | |
583 | } | |
584 | ||
585 | static int at91_gpiolib_direction_output(struct gpio_chip *chip, | |
586 | unsigned offset, int val) | |
587 | { | |
588 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
589 | void __iomem *pio = at91_gpio->regbase; | |
590 | unsigned mask = 1 << offset; | |
591 | ||
592 | __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
593 | __raw_writel(mask, pio + PIO_OER); | |
594 | return 0; | |
595 | } | |
596 | ||
597 | static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset) | |
598 | { | |
599 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
600 | void __iomem *pio = at91_gpio->regbase; | |
601 | unsigned mask = 1 << offset; | |
602 | u32 pdsr; | |
603 | ||
604 | pdsr = __raw_readl(pio + PIO_PDSR); | |
605 | return (pdsr & mask) != 0; | |
606 | } | |
607 | ||
608 | static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val) | |
609 | { | |
610 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
611 | void __iomem *pio = at91_gpio->regbase; | |
612 | unsigned mask = 1 << offset; | |
613 | ||
614 | __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
615 | } | |
616 | ||
f373e8c0 RM |
617 | static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
618 | { | |
619 | int i; | |
620 | ||
621 | for (i = 0; i < chip->ngpio; i++) { | |
622 | unsigned pin = chip->base + i; | |
623 | void __iomem *pio = pin_to_controller(pin); | |
624 | unsigned mask = pin_to_mask(pin); | |
625 | const char *gpio_label; | |
626 | ||
627 | gpio_label = gpiochip_is_requested(chip, i); | |
628 | if (gpio_label) { | |
629 | seq_printf(s, "[%s] GPIO%s%d: ", | |
630 | gpio_label, chip->label, i); | |
631 | if (__raw_readl(pio + PIO_PSR) & mask) | |
632 | seq_printf(s, "[gpio] %s\n", | |
633 | at91_get_gpio_value(pin) ? | |
634 | "set" : "clear"); | |
635 | else | |
636 | seq_printf(s, "[periph %s]\n", | |
637 | __raw_readl(pio + PIO_ABSR) & | |
638 | mask ? "B" : "A"); | |
639 | } | |
640 | } | |
641 | } | |
642 | ||
21f81872 NF |
643 | static int __init at91_gpio_setup_clk(int idx) |
644 | { | |
645 | struct at91_gpio_chip *at91_gpio = &gpio_chip[idx]; | |
646 | ||
647 | /* retreive PIO controller's clock */ | |
648 | at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label); | |
649 | if (IS_ERR(at91_gpio->clock)) { | |
650 | pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx); | |
651 | goto err; | |
652 | } | |
653 | ||
654 | if (clk_prepare(at91_gpio->clock)) | |
655 | goto clk_prep_err; | |
656 | ||
657 | /* enable PIO controller's clock */ | |
658 | if (clk_enable(at91_gpio->clock)) { | |
659 | pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx); | |
660 | goto clk_err; | |
661 | } | |
662 | ||
663 | return 0; | |
664 | ||
665 | clk_err: | |
666 | clk_unprepare(at91_gpio->clock); | |
667 | clk_prep_err: | |
668 | clk_put(at91_gpio->clock); | |
669 | err: | |
670 | return -EINVAL; | |
671 | } | |
672 | ||
673 | #ifdef CONFIG_OF_GPIO | |
674 | static void __init of_at91_gpio_init_one(struct device_node *np) | |
675 | { | |
676 | int alias_idx; | |
677 | struct at91_gpio_chip *at91_gpio; | |
678 | ||
679 | if (!np) | |
680 | return; | |
681 | ||
682 | alias_idx = of_alias_get_id(np, "gpio"); | |
683 | if (alias_idx >= MAX_GPIO_BANKS) { | |
684 | pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n", | |
685 | alias_idx, MAX_GPIO_BANKS); | |
686 | return; | |
687 | } | |
688 | ||
689 | at91_gpio = &gpio_chip[alias_idx]; | |
690 | at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio; | |
691 | ||
692 | at91_gpio->regbase = of_iomap(np, 0); | |
693 | if (!at91_gpio->regbase) { | |
694 | pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", | |
695 | alias_idx); | |
696 | return; | |
697 | } | |
698 | ||
699 | /* Get the interrupts property */ | |
700 | if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) { | |
701 | pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n", | |
702 | alias_idx); | |
703 | goto ioremap_err; | |
704 | } | |
705 | ||
706 | /* Setup clock */ | |
707 | if (at91_gpio_setup_clk(alias_idx)) | |
708 | goto ioremap_err; | |
709 | ||
710 | at91_gpio->chip.of_node = np; | |
711 | gpio_banks = max(gpio_banks, alias_idx + 1); | |
712 | at91_gpio->pioc_idx = alias_idx; | |
713 | return; | |
714 | ||
715 | ioremap_err: | |
716 | iounmap(at91_gpio->regbase); | |
717 | } | |
718 | ||
719 | static int __init of_at91_gpio_init(void) | |
720 | { | |
721 | struct device_node *np = NULL; | |
722 | ||
723 | /* | |
724 | * This isn't ideal, but it gets things hooked up until this | |
725 | * driver is converted into a platform_device | |
726 | */ | |
727 | for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio") | |
728 | of_at91_gpio_init_one(np); | |
729 | ||
730 | return gpio_banks > 0 ? 0 : -EINVAL; | |
731 | } | |
732 | #else | |
733 | static int __init of_at91_gpio_init(void) | |
734 | { | |
735 | return -EINVAL; | |
736 | } | |
737 | #endif | |
738 | ||
739 | static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq) | |
740 | { | |
741 | struct at91_gpio_chip *at91_gpio = &gpio_chip[idx]; | |
742 | ||
743 | at91_gpio->chip.base = idx * at91_gpio->chip.ngpio; | |
744 | at91_gpio->pioc_hwirq = pioc_hwirq; | |
745 | at91_gpio->pioc_idx = idx; | |
746 | ||
747 | at91_gpio->regbase = ioremap(regbase, 512); | |
748 | if (!at91_gpio->regbase) { | |
749 | pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx); | |
750 | return; | |
751 | } | |
752 | ||
753 | if (at91_gpio_setup_clk(idx)) | |
754 | goto ioremap_err; | |
755 | ||
756 | gpio_banks = max(gpio_banks, idx + 1); | |
757 | return; | |
758 | ||
759 | ioremap_err: | |
760 | iounmap(at91_gpio->regbase); | |
761 | } | |
762 | ||
f2173834 AV |
763 | /* |
764 | * Called from the processor-specific init to enable GPIO pin support. | |
765 | */ | |
766 | void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) | |
767 | { | |
21f81872 | 768 | unsigned i; |
f373e8c0 | 769 | struct at91_gpio_chip *at91_gpio, *last = NULL; |
e83aff58 | 770 | |
f2173834 AV |
771 | BUG_ON(nr_banks > MAX_GPIO_BANKS); |
772 | ||
21f81872 NF |
773 | if (of_at91_gpio_init() < 0) { |
774 | /* No GPIO controller found in device tree */ | |
775 | for (i = 0; i < nr_banks; i++) | |
776 | at91_gpio_init_one(i, data[i].regbase, data[i].id); | |
777 | } | |
e83aff58 | 778 | |
21f81872 | 779 | for (i = 0; i < gpio_banks; i++) { |
f373e8c0 RM |
780 | at91_gpio = &gpio_chip[i]; |
781 | ||
4340cde5 NF |
782 | /* |
783 | * GPIO controller are grouped on some SoC: | |
784 | * PIOC, PIOD and PIOE can share the same IRQ line | |
785 | */ | |
786 | if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq) | |
f373e8c0 RM |
787 | last->next = at91_gpio; |
788 | last = at91_gpio; | |
789 | ||
790 | gpiochip_add(&at91_gpio->chip); | |
e83aff58 | 791 | } |
73a59c1c | 792 | } |