Commit | Line | Data |
---|---|---|
73a59c1c | 1 | /* |
9d041268 | 2 | * linux/arch/arm/mach-at91/gpio.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2005 HP Labs | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
f2173834 | 12 | #include <linux/clk.h> |
73a59c1c | 13 | #include <linux/errno.h> |
b134ce85 | 14 | #include <linux/device.h> |
2f8163ba | 15 | #include <linux/gpio.h> |
07d265dd TG |
16 | #include <linux/interrupt.h> |
17 | #include <linux/irq.h> | |
b66545e7 AV |
18 | #include <linux/debugfs.h> |
19 | #include <linux/seq_file.h> | |
73a59c1c SP |
20 | #include <linux/kernel.h> |
21 | #include <linux/list.h> | |
22 | #include <linux/module.h> | |
fced80c7 | 23 | #include <linux/io.h> |
21f81872 NF |
24 | #include <linux/irqdomain.h> |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
8014d6f4 | 27 | #include <linux/of_gpio.h> |
73a59c1c | 28 | |
42a859da LD |
29 | #include <asm/mach/irq.h> |
30 | ||
a09e64fb RK |
31 | #include <mach/hardware.h> |
32 | #include <mach/at91_pio.h> | |
73a59c1c | 33 | |
f2173834 AV |
34 | #include "generic.h" |
35 | ||
fc33ff43 JCPV |
36 | #define MAX_NB_GPIO_PER_BANK 32 |
37 | ||
f373e8c0 RM |
38 | struct at91_gpio_chip { |
39 | struct gpio_chip chip; | |
40 | struct at91_gpio_chip *next; /* Bank sharing same clock */ | |
4340cde5 | 41 | int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ |
8014d6f4 | 42 | int pioc_virq; /* PIO bank Linux virtual interrupt */ |
21f81872 | 43 | int pioc_idx; /* PIO bank index */ |
4340cde5 | 44 | void __iomem *regbase; /* PIO bank virtual address */ |
619d4a4b | 45 | struct clk *clock; /* associated clock */ |
21f81872 | 46 | struct irq_domain *domain; /* associated irq domain */ |
f373e8c0 | 47 | }; |
f2173834 | 48 | |
f373e8c0 RM |
49 | #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) |
50 | ||
c18486e1 | 51 | static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset); |
f373e8c0 RM |
52 | static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip); |
53 | static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val); | |
54 | static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset); | |
55 | static int at91_gpiolib_direction_output(struct gpio_chip *chip, | |
56 | unsigned offset, int val); | |
57 | static int at91_gpiolib_direction_input(struct gpio_chip *chip, | |
58 | unsigned offset); | |
b134ce85 | 59 | static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset); |
f373e8c0 | 60 | |
fc33ff43 | 61 | #define AT91_GPIO_CHIP(name) \ |
f373e8c0 RM |
62 | { \ |
63 | .chip = { \ | |
64 | .label = name, \ | |
c18486e1 | 65 | .request = at91_gpiolib_request, \ |
f373e8c0 RM |
66 | .direction_input = at91_gpiolib_direction_input, \ |
67 | .direction_output = at91_gpiolib_direction_output, \ | |
68 | .get = at91_gpiolib_get, \ | |
69 | .set = at91_gpiolib_set, \ | |
70 | .dbg_show = at91_gpiolib_dbg_show, \ | |
b134ce85 | 71 | .to_irq = at91_gpiolib_to_irq, \ |
fc33ff43 | 72 | .ngpio = MAX_NB_GPIO_PER_BANK, \ |
f373e8c0 RM |
73 | }, \ |
74 | } | |
f2173834 | 75 | |
f373e8c0 | 76 | static struct at91_gpio_chip gpio_chip[] = { |
fc33ff43 JCPV |
77 | AT91_GPIO_CHIP("pioA"), |
78 | AT91_GPIO_CHIP("pioB"), | |
79 | AT91_GPIO_CHIP("pioC"), | |
80 | AT91_GPIO_CHIP("pioD"), | |
81 | AT91_GPIO_CHIP("pioE"), | |
f373e8c0 RM |
82 | }; |
83 | ||
84 | static int gpio_banks; | |
582d5fbd NF |
85 | static unsigned long at91_gpio_caps; |
86 | ||
87 | /* All PIO controllers support PIO3 features */ | |
88 | #define AT91_GPIO_CAP_PIO3 (1 << 0) | |
89 | ||
90 | #define has_pio3() (at91_gpio_caps & AT91_GPIO_CAP_PIO3) | |
91 | ||
92 | /*--------------------------------------------------------------------------*/ | |
73a59c1c SP |
93 | |
94 | static inline void __iomem *pin_to_controller(unsigned pin) | |
95 | { | |
fc33ff43 | 96 | pin /= MAX_NB_GPIO_PER_BANK; |
f2173834 | 97 | if (likely(pin < gpio_banks)) |
f373e8c0 | 98 | return gpio_chip[pin].regbase; |
73a59c1c SP |
99 | |
100 | return NULL; | |
101 | } | |
102 | ||
103 | static inline unsigned pin_to_mask(unsigned pin) | |
104 | { | |
fc33ff43 | 105 | return 1 << (pin % MAX_NB_GPIO_PER_BANK); |
73a59c1c SP |
106 | } |
107 | ||
108 | ||
582d5fbd NF |
109 | static char peripheral_function(void __iomem *pio, unsigned mask) |
110 | { | |
111 | char ret = 'X'; | |
112 | u8 select; | |
113 | ||
114 | if (pio) { | |
115 | if (has_pio3()) { | |
116 | select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask); | |
117 | select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1); | |
118 | ret = 'A' + select; | |
119 | } else { | |
120 | ret = __raw_readl(pio + PIO_ABSR) & mask ? | |
121 | 'B' : 'A'; | |
122 | } | |
123 | } | |
124 | ||
125 | return ret; | |
126 | } | |
127 | ||
73a59c1c SP |
128 | /*--------------------------------------------------------------------------*/ |
129 | ||
130 | /* Not all hardware capabilities are exposed through these calls; they | |
131 | * only encapsulate the most common features and modes. (So if you | |
132 | * want to change signals in groups, do it directly.) | |
133 | * | |
134 | * Bootloaders will usually handle some of the pin multiplexing setup. | |
135 | * The intent is certainly that by the time Linux is fully booted, all | |
136 | * pins should have been fully initialized. These setup calls should | |
137 | * only be used by board setup routines, or possibly in driver probe(). | |
138 | * | |
139 | * For bootloaders doing all that setup, these calls could be inlined | |
140 | * as NOPs so Linux won't duplicate any setup code | |
141 | */ | |
142 | ||
143 | ||
a31c4eea DB |
144 | /* |
145 | * mux the pin to the "GPIO" peripheral role. | |
146 | */ | |
147 | int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup) | |
148 | { | |
149 | void __iomem *pio = pin_to_controller(pin); | |
150 | unsigned mask = pin_to_mask(pin); | |
151 | ||
152 | if (!pio) | |
153 | return -EINVAL; | |
154 | __raw_writel(mask, pio + PIO_IDR); | |
155 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
156 | __raw_writel(mask, pio + PIO_PER); | |
157 | return 0; | |
158 | } | |
159 | EXPORT_SYMBOL(at91_set_GPIO_periph); | |
160 | ||
161 | ||
73a59c1c SP |
162 | /* |
163 | * mux the pin to the "A" internal peripheral role. | |
164 | */ | |
165 | int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup) | |
166 | { | |
167 | void __iomem *pio = pin_to_controller(pin); | |
168 | unsigned mask = pin_to_mask(pin); | |
169 | ||
170 | if (!pio) | |
171 | return -EINVAL; | |
172 | ||
173 | __raw_writel(mask, pio + PIO_IDR); | |
174 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
582d5fbd NF |
175 | if (has_pio3()) { |
176 | __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, | |
177 | pio + PIO_ABCDSR1); | |
178 | __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask, | |
179 | pio + PIO_ABCDSR2); | |
180 | } else { | |
181 | __raw_writel(mask, pio + PIO_ASR); | |
182 | } | |
73a59c1c SP |
183 | __raw_writel(mask, pio + PIO_PDR); |
184 | return 0; | |
185 | } | |
186 | EXPORT_SYMBOL(at91_set_A_periph); | |
187 | ||
188 | ||
189 | /* | |
190 | * mux the pin to the "B" internal peripheral role. | |
191 | */ | |
192 | int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup) | |
193 | { | |
194 | void __iomem *pio = pin_to_controller(pin); | |
195 | unsigned mask = pin_to_mask(pin); | |
196 | ||
197 | if (!pio) | |
198 | return -EINVAL; | |
199 | ||
200 | __raw_writel(mask, pio + PIO_IDR); | |
201 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
582d5fbd NF |
202 | if (has_pio3()) { |
203 | __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, | |
204 | pio + PIO_ABCDSR1); | |
205 | __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask, | |
206 | pio + PIO_ABCDSR2); | |
207 | } else { | |
208 | __raw_writel(mask, pio + PIO_BSR); | |
209 | } | |
73a59c1c SP |
210 | __raw_writel(mask, pio + PIO_PDR); |
211 | return 0; | |
212 | } | |
213 | EXPORT_SYMBOL(at91_set_B_periph); | |
214 | ||
215 | ||
216 | /* | |
582d5fbd NF |
217 | * mux the pin to the "C" internal peripheral role. |
218 | */ | |
219 | int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup) | |
220 | { | |
221 | void __iomem *pio = pin_to_controller(pin); | |
222 | unsigned mask = pin_to_mask(pin); | |
223 | ||
224 | if (!pio || !has_pio3()) | |
225 | return -EINVAL; | |
226 | ||
227 | __raw_writel(mask, pio + PIO_IDR); | |
228 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
229 | __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); | |
230 | __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
231 | __raw_writel(mask, pio + PIO_PDR); | |
232 | return 0; | |
233 | } | |
234 | EXPORT_SYMBOL(at91_set_C_periph); | |
235 | ||
236 | ||
237 | /* | |
238 | * mux the pin to the "D" internal peripheral role. | |
239 | */ | |
240 | int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup) | |
241 | { | |
242 | void __iomem *pio = pin_to_controller(pin); | |
243 | unsigned mask = pin_to_mask(pin); | |
244 | ||
245 | if (!pio || !has_pio3()) | |
246 | return -EINVAL; | |
247 | ||
248 | __raw_writel(mask, pio + PIO_IDR); | |
249 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
250 | __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); | |
251 | __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
252 | __raw_writel(mask, pio + PIO_PDR); | |
253 | return 0; | |
254 | } | |
255 | EXPORT_SYMBOL(at91_set_D_periph); | |
256 | ||
257 | ||
258 | /* | |
259 | * mux the pin to the gpio controller (instead of "A", "B", "C" | |
260 | * or "D" peripheral), and configure it for an input. | |
73a59c1c SP |
261 | */ |
262 | int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup) | |
263 | { | |
264 | void __iomem *pio = pin_to_controller(pin); | |
265 | unsigned mask = pin_to_mask(pin); | |
266 | ||
267 | if (!pio) | |
268 | return -EINVAL; | |
269 | ||
270 | __raw_writel(mask, pio + PIO_IDR); | |
271 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
272 | __raw_writel(mask, pio + PIO_ODR); | |
273 | __raw_writel(mask, pio + PIO_PER); | |
274 | return 0; | |
275 | } | |
276 | EXPORT_SYMBOL(at91_set_gpio_input); | |
277 | ||
278 | ||
279 | /* | |
582d5fbd NF |
280 | * mux the pin to the gpio controller (instead of "A", "B", "C" |
281 | * or "D" peripheral), and configure it for an output. | |
73a59c1c SP |
282 | */ |
283 | int __init_or_module at91_set_gpio_output(unsigned pin, int value) | |
284 | { | |
285 | void __iomem *pio = pin_to_controller(pin); | |
286 | unsigned mask = pin_to_mask(pin); | |
287 | ||
288 | if (!pio) | |
289 | return -EINVAL; | |
290 | ||
291 | __raw_writel(mask, pio + PIO_IDR); | |
292 | __raw_writel(mask, pio + PIO_PUDR); | |
293 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); | |
294 | __raw_writel(mask, pio + PIO_OER); | |
295 | __raw_writel(mask, pio + PIO_PER); | |
296 | return 0; | |
297 | } | |
298 | EXPORT_SYMBOL(at91_set_gpio_output); | |
299 | ||
300 | ||
301 | /* | |
302 | * enable/disable the glitch filter; mostly used with IRQ handling. | |
303 | */ | |
304 | int __init_or_module at91_set_deglitch(unsigned pin, int is_on) | |
305 | { | |
306 | void __iomem *pio = pin_to_controller(pin); | |
307 | unsigned mask = pin_to_mask(pin); | |
308 | ||
309 | if (!pio) | |
310 | return -EINVAL; | |
582d5fbd NF |
311 | |
312 | if (has_pio3() && is_on) | |
313 | __raw_writel(mask, pio + PIO_IFSCDR); | |
73a59c1c SP |
314 | __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); |
315 | return 0; | |
316 | } | |
317 | EXPORT_SYMBOL(at91_set_deglitch); | |
318 | ||
582d5fbd NF |
319 | /* |
320 | * enable/disable the debounce filter; | |
321 | */ | |
322 | int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div) | |
323 | { | |
324 | void __iomem *pio = pin_to_controller(pin); | |
325 | unsigned mask = pin_to_mask(pin); | |
326 | ||
327 | if (!pio || !has_pio3()) | |
328 | return -EINVAL; | |
329 | ||
330 | if (is_on) { | |
331 | __raw_writel(mask, pio + PIO_IFSCER); | |
332 | __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); | |
333 | __raw_writel(mask, pio + PIO_IFER); | |
334 | } else { | |
335 | __raw_writel(mask, pio + PIO_IFDR); | |
336 | } | |
337 | return 0; | |
338 | } | |
339 | EXPORT_SYMBOL(at91_set_debounce); | |
340 | ||
df666b9c AV |
341 | /* |
342 | * enable/disable the multi-driver; This is only valid for output and | |
343 | * allows the output pin to run as an open collector output. | |
344 | */ | |
345 | int __init_or_module at91_set_multi_drive(unsigned pin, int is_on) | |
346 | { | |
347 | void __iomem *pio = pin_to_controller(pin); | |
348 | unsigned mask = pin_to_mask(pin); | |
349 | ||
350 | if (!pio) | |
351 | return -EINVAL; | |
352 | ||
353 | __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR)); | |
354 | return 0; | |
355 | } | |
356 | EXPORT_SYMBOL(at91_set_multi_drive); | |
357 | ||
582d5fbd NF |
358 | /* |
359 | * enable/disable the pull-down. | |
360 | * If pull-up already enabled while calling the function, we disable it. | |
361 | */ | |
362 | int __init_or_module at91_set_pulldown(unsigned pin, int is_on) | |
363 | { | |
364 | void __iomem *pio = pin_to_controller(pin); | |
365 | unsigned mask = pin_to_mask(pin); | |
366 | ||
367 | if (!pio || !has_pio3()) | |
368 | return -EINVAL; | |
369 | ||
370 | /* Disable pull-up anyway */ | |
371 | __raw_writel(mask, pio + PIO_PUDR); | |
372 | __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); | |
373 | return 0; | |
374 | } | |
375 | EXPORT_SYMBOL(at91_set_pulldown); | |
376 | ||
377 | /* | |
378 | * disable Schmitt trigger | |
379 | */ | |
380 | int __init_or_module at91_disable_schmitt_trig(unsigned pin) | |
381 | { | |
382 | void __iomem *pio = pin_to_controller(pin); | |
383 | unsigned mask = pin_to_mask(pin); | |
384 | ||
385 | if (!pio || !has_pio3()) | |
386 | return -EINVAL; | |
387 | ||
388 | __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); | |
389 | return 0; | |
390 | } | |
391 | EXPORT_SYMBOL(at91_disable_schmitt_trig); | |
392 | ||
73a59c1c SP |
393 | /* |
394 | * assuming the pin is muxed as a gpio output, set its value. | |
395 | */ | |
396 | int at91_set_gpio_value(unsigned pin, int value) | |
397 | { | |
398 | void __iomem *pio = pin_to_controller(pin); | |
399 | unsigned mask = pin_to_mask(pin); | |
400 | ||
401 | if (!pio) | |
402 | return -EINVAL; | |
403 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); | |
404 | return 0; | |
405 | } | |
406 | EXPORT_SYMBOL(at91_set_gpio_value); | |
407 | ||
408 | ||
409 | /* | |
410 | * read the pin's value (works even if it's not muxed as a gpio). | |
411 | */ | |
412 | int at91_get_gpio_value(unsigned pin) | |
413 | { | |
414 | void __iomem *pio = pin_to_controller(pin); | |
415 | unsigned mask = pin_to_mask(pin); | |
416 | u32 pdsr; | |
417 | ||
418 | if (!pio) | |
419 | return -EINVAL; | |
420 | pdsr = __raw_readl(pio + PIO_PDSR); | |
421 | return (pdsr & mask) != 0; | |
422 | } | |
423 | EXPORT_SYMBOL(at91_get_gpio_value); | |
424 | ||
425 | /*--------------------------------------------------------------------------*/ | |
426 | ||
814138ff AV |
427 | #ifdef CONFIG_PM |
428 | ||
f2173834 AV |
429 | static u32 wakeups[MAX_GPIO_BANKS]; |
430 | static u32 backups[MAX_GPIO_BANKS]; | |
814138ff | 431 | |
da0f9403 | 432 | static int gpio_irq_set_wake(struct irq_data *d, unsigned state) |
814138ff | 433 | { |
21f81872 NF |
434 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); |
435 | unsigned mask = 1 << d->hwirq; | |
436 | unsigned bank = at91_gpio->pioc_idx; | |
814138ff | 437 | |
3ea163e4 | 438 | if (unlikely(bank >= MAX_GPIO_BANKS)) |
814138ff AV |
439 | return -EINVAL; |
440 | ||
441 | if (state) | |
3ea163e4 | 442 | wakeups[bank] |= mask; |
814138ff | 443 | else |
3ea163e4 AV |
444 | wakeups[bank] &= ~mask; |
445 | ||
8014d6f4 | 446 | irq_set_irq_wake(at91_gpio->pioc_virq, state); |
814138ff AV |
447 | |
448 | return 0; | |
449 | } | |
450 | ||
451 | void at91_gpio_suspend(void) | |
452 | { | |
453 | int i; | |
454 | ||
f2173834 | 455 | for (i = 0; i < gpio_banks; i++) { |
f373e8c0 | 456 | void __iomem *pio = gpio_chip[i].regbase; |
814138ff | 457 | |
e83aff58 DB |
458 | backups[i] = __raw_readl(pio + PIO_IMR); |
459 | __raw_writel(backups[i], pio + PIO_IDR); | |
460 | __raw_writel(wakeups[i], pio + PIO_IER); | |
814138ff | 461 | |
21f81872 NF |
462 | if (!wakeups[i]) { |
463 | clk_unprepare(gpio_chip[i].clock); | |
619d4a4b | 464 | clk_disable(gpio_chip[i].clock); |
21f81872 | 465 | } else { |
814138ff | 466 | #ifdef CONFIG_PM_DEBUG |
3ea163e4 | 467 | printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); |
814138ff AV |
468 | #endif |
469 | } | |
470 | } | |
471 | } | |
472 | ||
473 | void at91_gpio_resume(void) | |
474 | { | |
475 | int i; | |
476 | ||
f2173834 | 477 | for (i = 0; i < gpio_banks; i++) { |
f373e8c0 | 478 | void __iomem *pio = gpio_chip[i].regbase; |
814138ff | 479 | |
21f81872 NF |
480 | if (!wakeups[i]) { |
481 | if (clk_prepare(gpio_chip[i].clock) == 0) | |
482 | clk_enable(gpio_chip[i].clock); | |
483 | } | |
3ea163e4 | 484 | |
e83aff58 DB |
485 | __raw_writel(wakeups[i], pio + PIO_IDR); |
486 | __raw_writel(backups[i], pio + PIO_IER); | |
f2173834 | 487 | } |
814138ff AV |
488 | } |
489 | ||
490 | #else | |
491 | #define gpio_irq_set_wake NULL | |
492 | #endif | |
493 | ||
73a59c1c SP |
494 | |
495 | /* Several AIC controller irqs are dispatched through this GPIO handler. | |
496 | * To use any AT91_PIN_* as an externally triggered IRQ, first call | |
497 | * at91_set_gpio_input() then maybe enable its glitch filter. | |
498 | * Then just request_irq() with the pin ID; it works like any ARM IRQ | |
582d5fbd NF |
499 | * handler. |
500 | * First implementation always triggers on rising and falling edges | |
501 | * whereas the newer PIO3 can be additionally configured to trigger on | |
502 | * level, edge with any polarity. | |
73a59c1c SP |
503 | * |
504 | * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after | |
505 | * configuring them with at91_set_a_periph() or at91_set_b_periph(). | |
506 | * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. | |
507 | */ | |
508 | ||
da0f9403 | 509 | static void gpio_irq_mask(struct irq_data *d) |
73a59c1c | 510 | { |
21f81872 NF |
511 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); |
512 | void __iomem *pio = at91_gpio->regbase; | |
513 | unsigned mask = 1 << d->hwirq; | |
73a59c1c SP |
514 | |
515 | if (pio) | |
516 | __raw_writel(mask, pio + PIO_IDR); | |
517 | } | |
518 | ||
da0f9403 | 519 | static void gpio_irq_unmask(struct irq_data *d) |
73a59c1c | 520 | { |
21f81872 NF |
521 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); |
522 | void __iomem *pio = at91_gpio->regbase; | |
523 | unsigned mask = 1 << d->hwirq; | |
73a59c1c SP |
524 | |
525 | if (pio) | |
526 | __raw_writel(mask, pio + PIO_IER); | |
527 | } | |
528 | ||
da0f9403 | 529 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
73a59c1c | 530 | { |
e83aff58 DB |
531 | switch (type) { |
532 | case IRQ_TYPE_NONE: | |
533 | case IRQ_TYPE_EDGE_BOTH: | |
534 | return 0; | |
535 | default: | |
536 | return -EINVAL; | |
537 | } | |
73a59c1c SP |
538 | } |
539 | ||
582d5fbd NF |
540 | /* Alternate irq type for PIO3 support */ |
541 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type) | |
542 | { | |
543 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
544 | void __iomem *pio = at91_gpio->regbase; | |
545 | unsigned mask = 1 << d->hwirq; | |
546 | ||
547 | switch (type) { | |
548 | case IRQ_TYPE_EDGE_RISING: | |
549 | __raw_writel(mask, pio + PIO_ESR); | |
550 | __raw_writel(mask, pio + PIO_REHLSR); | |
551 | break; | |
552 | case IRQ_TYPE_EDGE_FALLING: | |
553 | __raw_writel(mask, pio + PIO_ESR); | |
554 | __raw_writel(mask, pio + PIO_FELLSR); | |
555 | break; | |
556 | case IRQ_TYPE_LEVEL_LOW: | |
557 | __raw_writel(mask, pio + PIO_LSR); | |
558 | __raw_writel(mask, pio + PIO_FELLSR); | |
559 | break; | |
560 | case IRQ_TYPE_LEVEL_HIGH: | |
561 | __raw_writel(mask, pio + PIO_LSR); | |
562 | __raw_writel(mask, pio + PIO_REHLSR); | |
563 | break; | |
564 | case IRQ_TYPE_EDGE_BOTH: | |
565 | /* | |
566 | * disable additional interrupt modes: | |
567 | * fall back to default behavior | |
568 | */ | |
569 | __raw_writel(mask, pio + PIO_AIMDR); | |
570 | return 0; | |
571 | case IRQ_TYPE_NONE: | |
572 | default: | |
573 | pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); | |
574 | return -EINVAL; | |
575 | } | |
576 | ||
577 | /* enable additional interrupt modes */ | |
578 | __raw_writel(mask, pio + PIO_AIMER); | |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
38c677cb DB |
583 | static struct irq_chip gpio_irqchip = { |
584 | .name = "GPIO", | |
ac93cdbd | 585 | .irq_disable = gpio_irq_mask, |
da0f9403 LB |
586 | .irq_mask = gpio_irq_mask, |
587 | .irq_unmask = gpio_irq_unmask, | |
582d5fbd | 588 | /* .irq_set_type is set dynamically */ |
da0f9403 | 589 | .irq_set_wake = gpio_irq_set_wake, |
73a59c1c SP |
590 | }; |
591 | ||
10dd5ce2 | 592 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
73a59c1c | 593 | { |
42a859da | 594 | struct irq_chip *chip = irq_desc_get_chip(desc); |
ac93cdbd | 595 | struct irq_data *idata = irq_desc_get_irq_data(desc); |
ac93cdbd TG |
596 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); |
597 | void __iomem *pio = at91_gpio->regbase; | |
8014d6f4 NF |
598 | unsigned long isr; |
599 | int n; | |
73a59c1c | 600 | |
42a859da | 601 | chained_irq_enter(chip, desc); |
73a59c1c | 602 | for (;;) { |
e83aff58 DB |
603 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. |
604 | * When there none are pending, we're finished unless we need | |
605 | * to process multiple banks (like ID_PIOCDE on sam9263). | |
606 | */ | |
73a59c1c | 607 | isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); |
e83aff58 | 608 | if (!isr) { |
f373e8c0 | 609 | if (!at91_gpio->next) |
e83aff58 | 610 | break; |
f373e8c0 RM |
611 | at91_gpio = at91_gpio->next; |
612 | pio = at91_gpio->regbase; | |
e83aff58 DB |
613 | continue; |
614 | } | |
73a59c1c | 615 | |
8014d6f4 NF |
616 | n = find_first_bit(&isr, BITS_PER_LONG); |
617 | while (n < BITS_PER_LONG) { | |
618 | generic_handle_irq(irq_find_mapping(at91_gpio->domain, n)); | |
619 | n = find_next_bit(&isr, BITS_PER_LONG, n + 1); | |
73a59c1c SP |
620 | } |
621 | } | |
42a859da | 622 | chained_irq_exit(chip, desc); |
73a59c1c SP |
623 | /* now it may re-trigger */ |
624 | } | |
625 | ||
f2173834 AV |
626 | /*--------------------------------------------------------------------------*/ |
627 | ||
b66545e7 AV |
628 | #ifdef CONFIG_DEBUG_FS |
629 | ||
582d5fbd NF |
630 | static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask) |
631 | { | |
632 | char *trigger = NULL; | |
633 | char *polarity = NULL; | |
634 | ||
635 | if (__raw_readl(pio + PIO_IMR) & mask) { | |
636 | if (!has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) { | |
637 | trigger = "edge"; | |
638 | polarity = "both"; | |
639 | } else { | |
640 | if (__raw_readl(pio + PIO_ELSR) & mask) { | |
641 | trigger = "level"; | |
642 | polarity = __raw_readl(pio + PIO_FRLHSR) & mask ? | |
643 | "high" : "low"; | |
644 | } else { | |
645 | trigger = "edge"; | |
646 | polarity = __raw_readl(pio + PIO_FRLHSR) & mask ? | |
647 | "rising" : "falling"; | |
648 | } | |
649 | } | |
650 | seq_printf(s, "IRQ:%s-%s\t", trigger, polarity); | |
651 | } else { | |
652 | seq_printf(s, "GPIO:%s\t\t", | |
653 | __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0"); | |
654 | } | |
655 | } | |
656 | ||
b66545e7 AV |
657 | static int at91_gpio_show(struct seq_file *s, void *unused) |
658 | { | |
659 | int bank, j; | |
660 | ||
661 | /* print heading */ | |
662 | seq_printf(s, "Pin\t"); | |
663 | for (bank = 0; bank < gpio_banks; bank++) { | |
582d5fbd | 664 | seq_printf(s, "PIO%c\t\t", 'A' + bank); |
b66545e7 AV |
665 | }; |
666 | seq_printf(s, "\n\n"); | |
667 | ||
668 | /* print pin status */ | |
669 | for (j = 0; j < 32; j++) { | |
670 | seq_printf(s, "%i:\t", j); | |
671 | ||
672 | for (bank = 0; bank < gpio_banks; bank++) { | |
d0fbda9a | 673 | unsigned pin = (32 * bank) + j; |
b66545e7 AV |
674 | void __iomem *pio = pin_to_controller(pin); |
675 | unsigned mask = pin_to_mask(pin); | |
676 | ||
677 | if (__raw_readl(pio + PIO_PSR) & mask) | |
582d5fbd | 678 | gpio_printf(s, pio, mask); |
b66545e7 | 679 | else |
582d5fbd NF |
680 | seq_printf(s, "%c\t\t", |
681 | peripheral_function(pio, mask)); | |
b66545e7 AV |
682 | } |
683 | ||
684 | seq_printf(s, "\n"); | |
685 | } | |
686 | ||
687 | return 0; | |
688 | } | |
689 | ||
690 | static int at91_gpio_open(struct inode *inode, struct file *file) | |
691 | { | |
692 | return single_open(file, at91_gpio_show, NULL); | |
693 | } | |
694 | ||
695 | static const struct file_operations at91_gpio_operations = { | |
696 | .open = at91_gpio_open, | |
697 | .read = seq_read, | |
698 | .llseek = seq_lseek, | |
699 | .release = single_release, | |
700 | }; | |
701 | ||
702 | static int __init at91_gpio_debugfs_init(void) | |
703 | { | |
704 | /* /sys/kernel/debug/at91_gpio */ | |
705 | (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations); | |
706 | return 0; | |
707 | } | |
708 | postcore_initcall(at91_gpio_debugfs_init); | |
709 | ||
710 | #endif | |
711 | ||
712 | /*--------------------------------------------------------------------------*/ | |
713 | ||
8014d6f4 NF |
714 | /* |
715 | * This lock class tells lockdep that GPIO irqs are in a different | |
716 | * category than their parents, so it won't report false recursion. | |
717 | */ | |
718 | static struct lock_class_key gpio_lock_class; | |
719 | ||
720 | #if defined(CONFIG_OF) | |
721 | static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq, | |
722 | irq_hw_number_t hw) | |
723 | { | |
724 | struct at91_gpio_chip *at91_gpio = h->host_data; | |
725 | ||
726 | irq_set_lockdep_class(virq, &gpio_lock_class); | |
727 | ||
728 | /* | |
729 | * Can use the "simple" and not "edge" handler since it's | |
730 | * shorter, and the AIC handles interrupts sanely. | |
731 | */ | |
732 | irq_set_chip_and_handler(virq, &gpio_irqchip, | |
733 | handle_simple_irq); | |
734 | set_irq_flags(virq, IRQF_VALID); | |
735 | irq_set_chip_data(virq, at91_gpio); | |
736 | ||
737 | return 0; | |
738 | } | |
739 | ||
740 | static struct irq_domain_ops at91_gpio_ops = { | |
741 | .map = at91_gpio_irq_map, | |
742 | .xlate = irq_domain_xlate_twocell, | |
743 | }; | |
744 | ||
745 | int __init at91_gpio_of_irq_setup(struct device_node *node, | |
746 | struct device_node *parent) | |
747 | { | |
748 | struct at91_gpio_chip *prev = NULL; | |
749 | int alias_idx = of_alias_get_id(node, "gpio"); | |
750 | struct at91_gpio_chip *at91_gpio = &gpio_chip[alias_idx]; | |
751 | ||
582d5fbd NF |
752 | /* Setup proper .irq_set_type function */ |
753 | if (has_pio3()) | |
754 | gpio_irqchip.irq_set_type = alt_gpio_irq_type; | |
755 | else | |
756 | gpio_irqchip.irq_set_type = gpio_irq_type; | |
757 | ||
8014d6f4 NF |
758 | /* Disable irqs of this PIO controller */ |
759 | __raw_writel(~0, at91_gpio->regbase + PIO_IDR); | |
760 | ||
761 | /* Setup irq domain */ | |
762 | at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio, | |
763 | &at91_gpio_ops, at91_gpio); | |
764 | if (!at91_gpio->domain) | |
765 | panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", | |
766 | at91_gpio->pioc_idx); | |
767 | ||
768 | /* Setup chained handler */ | |
769 | if (at91_gpio->pioc_idx) | |
770 | prev = &gpio_chip[at91_gpio->pioc_idx - 1]; | |
771 | ||
772 | /* The toplevel handler handles one bank of GPIOs, except | |
773 | * on some SoC it can handles up to three... | |
774 | * We only set up the handler for the first of the list. | |
775 | */ | |
776 | if (prev && prev->next == at91_gpio) | |
777 | return 0; | |
778 | ||
779 | at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent), | |
780 | at91_gpio->pioc_hwirq); | |
781 | irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio); | |
782 | irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler); | |
783 | ||
784 | return 0; | |
785 | } | |
786 | #else | |
787 | int __init at91_gpio_of_irq_setup(struct device_node *node, | |
788 | struct device_node *parent) | |
789 | { | |
790 | return -EINVAL; | |
791 | } | |
792 | #endif | |
793 | ||
21f81872 NF |
794 | /* |
795 | * irqdomain initialization: pile up irqdomains on top of AIC range | |
796 | */ | |
797 | static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio) | |
798 | { | |
799 | int irq_base; | |
800 | ||
801 | irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0); | |
802 | if (irq_base < 0) | |
803 | panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n", | |
804 | at91_gpio->pioc_idx, irq_base); | |
8014d6f4 | 805 | at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio, |
21f81872 NF |
806 | irq_base, 0, |
807 | &irq_domain_simple_ops, NULL); | |
808 | if (!at91_gpio->domain) | |
809 | panic("at91_gpio.%d: couldn't allocate irq domain.\n", | |
810 | at91_gpio->pioc_idx); | |
811 | } | |
812 | ||
f2173834 AV |
813 | /* |
814 | * Called from the processor-specific init to enable GPIO interrupt support. | |
815 | */ | |
816 | void __init at91_gpio_irq_setup(void) | |
73a59c1c | 817 | { |
21f81872 NF |
818 | unsigned pioc; |
819 | int gpio_irqnbr = 0; | |
f373e8c0 | 820 | struct at91_gpio_chip *this, *prev; |
73a59c1c | 821 | |
582d5fbd NF |
822 | /* Setup proper .irq_set_type function */ |
823 | if (has_pio3()) | |
824 | gpio_irqchip.irq_set_type = alt_gpio_irq_type; | |
825 | else | |
826 | gpio_irqchip.irq_set_type = gpio_irq_type; | |
827 | ||
d0fbda9a | 828 | for (pioc = 0, this = gpio_chip, prev = NULL; |
e83aff58 DB |
829 | pioc++ < gpio_banks; |
830 | prev = this, this++) { | |
8014d6f4 | 831 | int offset; |
73a59c1c | 832 | |
e83aff58 | 833 | __raw_writel(~0, this->regbase + PIO_IDR); |
73a59c1c | 834 | |
21f81872 NF |
835 | /* setup irq domain for this GPIO controller */ |
836 | at91_gpio_irqdomain(this); | |
837 | ||
838 | for (offset = 0; offset < this->chip.ngpio; offset++) { | |
839 | unsigned int virq = irq_find_mapping(this->domain, offset); | |
840 | irq_set_lockdep_class(virq, &gpio_lock_class); | |
37aca70c | 841 | |
814138ff AV |
842 | /* |
843 | * Can use the "simple" and not "edge" handler since it's | |
3a4fa0a2 | 844 | * shorter, and the AIC handles interrupts sanely. |
814138ff | 845 | */ |
21f81872 | 846 | irq_set_chip_and_handler(virq, &gpio_irqchip, |
f38c02f3 | 847 | handle_simple_irq); |
21f81872 NF |
848 | set_irq_flags(virq, IRQF_VALID); |
849 | irq_set_chip_data(virq, this); | |
850 | ||
851 | gpio_irqnbr++; | |
73a59c1c SP |
852 | } |
853 | ||
e83aff58 | 854 | /* The toplevel handler handles one bank of GPIOs, except |
4340cde5 NF |
855 | * on some SoC it can handles up to three... |
856 | * We only set up the handler for the first of the list. | |
e83aff58 DB |
857 | */ |
858 | if (prev && prev->next == this) | |
859 | continue; | |
860 | ||
8014d6f4 NF |
861 | this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq); |
862 | irq_set_chip_data(this->pioc_virq, this); | |
863 | irq_set_chained_handler(this->pioc_virq, gpio_irq_handler); | |
73a59c1c | 864 | } |
21f81872 | 865 | pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks); |
f2173834 AV |
866 | } |
867 | ||
f373e8c0 | 868 | /* gpiolib support */ |
c18486e1 JCPV |
869 | static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset) |
870 | { | |
871 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
872 | void __iomem *pio = at91_gpio->regbase; | |
873 | unsigned mask = 1 << offset; | |
874 | ||
875 | __raw_writel(mask, pio + PIO_PER); | |
876 | return 0; | |
877 | } | |
878 | ||
f373e8c0 RM |
879 | static int at91_gpiolib_direction_input(struct gpio_chip *chip, |
880 | unsigned offset) | |
881 | { | |
882 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
883 | void __iomem *pio = at91_gpio->regbase; | |
884 | unsigned mask = 1 << offset; | |
885 | ||
886 | __raw_writel(mask, pio + PIO_ODR); | |
887 | return 0; | |
888 | } | |
889 | ||
890 | static int at91_gpiolib_direction_output(struct gpio_chip *chip, | |
891 | unsigned offset, int val) | |
892 | { | |
893 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
894 | void __iomem *pio = at91_gpio->regbase; | |
895 | unsigned mask = 1 << offset; | |
896 | ||
897 | __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
898 | __raw_writel(mask, pio + PIO_OER); | |
899 | return 0; | |
900 | } | |
901 | ||
902 | static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset) | |
903 | { | |
904 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
905 | void __iomem *pio = at91_gpio->regbase; | |
906 | unsigned mask = 1 << offset; | |
907 | u32 pdsr; | |
908 | ||
909 | pdsr = __raw_readl(pio + PIO_PDSR); | |
910 | return (pdsr & mask) != 0; | |
911 | } | |
912 | ||
913 | static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val) | |
914 | { | |
915 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
916 | void __iomem *pio = at91_gpio->regbase; | |
917 | unsigned mask = 1 << offset; | |
918 | ||
919 | __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
920 | } | |
921 | ||
f373e8c0 RM |
922 | static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
923 | { | |
924 | int i; | |
925 | ||
926 | for (i = 0; i < chip->ngpio; i++) { | |
927 | unsigned pin = chip->base + i; | |
928 | void __iomem *pio = pin_to_controller(pin); | |
929 | unsigned mask = pin_to_mask(pin); | |
930 | const char *gpio_label; | |
931 | ||
932 | gpio_label = gpiochip_is_requested(chip, i); | |
933 | if (gpio_label) { | |
934 | seq_printf(s, "[%s] GPIO%s%d: ", | |
935 | gpio_label, chip->label, i); | |
936 | if (__raw_readl(pio + PIO_PSR) & mask) | |
937 | seq_printf(s, "[gpio] %s\n", | |
938 | at91_get_gpio_value(pin) ? | |
939 | "set" : "clear"); | |
940 | else | |
582d5fbd NF |
941 | seq_printf(s, "[periph %c]\n", |
942 | peripheral_function(pio, mask)); | |
f373e8c0 RM |
943 | } |
944 | } | |
945 | } | |
946 | ||
b134ce85 NF |
947 | static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset) |
948 | { | |
949 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
8014d6f4 NF |
950 | int virq; |
951 | ||
952 | if (offset < chip->ngpio) | |
953 | virq = irq_create_mapping(at91_gpio->domain, offset); | |
954 | else | |
955 | virq = -ENXIO; | |
b134ce85 NF |
956 | |
957 | dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", | |
958 | chip->label, offset + chip->base, virq); | |
959 | return virq; | |
960 | } | |
961 | ||
21f81872 NF |
962 | static int __init at91_gpio_setup_clk(int idx) |
963 | { | |
964 | struct at91_gpio_chip *at91_gpio = &gpio_chip[idx]; | |
965 | ||
966 | /* retreive PIO controller's clock */ | |
967 | at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label); | |
968 | if (IS_ERR(at91_gpio->clock)) { | |
969 | pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx); | |
970 | goto err; | |
971 | } | |
972 | ||
973 | if (clk_prepare(at91_gpio->clock)) | |
974 | goto clk_prep_err; | |
975 | ||
976 | /* enable PIO controller's clock */ | |
977 | if (clk_enable(at91_gpio->clock)) { | |
978 | pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx); | |
979 | goto clk_err; | |
980 | } | |
981 | ||
982 | return 0; | |
983 | ||
984 | clk_err: | |
985 | clk_unprepare(at91_gpio->clock); | |
986 | clk_prep_err: | |
987 | clk_put(at91_gpio->clock); | |
988 | err: | |
989 | return -EINVAL; | |
990 | } | |
991 | ||
992 | #ifdef CONFIG_OF_GPIO | |
993 | static void __init of_at91_gpio_init_one(struct device_node *np) | |
994 | { | |
995 | int alias_idx; | |
996 | struct at91_gpio_chip *at91_gpio; | |
fc33ff43 | 997 | uint32_t ngpio; |
21f81872 NF |
998 | |
999 | if (!np) | |
1000 | return; | |
1001 | ||
1002 | alias_idx = of_alias_get_id(np, "gpio"); | |
1003 | if (alias_idx >= MAX_GPIO_BANKS) { | |
1004 | pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n", | |
1005 | alias_idx, MAX_GPIO_BANKS); | |
1006 | return; | |
1007 | } | |
1008 | ||
1009 | at91_gpio = &gpio_chip[alias_idx]; | |
fc33ff43 | 1010 | at91_gpio->chip.base = alias_idx * MAX_NB_GPIO_PER_BANK; |
21f81872 NF |
1011 | |
1012 | at91_gpio->regbase = of_iomap(np, 0); | |
1013 | if (!at91_gpio->regbase) { | |
1014 | pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", | |
1015 | alias_idx); | |
1016 | return; | |
1017 | } | |
1018 | ||
1019 | /* Get the interrupts property */ | |
1020 | if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) { | |
1021 | pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n", | |
1022 | alias_idx); | |
1023 | goto ioremap_err; | |
1024 | } | |
1025 | ||
582d5fbd NF |
1026 | /* Get capabilities from compatibility property */ |
1027 | if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio")) | |
1028 | at91_gpio_caps |= AT91_GPIO_CAP_PIO3; | |
1029 | ||
fc33ff43 JCPV |
1030 | if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { |
1031 | if (ngpio >= MAX_NB_GPIO_PER_BANK) | |
1032 | pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", | |
1033 | alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); | |
1034 | else | |
1035 | at91_gpio->chip.ngpio = ngpio; | |
1036 | } | |
1037 | ||
21f81872 NF |
1038 | /* Setup clock */ |
1039 | if (at91_gpio_setup_clk(alias_idx)) | |
1040 | goto ioremap_err; | |
1041 | ||
1042 | at91_gpio->chip.of_node = np; | |
1043 | gpio_banks = max(gpio_banks, alias_idx + 1); | |
1044 | at91_gpio->pioc_idx = alias_idx; | |
1045 | return; | |
1046 | ||
1047 | ioremap_err: | |
1048 | iounmap(at91_gpio->regbase); | |
1049 | } | |
1050 | ||
1051 | static int __init of_at91_gpio_init(void) | |
1052 | { | |
1053 | struct device_node *np = NULL; | |
1054 | ||
1055 | /* | |
1056 | * This isn't ideal, but it gets things hooked up until this | |
1057 | * driver is converted into a platform_device | |
1058 | */ | |
1059 | for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio") | |
1060 | of_at91_gpio_init_one(np); | |
1061 | ||
1062 | return gpio_banks > 0 ? 0 : -EINVAL; | |
1063 | } | |
1064 | #else | |
1065 | static int __init of_at91_gpio_init(void) | |
1066 | { | |
1067 | return -EINVAL; | |
1068 | } | |
1069 | #endif | |
1070 | ||
1071 | static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq) | |
1072 | { | |
1073 | struct at91_gpio_chip *at91_gpio = &gpio_chip[idx]; | |
1074 | ||
fc33ff43 | 1075 | at91_gpio->chip.base = idx * MAX_NB_GPIO_PER_BANK; |
21f81872 NF |
1076 | at91_gpio->pioc_hwirq = pioc_hwirq; |
1077 | at91_gpio->pioc_idx = idx; | |
1078 | ||
1079 | at91_gpio->regbase = ioremap(regbase, 512); | |
1080 | if (!at91_gpio->regbase) { | |
1081 | pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx); | |
1082 | return; | |
1083 | } | |
1084 | ||
1085 | if (at91_gpio_setup_clk(idx)) | |
1086 | goto ioremap_err; | |
1087 | ||
1088 | gpio_banks = max(gpio_banks, idx + 1); | |
1089 | return; | |
1090 | ||
1091 | ioremap_err: | |
1092 | iounmap(at91_gpio->regbase); | |
1093 | } | |
1094 | ||
f2173834 AV |
1095 | /* |
1096 | * Called from the processor-specific init to enable GPIO pin support. | |
1097 | */ | |
1098 | void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) | |
1099 | { | |
21f81872 | 1100 | unsigned i; |
f373e8c0 | 1101 | struct at91_gpio_chip *at91_gpio, *last = NULL; |
e83aff58 | 1102 | |
f2173834 AV |
1103 | BUG_ON(nr_banks > MAX_GPIO_BANKS); |
1104 | ||
21f81872 NF |
1105 | if (of_at91_gpio_init() < 0) { |
1106 | /* No GPIO controller found in device tree */ | |
1107 | for (i = 0; i < nr_banks; i++) | |
1108 | at91_gpio_init_one(i, data[i].regbase, data[i].id); | |
1109 | } | |
e83aff58 | 1110 | |
21f81872 | 1111 | for (i = 0; i < gpio_banks; i++) { |
f373e8c0 RM |
1112 | at91_gpio = &gpio_chip[i]; |
1113 | ||
4340cde5 NF |
1114 | /* |
1115 | * GPIO controller are grouped on some SoC: | |
1116 | * PIOC, PIOD and PIOE can share the same IRQ line | |
1117 | */ | |
1118 | if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq) | |
f373e8c0 RM |
1119 | last->next = at91_gpio; |
1120 | last = at91_gpio; | |
1121 | ||
1122 | gpiochip_add(&at91_gpio->chip); | |
e83aff58 | 1123 | } |
73a59c1c | 1124 | } |