[deliverable/linux.git] / arch / arm / mach-at91rm9200 / gpio.c

/*
 * linux/arch/arm/mach-at91rm9200/gpio.c
 *
 * Copyright (C) 2005 HP Labs
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/clk.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>

#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/gpio.h>

#include "generic.h"


static struct at91_gpio_bank *gpio;
static int gpio_banks;


static inline void __iomem *pin_to_controller(unsigned pin)
{
	void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;

	pin -= PIN_BASE;
	pin /= 32;
	if (likely(pin < gpio_banks))
		return sys_base + gpio[pin].offset;

	return NULL;
}

static inline unsigned pin_to_mask(unsigned pin)
{
	pin -= PIN_BASE;
	return 1 << (pin % 32);
}


/*--------------------------------------------------------------------------*/

/* Not all hardware capabilities are exposed through these calls; they
 * only encapsulate the most common features and modes.  (So if you
 * want to change signals in groups, do it directly.)
 *
 * Bootloaders will usually handle some of the pin multiplexing setup.
 * The intent is certainly that by the time Linux is fully booted, all
 * pins should have been fully initialized.  These setup calls should
 * only be used by board setup routines, or possibly in driver probe().
 *
 * For bootloaders doing all that setup, these calls could be inlined
 * as NOPs so Linux won't duplicate any setup code
 */


/*
 * mux the pin to the "A" internal peripheral role.
 */
int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	__raw_writel(mask, pio + PIO_ASR);
	__raw_writel(mask, pio + PIO_PDR);
	return 0;
}
EXPORT_SYMBOL(at91_set_A_periph);


/*
 * mux the pin to the "B" internal peripheral role.
 */
int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	__raw_writel(mask, pio + PIO_BSR);
	__raw_writel(mask, pio + PIO_PDR);
	return 0;
}
EXPORT_SYMBOL(at91_set_B_periph);


/*
 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
 * configure it for an input.
 */
int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	__raw_writel(mask, pio + PIO_ODR);
	__raw_writel(mask, pio + PIO_PER);
	return 0;
}
EXPORT_SYMBOL(at91_set_gpio_input);


/*
 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
 * and configure it for an output.
 */
int __init_or_module at91_set_gpio_output(unsigned pin, int value)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + PIO_PUDR);
	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
	__raw_writel(mask, pio + PIO_OER);
	__raw_writel(mask, pio + PIO_PER);
	return 0;
}
EXPORT_SYMBOL(at91_set_gpio_output);


/*
 * enable/disable the glitch filter; mostly used with IRQ handling.
 */
int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;
	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
	return 0;
}
EXPORT_SYMBOL(at91_set_deglitch);

/*
 * enable/disable the multi-driver; This is only valid for output and
 * allows the output pin to run as an open collector output.
 */
int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
	return 0;
}
EXPORT_SYMBOL(at91_set_multi_drive);

/*--------------------------------------------------------------------------*/

/*
 * assuming the pin is muxed as a gpio output, set its value.
 */
int at91_set_gpio_value(unsigned pin, int value)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;
	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
	return 0;
}
EXPORT_SYMBOL(at91_set_gpio_value);


/*
 * read the pin's value (works even if it's not muxed as a gpio).
 */
int at91_get_gpio_value(unsigned pin)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);
	u32		pdsr;

	if (!pio)
		return -EINVAL;
	pdsr = __raw_readl(pio + PIO_PDSR);
	return (pdsr & mask) != 0;
}
EXPORT_SYMBOL(at91_get_gpio_value);

/*--------------------------------------------------------------------------*/

#ifdef CONFIG_PM

static u32 wakeups[MAX_GPIO_BANKS];
static u32 backups[MAX_GPIO_BANKS];

static int gpio_irq_set_wake(unsigned pin, unsigned state)
{
	unsigned	mask = pin_to_mask(pin);
	unsigned	bank = (pin - PIN_BASE) / 32;

	if (unlikely(bank >= MAX_GPIO_BANKS))
		return -EINVAL;

	if (state)
		wakeups[bank] |= mask;
	else
		wakeups[bank] &= ~mask;

	set_irq_wake(gpio[bank].id, state);

	return 0;
}

void at91_gpio_suspend(void)
{
	int i;

	for (i = 0; i < gpio_banks; i++) {
		u32 pio = gpio[i].offset;

		backups[i] = at91_sys_read(pio + PIO_IMR);
		at91_sys_write(pio + PIO_IDR, backups[i]);
		at91_sys_write(pio + PIO_IER, wakeups[i]);

		if (!wakeups[i])
			clk_disable(gpio[i].clock);
		else {
#ifdef CONFIG_PM_DEBUG
			printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
#endif
		}
	}
}

void at91_gpio_resume(void)
{
	int i;

	for (i = 0; i < gpio_banks; i++) {
		u32 pio = gpio[i].offset;

		if (!wakeups[i])
			clk_enable(gpio[i].clock);

		at91_sys_write(pio + PIO_IDR, wakeups[i]);
		at91_sys_write(pio + PIO_IER, backups[i]);
	}
}

#else
#define gpio_irq_set_wake	NULL
#endif


/* Several AIC controller irqs are dispatched through this GPIO handler.
 * To use any AT91_PIN_* as an externally triggered IRQ, first call
 * at91_set_gpio_input() then maybe enable its glitch filter.
 * Then just request_irq() with the pin ID; it works like any ARM IRQ
 * handler, though it always triggers on rising and falling edges.
 *
 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
 * configuring them with at91_set_a_periph() or at91_set_b_periph().
 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
 */

static void gpio_irq_mask(unsigned pin)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (pio)
		__raw_writel(mask, pio + PIO_IDR);
}

static void gpio_irq_unmask(unsigned pin)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (pio)
		__raw_writel(mask, pio + PIO_IER);
}

static int gpio_irq_type(unsigned pin, unsigned type)
{
	return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
}

static struct irq_chip gpio_irqchip = {
	.name		= "GPIO",
	.mask		= gpio_irq_mask,
	.unmask		= gpio_irq_unmask,
	.set_type	= gpio_irq_type,
	.set_wake	= gpio_irq_set_wake,
};

static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
	unsigned	pin;
	struct irq_desc	*gpio;
	void __iomem	*pio;
	u32		isr;

	pio = get_irq_chip_data(irq);

	/* temporarily mask (level sensitive) parent IRQ */
	desc->chip->ack(irq);
	for (;;) {
		/* reading ISR acks the pending (edge triggered) GPIO interrupt */
		isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
		if (!isr)
			break;

		pin = (unsigned) get_irq_data(irq);
		gpio = &irq_desc[pin];

		while (isr) {
			if (isr & 1) {
				if (unlikely(gpio->depth)) {
					/*
					 * The core ARM interrupt handler lazily disables IRQs so
					 * another IRQ must be generated before it actually gets
					 * here to be disabled on the GPIO controller.
					 */
					gpio_irq_mask(pin);
				}
				else
					desc_handle_irq(pin, gpio);
			}
			pin++;
			gpio++;
			isr >>= 1;
		}
	}
	desc->chip->unmask(irq);
	/* now it may re-trigger */
}

/*--------------------------------------------------------------------------*/

/*
 * Called from the processor-specific init to enable GPIO interrupt support.
 */
void __init at91_gpio_irq_setup(void)
{
	unsigned	pioc, pin;

	for (pioc = 0, pin = PIN_BASE;
			pioc < gpio_banks;
			pioc++) {
		void __iomem	*controller;
		unsigned	id = gpio[pioc].id;
		unsigned	i;

		clk_enable(gpio[pioc].clock);	/* enable PIO controller's clock */

		controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset;
		__raw_writel(~0, controller + PIO_IDR);

		set_irq_data(id, (void *) pin);
		set_irq_chip_data(id, controller);

		for (i = 0; i < 32; i++, pin++) {
			/*
			 * Can use the "simple" and not "edge" handler since it's
			 * shorter, and the AIC handles interupts sanely.
			 */
			set_irq_chip(pin, &gpio_irqchip);
			set_irq_handler(pin, handle_simple_irq);
			set_irq_flags(pin, IRQF_VALID);
		}

		set_irq_chained_handler(id, gpio_irq_handler);
	}
	pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
}

/*
 * Called from the processor-specific init to enable GPIO pin support.
 */
void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
{
	BUG_ON(nr_banks > MAX_GPIO_BANKS);

	gpio = data;
	gpio_banks = nr_banks;
}
Commit	Line	Data
73a59c1c SP	1	/*
	2	* linux/arch/arm/mach-at91rm9200/gpio.c
	3	*
	4	* Copyright (C) 2005 HP Labs
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
f2173834	12	#include <linux/clk.h>
73a59c1c	13	#include <linux/errno.h>
07d265dd TG	14	#include <linux/interrupt.h>
07d265dd TG	15	#include <linux/irq.h>
73a59c1c SP	16	#include <linux/kernel.h>
	17	#include <linux/list.h>
	18	#include <linux/module.h>
	19
	20	#include <asm/io.h>
ea75ee9a	21	#include <asm/hardware.h>
55d8baee	22	#include <asm/arch/at91_pio.h>
73a59c1c SP	23	#include <asm/arch/gpio.h>
73a59c1c SP	24
f2173834 AV	25	#include "generic.h"
	26
	27
	28	static struct at91_gpio_bank *gpio;
	29	static int gpio_banks;
	30
73a59c1c SP	31
	32	static inline void __iomem *pin_to_controller(unsigned pin)
	33	{
	34	void __iomem sys_base = (void __iomem ) AT91_VA_BASE_SYS;
	35
	36	pin -= PIN_BASE;
	37	pin /= 32;
f2173834 AV	38	if (likely(pin < gpio_banks))
f2173834 AV	39	return sys_base + gpio[pin].offset;
73a59c1c SP	40
	41	return NULL;
	42	}
	43
	44	static inline unsigned pin_to_mask(unsigned pin)
	45	{
	46	pin -= PIN_BASE;
	47	return 1 << (pin % 32);
	48	}
	49
	50
	51	/--------------------------------------------------------------------------/
	52
	53	/* Not all hardware capabilities are exposed through these calls; they
	54	* only encapsulate the most common features and modes. (So if you
	55	* want to change signals in groups, do it directly.)
	56	*
	57	* Bootloaders will usually handle some of the pin multiplexing setup.
	58	* The intent is certainly that by the time Linux is fully booted, all
	59	* pins should have been fully initialized. These setup calls should
	60	* only be used by board setup routines, or possibly in driver probe().
	61	*
	62	* For bootloaders doing all that setup, these calls could be inlined
	63	* as NOPs so Linux won't duplicate any setup code
	64	*/
	65
	66
	67	/*
	68	* mux the pin to the "A" internal peripheral role.
	69	*/
	70	int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
	71	{
	72	void __iomem *pio = pin_to_controller(pin);
	73	unsigned mask = pin_to_mask(pin);
	74
	75	if (!pio)
	76	return -EINVAL;
	77
	78	__raw_writel(mask, pio + PIO_IDR);
	79	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	80	__raw_writel(mask, pio + PIO_ASR);
	81	__raw_writel(mask, pio + PIO_PDR);
	82	return 0;
	83	}
	84	EXPORT_SYMBOL(at91_set_A_periph);
	85
	86
	87	/*
	88	* mux the pin to the "B" internal peripheral role.
	89	*/
	90	int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
	91	{
	92	void __iomem *pio = pin_to_controller(pin);
	93	unsigned mask = pin_to_mask(pin);
	94
	95	if (!pio)
	96	return -EINVAL;
	97
	98	__raw_writel(mask, pio + PIO_IDR);
	99	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	100	__raw_writel(mask, pio + PIO_BSR);
	101	__raw_writel(mask, pio + PIO_PDR);
	102	return 0;
	103	}
104	EXPORT_SYMBOL(at91_set_B_periph);
105
106
107	/*
108	* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
109	* configure it for an input.
110	*/
111	int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
112	{
113	void __iomem *pio = pin_to_controller(pin);
114	unsigned mask = pin_to_mask(pin);
115
116	if (!pio)
117	return -EINVAL;
118
119	__raw_writel(mask, pio + PIO_IDR);
120	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
121	__raw_writel(mask, pio + PIO_ODR);
122	__raw_writel(mask, pio + PIO_PER);
123	return 0;
124	}
125	EXPORT_SYMBOL(at91_set_gpio_input);
126
127
128	/*
129	* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
130	* and configure it for an output.
131	*/
132	int __init_or_module at91_set_gpio_output(unsigned pin, int value)
133	{
134	void __iomem *pio = pin_to_controller(pin);
135	unsigned mask = pin_to_mask(pin);
136
137	if (!pio)
138	return -EINVAL;
139
140	__raw_writel(mask, pio + PIO_IDR);
141	__raw_writel(mask, pio + PIO_PUDR);
142	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
143	__raw_writel(mask, pio + PIO_OER);
144	__raw_writel(mask, pio + PIO_PER);
145	return 0;
146	}
147	EXPORT_SYMBOL(at91_set_gpio_output);
148
149
150	/*
151	* enable/disable the glitch filter; mostly used with IRQ handling.
152	*/
153	int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
154	{
155	void __iomem *pio = pin_to_controller(pin);
156	unsigned mask = pin_to_mask(pin);
157
158	if (!pio)
159	return -EINVAL;
160	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
161	return 0;
162	}
163	EXPORT_SYMBOL(at91_set_deglitch);
164
df666b9c AV	165	/*
	166	* enable/disable the multi-driver; This is only valid for output and
	167	* allows the output pin to run as an open collector output.
	168	*/
	169	int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
	170	{
	171	void __iomem *pio = pin_to_controller(pin);
	172	unsigned mask = pin_to_mask(pin);
	173
	174	if (!pio)
	175	return -EINVAL;
	176
	177	__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
	178	return 0;
	179	}
	180	EXPORT_SYMBOL(at91_set_multi_drive);
	181
73a59c1c SP	182	/--------------------------------------------------------------------------/
73a59c1c SP	183
73a59c1c SP	184	/*
	185	* assuming the pin is muxed as a gpio output, set its value.
	186	*/
	187	int at91_set_gpio_value(unsigned pin, int value)
	188	{
	189	void __iomem *pio = pin_to_controller(pin);
	190	unsigned mask = pin_to_mask(pin);
	191
	192	if (!pio)
	193	return -EINVAL;
	194	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
	195	return 0;
	196	}
	197	EXPORT_SYMBOL(at91_set_gpio_value);
	198
	199
	200	/*
	201	* read the pin's value (works even if it's not muxed as a gpio).
	202	*/
	203	int at91_get_gpio_value(unsigned pin)
	204	{
	205	void __iomem *pio = pin_to_controller(pin);
	206	unsigned mask = pin_to_mask(pin);
	207	u32 pdsr;
	208
	209	if (!pio)
	210	return -EINVAL;
	211	pdsr = __raw_readl(pio + PIO_PDSR);
	212	return (pdsr & mask) != 0;
	213	}
	214	EXPORT_SYMBOL(at91_get_gpio_value);
	215
	216	/--------------------------------------------------------------------------/
	217
814138ff AV	218	#ifdef CONFIG_PM
814138ff AV	219
f2173834 AV	220	static u32 wakeups[MAX_GPIO_BANKS];
f2173834 AV	221	static u32 backups[MAX_GPIO_BANKS];
814138ff AV	222
	223	static int gpio_irq_set_wake(unsigned pin, unsigned state)
	224	{
	225	unsigned mask = pin_to_mask(pin);
3ea163e4	226	unsigned bank = (pin - PIN_BASE) / 32;
814138ff	227
3ea163e4	228	if (unlikely(bank >= MAX_GPIO_BANKS))
814138ff AV	229	return -EINVAL;
	230
	231	if (state)
3ea163e4	232	wakeups[bank] \|= mask;
814138ff	233	else
3ea163e4 AV	234	wakeups[bank] &= ~mask;
	235
	236	set_irq_wake(gpio[bank].id, state);
814138ff AV	237
	238	return 0;
	239	}
	240
	241	void at91_gpio_suspend(void)
	242	{
	243	int i;
	244
f2173834 AV	245	for (i = 0; i < gpio_banks; i++) {
f2173834 AV	246	u32 pio = gpio[i].offset;
814138ff	247
814138ff	248	backups[i] = at91_sys_read(pio + PIO_IMR);
f2173834 AV	249	at91_sys_write(pio + PIO_IDR, backups[i]);
f2173834 AV	250	at91_sys_write(pio + PIO_IER, wakeups[i]);
814138ff	251
3ea163e4 AV	252	if (!wakeups[i])
	253	clk_disable(gpio[i].clock);
	254	else {
814138ff	255	#ifdef CONFIG_PM_DEBUG
3ea163e4	256	printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
814138ff AV	257	#endif
	258	}
	259	}
	260	}
	261
	262	void at91_gpio_resume(void)
	263	{
	264	int i;
	265
f2173834 AV	266	for (i = 0; i < gpio_banks; i++) {
f2173834 AV	267	u32 pio = gpio[i].offset;
814138ff	268
3ea163e4 AV	269	if (!wakeups[i])
	270	clk_enable(gpio[i].clock);
	271
f2173834 AV	272	at91_sys_write(pio + PIO_IDR, wakeups[i]);
f2173834 AV	273	at91_sys_write(pio + PIO_IER, backups[i]);
f2173834	274	}
814138ff AV	275	}
	276
	277	#else
	278	#define gpio_irq_set_wake NULL
	279	#endif
	280
73a59c1c SP	281
	282	/* Several AIC controller irqs are dispatched through this GPIO handler.
	283	* To use any AT91_PIN_* as an externally triggered IRQ, first call
	284	* at91_set_gpio_input() then maybe enable its glitch filter.
	285	* Then just request_irq() with the pin ID; it works like any ARM IRQ
	286	* handler, though it always triggers on rising and falling edges.
	287	*
	288	* Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
	289	* configuring them with at91_set_a_periph() or at91_set_b_periph().
	290	* IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
	291	*/
	292
	293	static void gpio_irq_mask(unsigned pin)
	294	{
	295	void __iomem *pio = pin_to_controller(pin);
	296	unsigned mask = pin_to_mask(pin);
	297
	298	if (pio)
	299	__raw_writel(mask, pio + PIO_IDR);
	300	}
	301
	302	static void gpio_irq_unmask(unsigned pin)
	303	{
	304	void __iomem *pio = pin_to_controller(pin);
	305	unsigned mask = pin_to_mask(pin);
	306
	307	if (pio)
	308	__raw_writel(mask, pio + PIO_IER);
	309	}
	310
	311	static int gpio_irq_type(unsigned pin, unsigned type)
	312	{
	313	return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
	314	}
	315
38c677cb DB	316	static struct irq_chip gpio_irqchip = {
38c677cb DB	317	.name = "GPIO",
73a59c1c SP	318	.mask = gpio_irq_mask,
	319	.unmask = gpio_irq_unmask,
	320	.set_type = gpio_irq_type,
814138ff	321	.set_wake = gpio_irq_set_wake,
73a59c1c SP	322	};
73a59c1c SP	323
10dd5ce2	324	static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
73a59c1c SP	325	{
73a59c1c SP	326	unsigned pin;
10dd5ce2	327	struct irq_desc *gpio;
73a59c1c SP	328	void __iomem *pio;
	329	u32 isr;
	330
07d265dd	331	pio = get_irq_chip_data(irq);
73a59c1c SP	332
	333	/* temporarily mask (level sensitive) parent IRQ */
	334	desc->chip->ack(irq);
	335	for (;;) {
814138ff	336	/* reading ISR acks the pending (edge triggered) GPIO interrupt */
73a59c1c SP	337	isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
	338	if (!isr)
	339	break;
	340
07d265dd	341	pin = (unsigned) get_irq_data(irq);
73a59c1c SP	342	gpio = &irq_desc[pin];
	343
	344	while (isr) {
abbea718	345	if (isr & 1) {
07d265dd	346	if (unlikely(gpio->depth)) {
abbea718 AV	347	/*
	348	* The core ARM interrupt handler lazily disables IRQs so
	349	* another IRQ must be generated before it actually gets
	350	* here to be disabled on the GPIO controller.
	351	*/
	352	gpio_irq_mask(pin);
	353	}
	354	else
0cd61b68	355	desc_handle_irq(pin, gpio);
abbea718	356	}
73a59c1c SP	357	pin++;
	358	gpio++;
	359	isr >>= 1;
	360	}
	361	}
	362	desc->chip->unmask(irq);
	363	/* now it may re-trigger */
	364	}
	365
f2173834 AV	366	/--------------------------------------------------------------------------/
	367
	368	/*
	369	* Called from the processor-specific init to enable GPIO interrupt support.
	370	*/
	371	void __init at91_gpio_irq_setup(void)
73a59c1c	372	{
f2173834	373	unsigned pioc, pin;
73a59c1c	374
f2173834 AV	375	for (pioc = 0, pin = PIN_BASE;
	376	pioc < gpio_banks;
	377	pioc++) {
73a59c1c	378	void __iomem *controller;
f2173834	379	unsigned id = gpio[pioc].id;
73a59c1c SP	380	unsigned i;
73a59c1c SP	381
f2173834 AV	382	clk_enable(gpio[pioc].clock); /* enable PIO controller's clock */
	383
	384	controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset;
73a59c1c SP	385	__raw_writel(~0, controller + PIO_IDR);
	386
	387	set_irq_data(id, (void *) pin);
10dd5ce2	388	set_irq_chip_data(id, controller);
73a59c1c SP	389
73a59c1c SP	390	for (i = 0; i < 32; i++, pin++) {
814138ff AV	391	/*
	392	* Can use the "simple" and not "edge" handler since it's
	393	* shorter, and the AIC handles interupts sanely.
	394	*/
73a59c1c	395	set_irq_chip(pin, &gpio_irqchip);
10dd5ce2	396	set_irq_handler(pin, handle_simple_irq);
73a59c1c SP	397	set_irq_flags(pin, IRQF_VALID);
	398	}
	399
	400	set_irq_chained_handler(id, gpio_irq_handler);
73a59c1c	401	}
f2173834 AV	402	pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
	403	}
	404
	405	/*
	406	* Called from the processor-specific init to enable GPIO pin support.
	407	*/
	408	void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
	409	{
	410	BUG_ON(nr_banks > MAX_GPIO_BANKS);
	411
	412	gpio = data;
	413	gpio_banks = nr_banks;
73a59c1c	414	}