[deliverable/linux.git] / arch / arm / mach-clps7500 / core.c

/*
 *  linux/arch/arm/mach-clps7500/core.c
 *
 *  Copyright (C) 1998 Russell King
 *  Copyright (C) 1999 Nexus Electronics Ltd
 *
 * Extra MM routines for CL7500 architecture
 */
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/list.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial_8250.h>
#include <linux/io.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>

#include <mach/hardware.h>
#include <asm/hardware/iomd.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

unsigned int vram_size;

static void cl7500_ack_irq_a(unsigned int irq)
{
	unsigned int val, mask;

	mask = 1 << irq;
	val = iomd_readb(IOMD_IRQMASKA);
	iomd_writeb(val & ~mask, IOMD_IRQMASKA);
	iomd_writeb(mask, IOMD_IRQCLRA);
}

static void cl7500_mask_irq_a(unsigned int irq)
{
	unsigned int val, mask;

	mask = 1 << irq;
	val = iomd_readb(IOMD_IRQMASKA);
	iomd_writeb(val & ~mask, IOMD_IRQMASKA);
}

static void cl7500_unmask_irq_a(unsigned int irq)
{
	unsigned int val, mask;

	mask = 1 << irq;
	val = iomd_readb(IOMD_IRQMASKA);
	iomd_writeb(val | mask, IOMD_IRQMASKA);
}

static struct irq_chip clps7500_a_chip = {
	.ack	= cl7500_ack_irq_a,
	.mask	= cl7500_mask_irq_a,
	.unmask	= cl7500_unmask_irq_a,
};

static void cl7500_mask_irq_b(unsigned int irq)
{
	unsigned int val, mask;

	mask = 1 << (irq & 7);
	val = iomd_readb(IOMD_IRQMASKB);
	iomd_writeb(val & ~mask, IOMD_IRQMASKB);
}

static void cl7500_unmask_irq_b(unsigned int irq)
{
	unsigned int val, mask;

	mask = 1 << (irq & 7);
	val = iomd_readb(IOMD_IRQMASKB);
	iomd_writeb(val | mask, IOMD_IRQMASKB);
}

static struct irq_chip clps7500_b_chip = {
	.ack	= cl7500_mask_irq_b,
	.mask	= cl7500_mask_irq_b,
	.unmask	= cl7500_unmask_irq_b,
};

static void cl7500_mask_irq_c(unsigned int irq)
{
	unsigned int val, mask;

	mask = 1 << (irq & 7);
	val = iomd_readb(IOMD_IRQMASKC);
	iomd_writeb(val & ~mask, IOMD_IRQMASKC);
}

static void cl7500_unmask_irq_c(unsigned int irq)
{
	unsigned int val, mask;

	mask = 1 << (irq & 7);
	val = iomd_readb(IOMD_IRQMASKC);
	iomd_writeb(val | mask, IOMD_IRQMASKC);
}

static struct irq_chip clps7500_c_chip = {
	.ack	= cl7500_mask_irq_c,
	.mask	= cl7500_mask_irq_c,
	.unmask	= cl7500_unmask_irq_c,
};

static void cl7500_mask_irq_d(unsigned int irq)
{
	unsigned int val, mask;

	mask = 1 << (irq & 7);
	val = iomd_readb(IOMD_IRQMASKD);
	iomd_writeb(val & ~mask, IOMD_IRQMASKD);
}

static void cl7500_unmask_irq_d(unsigned int irq)
{
	unsigned int val, mask;

	mask = 1 << (irq & 7);
	val = iomd_readb(IOMD_IRQMASKD);
	iomd_writeb(val | mask, IOMD_IRQMASKD);
}

static struct irq_chip clps7500_d_chip = {
	.ack	= cl7500_mask_irq_d,
	.mask	= cl7500_mask_irq_d,
	.unmask	= cl7500_unmask_irq_d,
};

static void cl7500_mask_irq_dma(unsigned int irq)
{
	unsigned int val, mask;

	mask = 1 << (irq & 7);
	val = iomd_readb(IOMD_DMAMASK);
	iomd_writeb(val & ~mask, IOMD_DMAMASK);
}

static void cl7500_unmask_irq_dma(unsigned int irq)
{
	unsigned int val, mask;

	mask = 1 << (irq & 7);
	val = iomd_readb(IOMD_DMAMASK);
	iomd_writeb(val | mask, IOMD_DMAMASK);
}

static struct irq_chip clps7500_dma_chip = {
	.ack	= cl7500_mask_irq_dma,
	.mask	= cl7500_mask_irq_dma,
	.unmask	= cl7500_unmask_irq_dma,
};

static void cl7500_mask_irq_fiq(unsigned int irq)
{
	unsigned int val, mask;

	mask = 1 << (irq & 7);
	val = iomd_readb(IOMD_FIQMASK);
	iomd_writeb(val & ~mask, IOMD_FIQMASK);
}

static void cl7500_unmask_irq_fiq(unsigned int irq)
{
	unsigned int val, mask;

	mask = 1 << (irq & 7);
	val = iomd_readb(IOMD_FIQMASK);
	iomd_writeb(val | mask, IOMD_FIQMASK);
}

static struct irq_chip clps7500_fiq_chip = {
	.ack	= cl7500_mask_irq_fiq,
	.mask	= cl7500_mask_irq_fiq,
	.unmask	= cl7500_unmask_irq_fiq,
};

static void cl7500_no_action(unsigned int irq)
{
}

static struct irq_chip clps7500_no_chip = {
	.ack	= cl7500_no_action,
	.mask	= cl7500_no_action,
	.unmask	= cl7500_no_action,
};

static struct irqaction irq_isa = {
	.handler = no_action,
	.mask = CPU_MASK_NONE,
	.name = "isa",
};

static void __init clps7500_init_irq(void)
{
	unsigned int irq, flags;

	iomd_writeb(0, IOMD_IRQMASKA);
	iomd_writeb(0, IOMD_IRQMASKB);
	iomd_writeb(0, IOMD_FIQMASK);
	iomd_writeb(0, IOMD_DMAMASK);

	for (irq = 0; irq < NR_IRQS; irq++) {
		flags = IRQF_VALID;

		if (irq <= 6 || (irq >= 9 && irq <= 15) ||
		    (irq >= 48 && irq <= 55))
			flags |= IRQF_PROBE;

		switch (irq) {
		case 0 ... 7:
			set_irq_chip(irq, &clps7500_a_chip);
			set_irq_handler(irq, handle_level_irq);
			set_irq_flags(irq, flags);
			break;

		case 8 ... 15:
			set_irq_chip(irq, &clps7500_b_chip);
			set_irq_handler(irq, handle_level_irq);
			set_irq_flags(irq, flags);
			break;

		case 16 ... 22:
			set_irq_chip(irq, &clps7500_dma_chip);
			set_irq_handler(irq, handle_level_irq);
			set_irq_flags(irq, flags);
			break;

		case 24 ... 31:
			set_irq_chip(irq, &clps7500_c_chip);
			set_irq_handler(irq, handle_level_irq);
			set_irq_flags(irq, flags);
			break;

		case 40 ... 47:
			set_irq_chip(irq, &clps7500_d_chip);
			set_irq_handler(irq, handle_level_irq);
			set_irq_flags(irq, flags);
			break;

		case 48 ... 55:
			set_irq_chip(irq, &clps7500_no_chip);
			set_irq_handler(irq, handle_level_irq);
			set_irq_flags(irq, flags);
			break;

		case 64 ... 72:
			set_irq_chip(irq, &clps7500_fiq_chip);
			set_irq_handler(irq, handle_level_irq);
			set_irq_flags(irq, flags);
			break;
		}
	}

	setup_irq(IRQ_ISA, &irq_isa);
}

static struct map_desc cl7500_io_desc[] __initdata = {
	{ 	/* IO space	*/
		.virtual	= (unsigned long)IO_BASE,
		.pfn		= __phys_to_pfn(IO_START),
		.length		= IO_SIZE,
		.type		= MT_DEVICE
	}, {	/* ISA space	*/
		.virtual	= ISA_BASE,
		.pfn		= __phys_to_pfn(ISA_START),
		.length		= ISA_SIZE,
		.type		= MT_DEVICE
	}, {	/* Flash	*/
		.virtual	= CLPS7500_FLASH_BASE,
		.pfn		= __phys_to_pfn(CLPS7500_FLASH_START),
		.length		= CLPS7500_FLASH_SIZE,
		.type		= MT_DEVICE
	}, {	/* LED		*/
		.virtual	= LED_BASE,
		.pfn		= __phys_to_pfn(LED_START),
		.length		= LED_SIZE,
		.type		= MT_DEVICE
	}
};

static void __init clps7500_map_io(void)
{
	iotable_init(cl7500_io_desc, ARRAY_SIZE(cl7500_io_desc));
}

extern void ioctime_init(void);
extern unsigned long ioc_timer_gettimeoffset(void);

static irqreturn_t
clps7500_timer_interrupt(int irq, void *dev_id)
{
	timer_tick();

	/* Why not using do_leds interface?? */
	{
		/* Twinkle the lights. */
		static int count, state = 0xff00;
		if (count-- == 0) {
			state ^= 0x100;
			count = 25;
			*((volatile unsigned int *)LED_ADDRESS) = state;
		}
	}

	return IRQ_HANDLED;
}

static struct irqaction clps7500_timer_irq = {
	.name		= "CLPS7500 Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= clps7500_timer_interrupt,
};

/*
 * Set up timer interrupt.
 */
static void __init clps7500_timer_init(void)
{
	ioctime_init();
	setup_irq(IRQ_TIMER, &clps7500_timer_irq);
}

static struct sys_timer clps7500_timer = {
	.init		= clps7500_timer_init,
	.offset		= ioc_timer_gettimeoffset,
};

static struct plat_serial8250_port serial_platform_data[] = {
	{
		.mapbase	= 0x03010fe0,
		.irq		= 10,
		.uartclk	= 1843200,
		.regshift	= 2,
		.iotype		= UPIO_MEM,
		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
	},
	{
		.mapbase	= 0x03010be0,
		.irq		= 0,
		.uartclk	= 1843200,
		.regshift	= 2,
		.iotype		= UPIO_MEM,
		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
	},
	{
		.iobase		= ISASLOT_IO + 0x2e8,
		.irq		= 41,
		.uartclk	= 1843200,
		.regshift	= 0,
		.iotype		= UPIO_PORT,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
	},
	{
		.iobase		= ISASLOT_IO + 0x3e8,
		.irq		= 40,
		.uartclk	= 1843200,
		.regshift	= 0,
		.iotype		= UPIO_PORT,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
	},
	{ },
};

static struct platform_device serial_device = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= serial_platform_data,
	},
};

static void __init clps7500_init(void)
{
	platform_device_register(&serial_device);
}

MACHINE_START(CLPS7500, "CL-PS7500")
	/* Maintainer: Philip Blundell */
	.phys_io	= 0x03000000,
	.io_pg_offst	= ((0xe0000000) >> 18) & 0xfffc,
	.map_io		= clps7500_map_io,
	.init_irq	= clps7500_init_irq,
	.init_machine	= clps7500_init,
	.timer		= &clps7500_timer,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-clps7500/core.c
	3	*
	4	* Copyright (C) 1998 Russell King
	5	* Copyright (C) 1999 Nexus Electronics Ltd
	6	*
	7	* Extra MM routines for CL7500 architecture
	8	*/
	9	#include <linux/kernel.h>
	10	#include <linux/types.h>
	11	#include <linux/interrupt.h>
cb03f87c	12	#include <linux/irq.h>
1da177e4 LT	13	#include <linux/list.h>
	14	#include <linux/sched.h>
	15	#include <linux/init.h>
	16	#include <linux/device.h>
	17	#include <linux/serial_8250.h>
fced80c7	18	#include <linux/io.h>
1da177e4 LT	19
	20	#include <asm/mach/arch.h>
	21	#include <asm/mach/map.h>
	22	#include <asm/mach/irq.h>
	23	#include <asm/mach/time.h>
	24
a09e64fb	25	#include <mach/hardware.h>
1da177e4	26	#include <asm/hardware/iomd.h>
1da177e4 LT	27	#include <asm/irq.h>
	28	#include <asm/mach-types.h>
	29
05216219 RK	30	unsigned int vram_size;
05216219 RK	31
1da177e4 LT	32	static void cl7500_ack_irq_a(unsigned int irq)
	33	{
	34	unsigned int val, mask;
	35
	36	mask = 1 << irq;
	37	val = iomd_readb(IOMD_IRQMASKA);
	38	iomd_writeb(val & ~mask, IOMD_IRQMASKA);
	39	iomd_writeb(mask, IOMD_IRQCLRA);
	40	}
	41
	42	static void cl7500_mask_irq_a(unsigned int irq)
	43	{
	44	unsigned int val, mask;
	45
	46	mask = 1 << irq;
	47	val = iomd_readb(IOMD_IRQMASKA);
	48	iomd_writeb(val & ~mask, IOMD_IRQMASKA);
	49	}
	50
	51	static void cl7500_unmask_irq_a(unsigned int irq)
	52	{
	53	unsigned int val, mask;
	54
	55	mask = 1 << irq;
	56	val = iomd_readb(IOMD_IRQMASKA);
	57	iomd_writeb(val \| mask, IOMD_IRQMASKA);
	58	}
	59
10dd5ce2	60	static struct irq_chip clps7500_a_chip = {
1da177e4 LT	61	.ack = cl7500_ack_irq_a,
	62	.mask = cl7500_mask_irq_a,
	63	.unmask = cl7500_unmask_irq_a,
	64	};
	65
	66	static void cl7500_mask_irq_b(unsigned int irq)
	67	{
	68	unsigned int val, mask;
	69
	70	mask = 1 << (irq & 7);
	71	val = iomd_readb(IOMD_IRQMASKB);
	72	iomd_writeb(val & ~mask, IOMD_IRQMASKB);
	73	}
	74
	75	static void cl7500_unmask_irq_b(unsigned int irq)
	76	{
	77	unsigned int val, mask;
	78
	79	mask = 1 << (irq & 7);
	80	val = iomd_readb(IOMD_IRQMASKB);
	81	iomd_writeb(val \| mask, IOMD_IRQMASKB);
	82	}
	83
10dd5ce2	84	static struct irq_chip clps7500_b_chip = {
1da177e4 LT	85	.ack = cl7500_mask_irq_b,
	86	.mask = cl7500_mask_irq_b,
	87	.unmask = cl7500_unmask_irq_b,
	88	};
	89
	90	static void cl7500_mask_irq_c(unsigned int irq)
	91	{
	92	unsigned int val, mask;
	93
	94	mask = 1 << (irq & 7);
	95	val = iomd_readb(IOMD_IRQMASKC);
	96	iomd_writeb(val & ~mask, IOMD_IRQMASKC);
	97	}
	98
	99	static void cl7500_unmask_irq_c(unsigned int irq)
	100	{
	101	unsigned int val, mask;
	102
	103	mask = 1 << (irq & 7);
	104	val = iomd_readb(IOMD_IRQMASKC);
	105	iomd_writeb(val \| mask, IOMD_IRQMASKC);
	106	}
	107
10dd5ce2	108	static struct irq_chip clps7500_c_chip = {
1da177e4 LT	109	.ack = cl7500_mask_irq_c,
	110	.mask = cl7500_mask_irq_c,
	111	.unmask = cl7500_unmask_irq_c,
	112	};
	113
	114	static void cl7500_mask_irq_d(unsigned int irq)
	115	{
	116	unsigned int val, mask;
	117
	118	mask = 1 << (irq & 7);
	119	val = iomd_readb(IOMD_IRQMASKD);
	120	iomd_writeb(val & ~mask, IOMD_IRQMASKD);
	121	}
	122
	123	static void cl7500_unmask_irq_d(unsigned int irq)
	124	{
	125	unsigned int val, mask;
	126
	127	mask = 1 << (irq & 7);
	128	val = iomd_readb(IOMD_IRQMASKD);
	129	iomd_writeb(val \| mask, IOMD_IRQMASKD);
	130	}
	131
10dd5ce2	132	static struct irq_chip clps7500_d_chip = {
1da177e4 LT	133	.ack = cl7500_mask_irq_d,
	134	.mask = cl7500_mask_irq_d,
	135	.unmask = cl7500_unmask_irq_d,
	136	};
	137
	138	static void cl7500_mask_irq_dma(unsigned int irq)
	139	{
	140	unsigned int val, mask;
	141
	142	mask = 1 << (irq & 7);
	143	val = iomd_readb(IOMD_DMAMASK);
	144	iomd_writeb(val & ~mask, IOMD_DMAMASK);
	145	}
	146
	147	static void cl7500_unmask_irq_dma(unsigned int irq)
	148	{
	149	unsigned int val, mask;
	150
	151	mask = 1 << (irq & 7);
	152	val = iomd_readb(IOMD_DMAMASK);
	153	iomd_writeb(val \| mask, IOMD_DMAMASK);
	154	}
	155
10dd5ce2	156	static struct irq_chip clps7500_dma_chip = {
1da177e4 LT	157	.ack = cl7500_mask_irq_dma,
	158	.mask = cl7500_mask_irq_dma,
	159	.unmask = cl7500_unmask_irq_dma,
	160	};
	161
	162	static void cl7500_mask_irq_fiq(unsigned int irq)
	163	{
	164	unsigned int val, mask;
	165
	166	mask = 1 << (irq & 7);
	167	val = iomd_readb(IOMD_FIQMASK);
	168	iomd_writeb(val & ~mask, IOMD_FIQMASK);
	169	}
	170
	171	static void cl7500_unmask_irq_fiq(unsigned int irq)
	172	{
	173	unsigned int val, mask;
	174
	175	mask = 1 << (irq & 7);
	176	val = iomd_readb(IOMD_FIQMASK);
	177	iomd_writeb(val \| mask, IOMD_FIQMASK);
	178	}
	179
10dd5ce2	180	static struct irq_chip clps7500_fiq_chip = {
1da177e4 LT	181	.ack = cl7500_mask_irq_fiq,
	182	.mask = cl7500_mask_irq_fiq,
	183	.unmask = cl7500_unmask_irq_fiq,
	184	};
	185
	186	static void cl7500_no_action(unsigned int irq)
	187	{
	188	}
	189
10dd5ce2	190	static struct irq_chip clps7500_no_chip = {
1da177e4 LT	191	.ack = cl7500_no_action,
	192	.mask = cl7500_no_action,
	193	.unmask = cl7500_no_action,
	194	};
	195
1a10497c TG	196	static struct irqaction irq_isa = {
	197	.handler = no_action,
	198	.mask = CPU_MASK_NONE,
	199	.name = "isa",
	200	};
1da177e4 LT	201
	202	static void __init clps7500_init_irq(void)
	203	{
	204	unsigned int irq, flags;
	205
	206	iomd_writeb(0, IOMD_IRQMASKA);
	207	iomd_writeb(0, IOMD_IRQMASKB);
	208	iomd_writeb(0, IOMD_FIQMASK);
	209	iomd_writeb(0, IOMD_DMAMASK);
	210
	211	for (irq = 0; irq < NR_IRQS; irq++) {
	212	flags = IRQF_VALID;
	213
	214	if (irq <= 6 \|\| (irq >= 9 && irq <= 15) \|\|
	215	(irq >= 48 && irq <= 55))
	216	flags \|= IRQF_PROBE;
	217
	218	switch (irq) {
	219	case 0 ... 7:
	220	set_irq_chip(irq, &clps7500_a_chip);
10dd5ce2	221	set_irq_handler(irq, handle_level_irq);
1da177e4 LT	222	set_irq_flags(irq, flags);
	223	break;
	224
	225	case 8 ... 15:
	226	set_irq_chip(irq, &clps7500_b_chip);
10dd5ce2	227	set_irq_handler(irq, handle_level_irq);
1da177e4 LT	228	set_irq_flags(irq, flags);
	229	break;
	230
	231	case 16 ... 22:
	232	set_irq_chip(irq, &clps7500_dma_chip);
10dd5ce2	233	set_irq_handler(irq, handle_level_irq);
1da177e4 LT	234	set_irq_flags(irq, flags);
	235	break;
	236
	237	case 24 ... 31:
	238	set_irq_chip(irq, &clps7500_c_chip);
10dd5ce2	239	set_irq_handler(irq, handle_level_irq);
1da177e4 LT	240	set_irq_flags(irq, flags);
	241	break;
	242
	243	case 40 ... 47:
	244	set_irq_chip(irq, &clps7500_d_chip);
10dd5ce2	245	set_irq_handler(irq, handle_level_irq);
1da177e4 LT	246	set_irq_flags(irq, flags);
	247	break;
	248
	249	case 48 ... 55:
	250	set_irq_chip(irq, &clps7500_no_chip);
10dd5ce2	251	set_irq_handler(irq, handle_level_irq);
1da177e4 LT	252	set_irq_flags(irq, flags);
	253	break;
	254
	255	case 64 ... 72:
	256	set_irq_chip(irq, &clps7500_fiq_chip);
10dd5ce2	257	set_irq_handler(irq, handle_level_irq);
1da177e4 LT	258	set_irq_flags(irq, flags);
	259	break;
	260	}
	261	}
	262
	263	setup_irq(IRQ_ISA, &irq_isa);
	264	}
	265
	266	static struct map_desc cl7500_io_desc[] __initdata = {
d157e9ec	267	{ /* IO space */
9b73fcf8	268	.virtual = (unsigned long)IO_BASE,
d157e9ec DS	269	.pfn = __phys_to_pfn(IO_START),
	270	.length = IO_SIZE,
	271	.type = MT_DEVICE
	272	}, { /* ISA space */
	273	.virtual = ISA_BASE,
	274	.pfn = __phys_to_pfn(ISA_START),
	275	.length = ISA_SIZE,
	276	.type = MT_DEVICE
	277	}, { /* Flash */
d9a682a5 RK	278	.virtual = CLPS7500_FLASH_BASE,
	279	.pfn = __phys_to_pfn(CLPS7500_FLASH_START),
	280	.length = CLPS7500_FLASH_SIZE,
d157e9ec DS	281	.type = MT_DEVICE
	282	}, { /* LED */
	283	.virtual = LED_BASE,
	284	.pfn = __phys_to_pfn(LED_START),
	285	.length = LED_SIZE,
	286	.type = MT_DEVICE
	287	}
1da177e4 LT	288	};
	289
	290	static void __init clps7500_map_io(void)
	291	{
	292	iotable_init(cl7500_io_desc, ARRAY_SIZE(cl7500_io_desc));
	293	}
	294
	295	extern void ioctime_init(void);
	296	extern unsigned long ioc_timer_gettimeoffset(void);
	297
	298	static irqreturn_t
0cd61b68	299	clps7500_timer_interrupt(int irq, void *dev_id)
1da177e4	300	{
0cd61b68	301	timer_tick();
1da177e4 LT	302
	303	/* Why not using do_leds interface?? */
	304	{
	305	/* Twinkle the lights. */
	306	static int count, state = 0xff00;
	307	if (count-- == 0) {
	308	state ^= 0x100;
	309	count = 25;
	310	((volatile unsigned int )LED_ADDRESS) = state;
	311	}
	312	}
	313
1da177e4 LT	314	return IRQ_HANDLED;
	315	}
	316
	317	static struct irqaction clps7500_timer_irq = {
	318	.name = "CLPS7500 Timer Tick",
b30fabad	319	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
09b8b5f8	320	.handler = clps7500_timer_interrupt,
1da177e4 LT	321	};
	322
	323	/*
	324	* Set up timer interrupt.
	325	*/
	326	static void __init clps7500_timer_init(void)
	327	{
	328	ioctime_init();
	329	setup_irq(IRQ_TIMER, &clps7500_timer_irq);
	330	}
	331
	332	static struct sys_timer clps7500_timer = {
	333	.init = clps7500_timer_init,
	334	.offset = ioc_timer_gettimeoffset,
	335	};
	336
	337	static struct plat_serial8250_port serial_platform_data[] = {
	338	{
	339	.mapbase = 0x03010fe0,
	340	.irq = 10,
	341	.uartclk = 1843200,
	342	.regshift = 2,
	343	.iotype = UPIO_MEM,
	344	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP \| UPF_SKIP_TEST,
	345	},
	346	{
	347	.mapbase = 0x03010be0,
	348	.irq = 0,
	349	.uartclk = 1843200,
	350	.regshift = 2,
	351	.iotype = UPIO_MEM,
	352	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP \| UPF_SKIP_TEST,
	353	},
	354	{
	355	.iobase = ISASLOT_IO + 0x2e8,
	356	.irq = 41,
	357	.uartclk = 1843200,
	358	.regshift = 0,
	359	.iotype = UPIO_PORT,
	360	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
	361	},
	362	{
	363	.iobase = ISASLOT_IO + 0x3e8,
	364	.irq = 40,
	365	.uartclk = 1843200,
	366	.regshift = 0,
	367	.iotype = UPIO_PORT,
	368	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST,
	369	},
	370	{ },
	371	};
	372
	373	static struct platform_device serial_device = {
	374	.name = "serial8250",
6df29deb	375	.id = PLAT8250_DEV_PLATFORM,
1da177e4 LT	376	.dev = {
	377	.platform_data = serial_platform_data,
	378	},
	379	};
	380
	381	static void __init clps7500_init(void)
	382	{
	383	platform_device_register(&serial_device);
	384	}
	385
	386	MACHINE_START(CLPS7500, "CL-PS7500")
e9dea0c6	387	/* Maintainer: Philip Blundell */
e9dea0c6 RK	388	.phys_io = 0x03000000,
	389	.io_pg_offst = ((0xe0000000) >> 18) & 0xfffc,
	390	.map_io = clps7500_map_io,
	391	.init_irq = clps7500_init_irq,
	392	.init_machine = clps7500_init,
	393	.timer = &clps7500_timer,
1da177e4 LT	394	MACHINE_END
1da177e4 LT	395