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37dd0095 SP |
1 | /* |
2 | * TI DaVinci DM365 EVM board support | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments Incorporated | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | #include <linux/kernel.h> | |
37dd0095 | 16 | #include <linux/init.h> |
42d399e4 | 17 | #include <linux/err.h> |
37dd0095 SP |
18 | #include <linux/i2c.h> |
19 | #include <linux/io.h> | |
20 | #include <linux/clk.h> | |
8ed0a9d4 | 21 | #include <linux/i2c/at24.h> |
ff255c6c | 22 | #include <linux/leds.h> |
37b798da SP |
23 | #include <linux/mtd/mtd.h> |
24 | #include <linux/mtd/partitions.h> | |
25 | #include <linux/mtd/nand.h> | |
990c09d5 | 26 | #include <linux/input.h> |
42d399e4 | 27 | |
37dd0095 SP |
28 | #include <asm/mach-types.h> |
29 | #include <asm/mach/arch.h> | |
42d399e4 | 30 | |
8ed0a9d4 | 31 | #include <mach/mux.h> |
37dd0095 | 32 | #include <mach/dm365.h> |
37dd0095 SP |
33 | #include <mach/common.h> |
34 | #include <mach/i2c.h> | |
37dd0095 | 35 | #include <mach/serial.h> |
a45c8ba3 | 36 | #include <mach/mmc.h> |
37b798da | 37 | #include <mach/nand.h> |
990c09d5 | 38 | #include <mach/keyscan.h> |
37b798da | 39 | |
ff255c6c DB |
40 | static inline int have_imager(void) |
41 | { | |
42 | /* REVISIT when it's supported, trigger via Kconfig */ | |
43 | return 0; | |
44 | } | |
45 | ||
46 | static inline int have_tvp7002(void) | |
47 | { | |
48 | /* REVISIT when it's supported, trigger via Kconfig */ | |
49 | return 0; | |
50 | } | |
51 | ||
52 | ||
37b798da SP |
53 | #define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000 |
54 | #define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 | |
ff255c6c | 55 | #define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 |
37dd0095 | 56 | |
8ed0a9d4 SP |
57 | #define DM365_EVM_PHY_MASK (0x2) |
58 | #define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ | |
59 | ||
ff255c6c DB |
60 | /* |
61 | * A MAX-II CPLD is used for various board control functions. | |
62 | */ | |
63 | #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3)) | |
64 | ||
65 | #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */ | |
66 | #define CPLD_TEST CPLD_OFFSET(0,1) | |
67 | #define CPLD_LEDS CPLD_OFFSET(0,2) | |
68 | #define CPLD_MUX CPLD_OFFSET(0,3) | |
69 | #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */ | |
70 | #define CPLD_POWER CPLD_OFFSET(1,1) | |
71 | #define CPLD_VIDEO CPLD_OFFSET(1,2) | |
72 | #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */ | |
73 | ||
74 | #define CPLD_DILC_OUT CPLD_OFFSET(2,0) | |
75 | #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */ | |
76 | ||
77 | #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2) | |
78 | #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3) | |
79 | #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0) | |
80 | #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1) | |
81 | #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2) | |
82 | #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3) | |
83 | #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0) | |
84 | #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1) | |
85 | #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2) | |
86 | ||
87 | #define CPLD_RESETS CPLD_OFFSET(4,3) | |
88 | ||
89 | #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0) | |
90 | #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1) | |
91 | #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2) | |
92 | #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3) | |
93 | #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0) | |
94 | #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1) | |
95 | ||
96 | static void __iomem *cpld; | |
97 | ||
98 | ||
37b798da SP |
99 | /* NOTE: this is geared for the standard config, with a socketed |
100 | * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you | |
101 | * swap chips with a different block size, partitioning will | |
102 | * need to be changed. This NAND chip MT29F16G08FAA is the default | |
103 | * NAND shipped with the Spectrum Digital DM365 EVM | |
104 | */ | |
105 | #define NAND_BLOCK_SIZE SZ_128K | |
106 | ||
107 | static struct mtd_partition davinci_nand_partitions[] = { | |
108 | { | |
109 | /* UBL (a few copies) plus U-Boot */ | |
110 | .name = "bootloader", | |
111 | .offset = 0, | |
112 | .size = 28 * NAND_BLOCK_SIZE, | |
113 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
114 | }, { | |
115 | /* U-Boot environment */ | |
116 | .name = "params", | |
117 | .offset = MTDPART_OFS_APPEND, | |
118 | .size = 2 * NAND_BLOCK_SIZE, | |
119 | .mask_flags = 0, | |
120 | }, { | |
121 | .name = "kernel", | |
122 | .offset = MTDPART_OFS_APPEND, | |
123 | .size = SZ_4M, | |
124 | .mask_flags = 0, | |
125 | }, { | |
126 | .name = "filesystem1", | |
127 | .offset = MTDPART_OFS_APPEND, | |
128 | .size = SZ_512M, | |
129 | .mask_flags = 0, | |
130 | }, { | |
131 | .name = "filesystem2", | |
132 | .offset = MTDPART_OFS_APPEND, | |
133 | .size = MTDPART_SIZ_FULL, | |
134 | .mask_flags = 0, | |
135 | } | |
136 | /* two blocks with bad block table (and mirror) at the end */ | |
137 | }; | |
138 | ||
139 | static struct davinci_nand_pdata davinci_nand_data = { | |
140 | .mask_chipsel = BIT(14), | |
141 | .parts = davinci_nand_partitions, | |
142 | .nr_parts = ARRAY_SIZE(davinci_nand_partitions), | |
143 | .ecc_mode = NAND_ECC_HW, | |
144 | .options = NAND_USE_FLASH_BBT, | |
dc4c05a5 | 145 | .ecc_bits = 4, |
37b798da SP |
146 | }; |
147 | ||
148 | static struct resource davinci_nand_resources[] = { | |
149 | { | |
150 | .start = DM365_ASYNC_EMIF_DATA_CE0_BASE, | |
151 | .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, | |
152 | .flags = IORESOURCE_MEM, | |
153 | }, { | |
154 | .start = DM365_ASYNC_EMIF_CONTROL_BASE, | |
155 | .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, | |
156 | .flags = IORESOURCE_MEM, | |
157 | }, | |
158 | }; | |
159 | ||
160 | static struct platform_device davinci_nand_device = { | |
161 | .name = "davinci_nand", | |
162 | .id = 0, | |
163 | .num_resources = ARRAY_SIZE(davinci_nand_resources), | |
164 | .resource = davinci_nand_resources, | |
165 | .dev = { | |
166 | .platform_data = &davinci_nand_data, | |
167 | }, | |
168 | }; | |
169 | ||
8ed0a9d4 SP |
170 | static struct at24_platform_data eeprom_info = { |
171 | .byte_len = (256*1024) / 8, | |
172 | .page_size = 64, | |
173 | .flags = AT24_FLAG_ADDR16, | |
174 | .setup = davinci_get_mac_addr, | |
175 | .context = (void *)0x7f00, | |
176 | }; | |
177 | ||
e9ab3214 MA |
178 | static struct snd_platform_data dm365_evm_snd_data; |
179 | ||
8ed0a9d4 SP |
180 | static struct i2c_board_info i2c_info[] = { |
181 | { | |
182 | I2C_BOARD_INFO("24c256", 0x50), | |
183 | .platform_data = &eeprom_info, | |
184 | }, | |
e9ab3214 MA |
185 | { |
186 | I2C_BOARD_INFO("tlv320aic3x", 0x18), | |
187 | }, | |
8ed0a9d4 SP |
188 | }; |
189 | ||
37dd0095 SP |
190 | static struct davinci_i2c_platform_data i2c_pdata = { |
191 | .bus_freq = 400 /* kHz */, | |
192 | .bus_delay = 0 /* usec */, | |
193 | }; | |
194 | ||
c92b29ec MA |
195 | static int dm365evm_keyscan_enable(struct device *dev) |
196 | { | |
197 | return davinci_cfg_reg(DM365_KEYSCAN); | |
198 | } | |
199 | ||
990c09d5 MA |
200 | static unsigned short dm365evm_keymap[] = { |
201 | KEY_KP2, | |
202 | KEY_LEFT, | |
203 | KEY_EXIT, | |
204 | KEY_DOWN, | |
205 | KEY_ENTER, | |
206 | KEY_UP, | |
207 | KEY_KP1, | |
208 | KEY_RIGHT, | |
209 | KEY_MENU, | |
210 | KEY_RECORD, | |
211 | KEY_REWIND, | |
212 | KEY_KPMINUS, | |
213 | KEY_STOP, | |
214 | KEY_FASTFORWARD, | |
215 | KEY_KPPLUS, | |
216 | KEY_PLAYPAUSE, | |
217 | 0 | |
218 | }; | |
219 | ||
220 | static struct davinci_ks_platform_data dm365evm_ks_data = { | |
c92b29ec | 221 | .device_enable = dm365evm_keyscan_enable, |
990c09d5 MA |
222 | .keymap = dm365evm_keymap, |
223 | .keymapsize = ARRAY_SIZE(dm365evm_keymap), | |
224 | .rep = 1, | |
225 | /* Scan period = strobe + interval */ | |
226 | .strobe = 0x5, | |
227 | .interval = 0x2, | |
228 | .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4, | |
229 | }; | |
990c09d5 | 230 | |
ff255c6c DB |
231 | static int cpld_mmc_get_cd(int module) |
232 | { | |
233 | if (!cpld) | |
234 | return -ENXIO; | |
235 | ||
236 | /* low == card present */ | |
237 | return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0)); | |
238 | } | |
239 | ||
240 | static int cpld_mmc_get_ro(int module) | |
241 | { | |
242 | if (!cpld) | |
243 | return -ENXIO; | |
244 | ||
245 | /* high == card's write protect switch active */ | |
246 | return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1)); | |
247 | } | |
248 | ||
a45c8ba3 | 249 | static struct davinci_mmc_config dm365evm_mmc_config = { |
ff255c6c DB |
250 | .get_cd = cpld_mmc_get_cd, |
251 | .get_ro = cpld_mmc_get_ro, | |
a45c8ba3 SP |
252 | .wires = 4, |
253 | .max_freq = 50000000, | |
254 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, | |
255 | .version = MMC_CTLR_VERSION_2, | |
256 | }; | |
257 | ||
8ed0a9d4 SP |
258 | static void dm365evm_emac_configure(void) |
259 | { | |
260 | /* | |
261 | * EMAC pins are multiplexed with GPIO and UART | |
262 | * Further details are available at the DM365 ARM | |
263 | * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127 | |
264 | */ | |
265 | davinci_cfg_reg(DM365_EMAC_TX_EN); | |
266 | davinci_cfg_reg(DM365_EMAC_TX_CLK); | |
267 | davinci_cfg_reg(DM365_EMAC_COL); | |
268 | davinci_cfg_reg(DM365_EMAC_TXD3); | |
269 | davinci_cfg_reg(DM365_EMAC_TXD2); | |
270 | davinci_cfg_reg(DM365_EMAC_TXD1); | |
271 | davinci_cfg_reg(DM365_EMAC_TXD0); | |
272 | davinci_cfg_reg(DM365_EMAC_RXD3); | |
273 | davinci_cfg_reg(DM365_EMAC_RXD2); | |
274 | davinci_cfg_reg(DM365_EMAC_RXD1); | |
275 | davinci_cfg_reg(DM365_EMAC_RXD0); | |
276 | davinci_cfg_reg(DM365_EMAC_RX_CLK); | |
277 | davinci_cfg_reg(DM365_EMAC_RX_DV); | |
278 | davinci_cfg_reg(DM365_EMAC_RX_ER); | |
279 | davinci_cfg_reg(DM365_EMAC_CRS); | |
280 | davinci_cfg_reg(DM365_EMAC_MDIO); | |
281 | davinci_cfg_reg(DM365_EMAC_MDCLK); | |
282 | ||
283 | /* | |
284 | * EMAC interrupts are multiplexed with GPIO interrupts | |
285 | * Details are available at the DM365 ARM | |
286 | * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 | |
287 | */ | |
288 | davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH); | |
289 | davinci_cfg_reg(DM365_INT_EMAC_RXPULSE); | |
290 | davinci_cfg_reg(DM365_INT_EMAC_TXPULSE); | |
291 | davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE); | |
292 | } | |
293 | ||
a45c8ba3 SP |
294 | static void dm365evm_mmc_configure(void) |
295 | { | |
296 | /* | |
297 | * MMC/SD pins are multiplexed with GPIO and EMIF | |
298 | * Further details are available at the DM365 ARM | |
299 | * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131 | |
300 | */ | |
301 | davinci_cfg_reg(DM365_SD1_CLK); | |
302 | davinci_cfg_reg(DM365_SD1_CMD); | |
303 | davinci_cfg_reg(DM365_SD1_DATA3); | |
304 | davinci_cfg_reg(DM365_SD1_DATA2); | |
305 | davinci_cfg_reg(DM365_SD1_DATA1); | |
306 | davinci_cfg_reg(DM365_SD1_DATA0); | |
307 | } | |
308 | ||
37dd0095 SP |
309 | static void __init evm_init_i2c(void) |
310 | { | |
311 | davinci_init_i2c(&i2c_pdata); | |
8ed0a9d4 | 312 | i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); |
37dd0095 SP |
313 | } |
314 | ||
ff255c6c | 315 | static struct platform_device *dm365_evm_nand_devices[] __initdata = { |
37b798da SP |
316 | &davinci_nand_device, |
317 | }; | |
318 | ||
ff255c6c DB |
319 | static inline int have_leds(void) |
320 | { | |
321 | #ifdef CONFIG_LEDS_CLASS | |
322 | return 1; | |
323 | #else | |
324 | return 0; | |
325 | #endif | |
326 | } | |
327 | ||
328 | struct cpld_led { | |
329 | struct led_classdev cdev; | |
330 | u8 mask; | |
331 | }; | |
332 | ||
333 | static const struct { | |
334 | const char *name; | |
335 | const char *trigger; | |
336 | } cpld_leds[] = { | |
337 | { "dm365evm::ds2", }, | |
338 | { "dm365evm::ds3", }, | |
339 | { "dm365evm::ds4", }, | |
340 | { "dm365evm::ds5", }, | |
341 | { "dm365evm::ds6", "nand-disk", }, | |
342 | { "dm365evm::ds7", "mmc1", }, | |
343 | { "dm365evm::ds8", "mmc0", }, | |
344 | { "dm365evm::ds9", "heartbeat", }, | |
345 | }; | |
346 | ||
347 | static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b) | |
348 | { | |
349 | struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); | |
350 | u8 reg = __raw_readb(cpld + CPLD_LEDS); | |
351 | ||
352 | if (b != LED_OFF) | |
353 | reg &= ~led->mask; | |
354 | else | |
355 | reg |= led->mask; | |
356 | __raw_writeb(reg, cpld + CPLD_LEDS); | |
357 | } | |
358 | ||
359 | static enum led_brightness cpld_led_get(struct led_classdev *cdev) | |
360 | { | |
361 | struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); | |
362 | u8 reg = __raw_readb(cpld + CPLD_LEDS); | |
363 | ||
364 | return (reg & led->mask) ? LED_OFF : LED_FULL; | |
365 | } | |
366 | ||
367 | static int __init cpld_leds_init(void) | |
368 | { | |
369 | int i; | |
370 | ||
371 | if (!have_leds() || !cpld) | |
372 | return 0; | |
373 | ||
374 | /* setup LEDs */ | |
375 | __raw_writeb(0xff, cpld + CPLD_LEDS); | |
376 | for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) { | |
377 | struct cpld_led *led; | |
378 | ||
379 | led = kzalloc(sizeof(*led), GFP_KERNEL); | |
380 | if (!led) | |
381 | break; | |
382 | ||
383 | led->cdev.name = cpld_leds[i].name; | |
384 | led->cdev.brightness_set = cpld_led_set; | |
385 | led->cdev.brightness_get = cpld_led_get; | |
386 | led->cdev.default_trigger = cpld_leds[i].trigger; | |
387 | led->mask = BIT(i); | |
388 | ||
389 | if (led_classdev_register(NULL, &led->cdev) < 0) { | |
390 | kfree(led); | |
391 | break; | |
392 | } | |
393 | } | |
394 | ||
395 | return 0; | |
396 | } | |
397 | /* run after subsys_initcall() for LEDs */ | |
398 | fs_initcall(cpld_leds_init); | |
399 | ||
400 | ||
401 | static void __init evm_init_cpld(void) | |
402 | { | |
403 | u8 mux, resets; | |
404 | const char *label; | |
405 | struct clk *aemif_clk; | |
406 | ||
407 | /* Make sure we can configure the CPLD through CS1. Then | |
408 | * leave it on for later access to MMC and LED registers. | |
409 | */ | |
410 | aemif_clk = clk_get(NULL, "aemif"); | |
411 | if (IS_ERR(aemif_clk)) | |
412 | return; | |
413 | clk_enable(aemif_clk); | |
414 | ||
415 | if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE, | |
416 | "cpld") == NULL) | |
417 | goto fail; | |
418 | cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE); | |
419 | if (!cpld) { | |
420 | release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, | |
421 | SECTION_SIZE); | |
422 | fail: | |
423 | pr_err("ERROR: can't map CPLD\n"); | |
424 | clk_disable(aemif_clk); | |
425 | return; | |
426 | } | |
427 | ||
428 | /* External muxing for some signals */ | |
429 | mux = 0; | |
430 | ||
431 | /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read). | |
432 | * NOTE: SW4 bus width setting must match! | |
433 | */ | |
434 | if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) { | |
435 | /* external keypad mux */ | |
436 | mux |= BIT(7); | |
437 | ||
438 | platform_add_devices(dm365_evm_nand_devices, | |
439 | ARRAY_SIZE(dm365_evm_nand_devices)); | |
440 | } else { | |
441 | /* no OneNAND support yet */ | |
442 | } | |
443 | ||
444 | /* Leave external chips in reset when unused. */ | |
445 | resets = BIT(3) | BIT(2) | BIT(1) | BIT(0); | |
446 | ||
447 | /* Static video input config with SN74CBT16214 1-of-3 mux: | |
448 | * - port b1 == tvp7002 (mux lowbits == 1 or 6) | |
449 | * - port b2 == imager (mux lowbits == 2 or 7) | |
450 | * - port b3 == tvp5146 (mux lowbits == 5) | |
451 | * | |
452 | * Runtime switching could work too, with limitations. | |
453 | */ | |
454 | if (have_imager()) { | |
455 | label = "HD imager"; | |
456 | mux |= 1; | |
457 | ||
458 | /* externally mux MMC1/ENET/AIC33 to imager */ | |
459 | mux |= BIT(6) | BIT(5) | BIT(3); | |
460 | } else { | |
461 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
462 | ||
463 | /* we can use MMC1 ... */ | |
464 | dm365evm_mmc_configure(); | |
465 | davinci_setup_mmc(1, &dm365evm_mmc_config); | |
466 | ||
467 | /* ... and ENET ... */ | |
468 | dm365evm_emac_configure(); | |
469 | soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK; | |
470 | soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY; | |
471 | resets &= ~BIT(3); | |
472 | ||
473 | /* ... and AIC33 */ | |
474 | resets &= ~BIT(1); | |
475 | ||
476 | if (have_tvp7002()) { | |
477 | mux |= 2; | |
478 | resets &= ~BIT(2); | |
479 | label = "tvp7002 HD"; | |
480 | } else { | |
481 | /* default to tvp5146 */ | |
482 | mux |= 5; | |
483 | resets &= ~BIT(0); | |
484 | label = "tvp5146 SD"; | |
485 | } | |
486 | } | |
487 | __raw_writeb(mux, cpld + CPLD_MUX); | |
488 | __raw_writeb(resets, cpld + CPLD_RESETS); | |
489 | pr_info("EVM: %s video input\n", label); | |
490 | ||
491 | /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */ | |
492 | } | |
493 | ||
37dd0095 SP |
494 | static struct davinci_uart_config uart_config __initdata = { |
495 | .enabled_uarts = (1 << 0), | |
496 | }; | |
497 | ||
498 | static void __init dm365_evm_map_io(void) | |
499 | { | |
500 | dm365_init(); | |
501 | } | |
502 | ||
503 | static __init void dm365_evm_init(void) | |
504 | { | |
505 | evm_init_i2c(); | |
506 | davinci_serial_init(&uart_config); | |
8ed0a9d4 SP |
507 | |
508 | dm365evm_emac_configure(); | |
a45c8ba3 SP |
509 | dm365evm_mmc_configure(); |
510 | ||
511 | davinci_setup_mmc(0, &dm365evm_mmc_config); | |
8ed0a9d4 | 512 | |
ff255c6c DB |
513 | /* maybe setup mmc1/etc ... _after_ mmc0 */ |
514 | evm_init_cpld(); | |
e9ab3214 MA |
515 | |
516 | dm365_init_asp(&dm365_evm_snd_data); | |
99381b4f | 517 | dm365_init_rtc(); |
990c09d5 | 518 | dm365_init_ks(&dm365evm_ks_data); |
37dd0095 SP |
519 | } |
520 | ||
521 | static __init void dm365_evm_irq_init(void) | |
522 | { | |
523 | davinci_irq_init(); | |
524 | } | |
525 | ||
526 | MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") | |
527 | .phys_io = IO_PHYS, | |
528 | .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, | |
529 | .boot_params = (0x80000100), | |
530 | .map_io = dm365_evm_map_io, | |
531 | .init_irq = dm365_evm_irq_init, | |
532 | .timer = &davinci_timer, | |
533 | .init_machine = dm365_evm_init, | |
534 | MACHINE_END | |
535 |