[deliverable/linux.git] / arch / arm / mach-davinci / board-dm365-evm.c

/*
 * TI DaVinci DM365 EVM board support
 *
 * Copyright (C) 2009 Texas Instruments Incorporated
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/i2c/at24.h>
#include <linux/leds.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand.h>
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <linux/spi/eeprom.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>

#include <mach/mux.h>
#include <mach/dm365.h>
#include <mach/common.h>
#include <mach/i2c.h>
#include <mach/serial.h>
#include <mach/mmc.h>
#include <mach/nand.h>
#include <mach/keyscan.h>

#include <media/tvp514x.h>

static inline int have_imager(void)
{
	/* REVISIT when it's supported, trigger via Kconfig */
	return 0;
}

static inline int have_tvp7002(void)
{
	/* REVISIT when it's supported, trigger via Kconfig */
	return 0;
}


#define DM365_ASYNC_EMIF_CONTROL_BASE	0x01d10000
#define DM365_ASYNC_EMIF_DATA_CE0_BASE	0x02000000
#define DM365_ASYNC_EMIF_DATA_CE1_BASE	0x04000000

#define DM365_EVM_PHY_MASK		(0x2)
#define DM365_EVM_MDIO_FREQUENCY	(2200000) /* PHY bus frequency */

/*
 * A MAX-II CPLD is used for various board control functions.
 */
#define CPLD_OFFSET(a13a8,a2a1)		(((a13a8) << 10) + ((a2a1) << 3))

#define CPLD_VERSION	CPLD_OFFSET(0,0)	/* r/o */
#define CPLD_TEST	CPLD_OFFSET(0,1)
#define CPLD_LEDS	CPLD_OFFSET(0,2)
#define CPLD_MUX	CPLD_OFFSET(0,3)
#define CPLD_SWITCH	CPLD_OFFSET(1,0)	/* r/o */
#define CPLD_POWER	CPLD_OFFSET(1,1)
#define CPLD_VIDEO	CPLD_OFFSET(1,2)
#define CPLD_CARDSTAT	CPLD_OFFSET(1,3)	/* r/o */

#define CPLD_DILC_OUT	CPLD_OFFSET(2,0)
#define CPLD_DILC_IN	CPLD_OFFSET(2,1)	/* r/o */

#define CPLD_IMG_DIR0	CPLD_OFFSET(2,2)
#define CPLD_IMG_MUX0	CPLD_OFFSET(2,3)
#define CPLD_IMG_MUX1	CPLD_OFFSET(3,0)
#define CPLD_IMG_DIR1	CPLD_OFFSET(3,1)
#define CPLD_IMG_MUX2	CPLD_OFFSET(3,2)
#define CPLD_IMG_MUX3	CPLD_OFFSET(3,3)
#define CPLD_IMG_DIR2	CPLD_OFFSET(4,0)
#define CPLD_IMG_MUX4	CPLD_OFFSET(4,1)
#define CPLD_IMG_MUX5	CPLD_OFFSET(4,2)

#define CPLD_RESETS	CPLD_OFFSET(4,3)

#define CPLD_CCD_DIR1	CPLD_OFFSET(0x3e,0)
#define CPLD_CCD_IO1	CPLD_OFFSET(0x3e,1)
#define CPLD_CCD_DIR2	CPLD_OFFSET(0x3e,2)
#define CPLD_CCD_IO2	CPLD_OFFSET(0x3e,3)
#define CPLD_CCD_DIR3	CPLD_OFFSET(0x3f,0)
#define CPLD_CCD_IO3	CPLD_OFFSET(0x3f,1)

static void __iomem *cpld;


/* NOTE:  this is geared for the standard config, with a socketed
 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
 * swap chips with a different block size, partitioning will
 * need to be changed. This NAND chip MT29F16G08FAA is the default
 * NAND shipped with the Spectrum Digital DM365 EVM
 */
#define NAND_BLOCK_SIZE		SZ_128K

static struct mtd_partition davinci_nand_partitions[] = {
	{
		/* UBL (a few copies) plus U-Boot */
		.name		= "bootloader",
		.offset		= 0,
		.size		= 28 * NAND_BLOCK_SIZE,
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
	}, {
		/* U-Boot environment */
		.name		= "params",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 2 * NAND_BLOCK_SIZE,
		.mask_flags	= 0,
	}, {
		.name		= "kernel",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_4M,
		.mask_flags	= 0,
	}, {
		.name		= "filesystem1",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_512M,
		.mask_flags	= 0,
	}, {
		.name		= "filesystem2",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= 0,
	}
	/* two blocks with bad block table (and mirror) at the end */
};

static struct davinci_nand_pdata davinci_nand_data = {
	.mask_chipsel		= BIT(14),
	.parts			= davinci_nand_partitions,
	.nr_parts		= ARRAY_SIZE(davinci_nand_partitions),
	.ecc_mode		= NAND_ECC_HW,
	.options		= NAND_USE_FLASH_BBT,
	.ecc_bits		= 4,
};

static struct resource davinci_nand_resources[] = {
	{
		.start		= DM365_ASYNC_EMIF_DATA_CE0_BASE,
		.end		= DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= DM365_ASYNC_EMIF_CONTROL_BASE,
		.end		= DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device davinci_nand_device = {
	.name			= "davinci_nand",
	.id			= 0,
	.num_resources		= ARRAY_SIZE(davinci_nand_resources),
	.resource		= davinci_nand_resources,
	.dev			= {
		.platform_data	= &davinci_nand_data,
	},
};

static struct at24_platform_data eeprom_info = {
	.byte_len       = (256*1024) / 8,
	.page_size      = 64,
	.flags          = AT24_FLAG_ADDR16,
	.setup          = davinci_get_mac_addr,
	.context	= (void *)0x7f00,
};

static struct snd_platform_data dm365_evm_snd_data;

static struct i2c_board_info i2c_info[] = {
	{
		I2C_BOARD_INFO("24c256", 0x50),
		.platform_data	= &eeprom_info,
	},
	{
		I2C_BOARD_INFO("tlv320aic3x", 0x18),
	},
};

static struct davinci_i2c_platform_data i2c_pdata = {
	.bus_freq	= 400	/* kHz */,
	.bus_delay	= 0	/* usec */,
};

static int dm365evm_keyscan_enable(struct device *dev)
{
	return davinci_cfg_reg(DM365_KEYSCAN);
}

static unsigned short dm365evm_keymap[] = {
	KEY_KP2,
	KEY_LEFT,
	KEY_EXIT,
	KEY_DOWN,
	KEY_ENTER,
	KEY_UP,
	KEY_KP1,
	KEY_RIGHT,
	KEY_MENU,
	KEY_RECORD,
	KEY_REWIND,
	KEY_KPMINUS,
	KEY_STOP,
	KEY_FASTFORWARD,
	KEY_KPPLUS,
	KEY_PLAYPAUSE,
	0
};

static struct davinci_ks_platform_data dm365evm_ks_data = {
	.device_enable	= dm365evm_keyscan_enable,
	.keymap		= dm365evm_keymap,
	.keymapsize	= ARRAY_SIZE(dm365evm_keymap),
	.rep		= 1,
	/* Scan period = strobe + interval */
	.strobe		= 0x5,
	.interval	= 0x2,
	.matrix_type	= DAVINCI_KEYSCAN_MATRIX_4X4,
};

static int cpld_mmc_get_cd(int module)
{
	if (!cpld)
		return -ENXIO;

	/* low == card present */
	return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
}

static int cpld_mmc_get_ro(int module)
{
	if (!cpld)
		return -ENXIO;

	/* high == card's write protect switch active */
	return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
}

static struct davinci_mmc_config dm365evm_mmc_config = {
	.get_cd		= cpld_mmc_get_cd,
	.get_ro		= cpld_mmc_get_ro,
	.wires		= 4,
	.max_freq	= 50000000,
	.caps		= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
	.version	= MMC_CTLR_VERSION_2,
};

static void dm365evm_emac_configure(void)
{
	/*
	 * EMAC pins are multiplexed with GPIO and UART
	 * Further details are available at the DM365 ARM
	 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
	 */
	davinci_cfg_reg(DM365_EMAC_TX_EN);
	davinci_cfg_reg(DM365_EMAC_TX_CLK);
	davinci_cfg_reg(DM365_EMAC_COL);
	davinci_cfg_reg(DM365_EMAC_TXD3);
	davinci_cfg_reg(DM365_EMAC_TXD2);
	davinci_cfg_reg(DM365_EMAC_TXD1);
	davinci_cfg_reg(DM365_EMAC_TXD0);
	davinci_cfg_reg(DM365_EMAC_RXD3);
	davinci_cfg_reg(DM365_EMAC_RXD2);
	davinci_cfg_reg(DM365_EMAC_RXD1);
	davinci_cfg_reg(DM365_EMAC_RXD0);
	davinci_cfg_reg(DM365_EMAC_RX_CLK);
	davinci_cfg_reg(DM365_EMAC_RX_DV);
	davinci_cfg_reg(DM365_EMAC_RX_ER);
	davinci_cfg_reg(DM365_EMAC_CRS);
	davinci_cfg_reg(DM365_EMAC_MDIO);
	davinci_cfg_reg(DM365_EMAC_MDCLK);

	/*
	 * EMAC interrupts are multiplexed with GPIO interrupts
	 * Details are available at the DM365 ARM
	 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
	 */
	davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
	davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
	davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
	davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
}

static void dm365evm_mmc_configure(void)
{
	/*
	 * MMC/SD pins are multiplexed with GPIO and EMIF
	 * Further details are available at the DM365 ARM
	 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
	 */
	davinci_cfg_reg(DM365_SD1_CLK);
	davinci_cfg_reg(DM365_SD1_CMD);
	davinci_cfg_reg(DM365_SD1_DATA3);
	davinci_cfg_reg(DM365_SD1_DATA2);
	davinci_cfg_reg(DM365_SD1_DATA1);
	davinci_cfg_reg(DM365_SD1_DATA0);
}

static struct tvp514x_platform_data tvp5146_pdata = {
	.clk_polarity = 0,
	.hs_polarity = 1,
	.vs_polarity = 1
};

#define TVP514X_STD_ALL        (V4L2_STD_NTSC | V4L2_STD_PAL)
/* Inputs available at the TVP5146 */
static struct v4l2_input tvp5146_inputs[] = {
	{
		.index = 0,
		.name = "Composite",
		.type = V4L2_INPUT_TYPE_CAMERA,
		.std = TVP514X_STD_ALL,
	},
	{
		.index = 1,
		.name = "S-Video",
		.type = V4L2_INPUT_TYPE_CAMERA,
		.std = TVP514X_STD_ALL,
	},
};

/*
 * this is the route info for connecting each input to decoder
 * ouput that goes to vpfe. There is a one to one correspondence
 * with tvp5146_inputs
 */
static struct vpfe_route tvp5146_routes[] = {
	{
		.input = INPUT_CVBS_VI2B,
		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
	},
{
		.input = INPUT_SVIDEO_VI2C_VI1C,
		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
	},
};

static struct vpfe_subdev_info vpfe_sub_devs[] = {
	{
		.name = "tvp5146",
		.grp_id = 0,
		.num_inputs = ARRAY_SIZE(tvp5146_inputs),
		.inputs = tvp5146_inputs,
		.routes = tvp5146_routes,
		.can_route = 1,
		.ccdc_if_params = {
			.if_type = VPFE_BT656,
			.hdpol = VPFE_PINPOL_POSITIVE,
			.vdpol = VPFE_PINPOL_POSITIVE,
		},
		.board_info = {
			I2C_BOARD_INFO("tvp5146", 0x5d),
			.platform_data = &tvp5146_pdata,
		},
	},
};

static struct vpfe_config vpfe_cfg = {
	.num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
	.sub_devs = vpfe_sub_devs,
	.i2c_adapter_id = 1,
	.card_name = "DM365 EVM",
	.ccdc = "ISIF",
};

static void __init evm_init_i2c(void)
{
	davinci_init_i2c(&i2c_pdata);
	i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
}

static struct platform_device *dm365_evm_nand_devices[] __initdata = {
	&davinci_nand_device,
};

static inline int have_leds(void)
{
#ifdef CONFIG_LEDS_CLASS
	return 1;
#else
	return 0;
#endif
}

struct cpld_led {
	struct led_classdev	cdev;
	u8			mask;
};

static const struct {
	const char *name;
	const char *trigger;
} cpld_leds[] = {
	{ "dm365evm::ds2", },
	{ "dm365evm::ds3", },
	{ "dm365evm::ds4", },
	{ "dm365evm::ds5", },
	{ "dm365evm::ds6", "nand-disk", },
	{ "dm365evm::ds7", "mmc1", },
	{ "dm365evm::ds8", "mmc0", },
	{ "dm365evm::ds9", "heartbeat", },
};

static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
{
	struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
	u8 reg = __raw_readb(cpld + CPLD_LEDS);

	if (b != LED_OFF)
		reg &= ~led->mask;
	else
		reg |= led->mask;
	__raw_writeb(reg, cpld + CPLD_LEDS);
}

static enum led_brightness cpld_led_get(struct led_classdev *cdev)
{
	struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
	u8 reg = __raw_readb(cpld + CPLD_LEDS);

	return (reg & led->mask) ? LED_OFF : LED_FULL;
}

static int __init cpld_leds_init(void)
{
	int	i;

	if (!have_leds() ||  !cpld)
		return 0;

	/* setup LEDs */
	__raw_writeb(0xff, cpld + CPLD_LEDS);
	for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
		struct cpld_led *led;

		led = kzalloc(sizeof(*led), GFP_KERNEL);
		if (!led)
			break;

		led->cdev.name = cpld_leds[i].name;
		led->cdev.brightness_set = cpld_led_set;
		led->cdev.brightness_get = cpld_led_get;
		led->cdev.default_trigger = cpld_leds[i].trigger;
		led->mask = BIT(i);

		if (led_classdev_register(NULL, &led->cdev) < 0) {
			kfree(led);
			break;
		}
	}

	return 0;
}
/* run after subsys_initcall() for LEDs */
fs_initcall(cpld_leds_init);


static void __init evm_init_cpld(void)
{
	u8 mux, resets;
	const char *label;
	struct clk *aemif_clk;

	/* Make sure we can configure the CPLD through CS1.  Then
	 * leave it on for later access to MMC and LED registers.
	 */
	aemif_clk = clk_get(NULL, "aemif");
	if (IS_ERR(aemif_clk))
		return;
	clk_enable(aemif_clk);

	if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
			"cpld") == NULL)
		goto fail;
	cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
	if (!cpld) {
		release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
				SECTION_SIZE);
fail:
		pr_err("ERROR: can't map CPLD\n");
		clk_disable(aemif_clk);
		return;
	}

	/* External muxing for some signals */
	mux = 0;

	/* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
	 * NOTE:  SW4 bus width setting must match!
	 */
	if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
		/* external keypad mux */
		mux |= BIT(7);

		platform_add_devices(dm365_evm_nand_devices,
				ARRAY_SIZE(dm365_evm_nand_devices));
	} else {
		/* no OneNAND support yet */
	}

	/* Leave external chips in reset when unused. */
	resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);

	/* Static video input config with SN74CBT16214 1-of-3 mux:
	 *  - port b1 == tvp7002 (mux lowbits == 1 or 6)
	 *  - port b2 == imager (mux lowbits == 2 or 7)
	 *  - port b3 == tvp5146 (mux lowbits == 5)
	 *
	 * Runtime switching could work too, with limitations.
	 */
	if (have_imager()) {
		label = "HD imager";
		mux |= 1;

		/* externally mux MMC1/ENET/AIC33 to imager */
		mux |= BIT(6) | BIT(5) | BIT(3);
	} else {
		struct davinci_soc_info *soc_info = &davinci_soc_info;

		/* we can use MMC1 ... */
		dm365evm_mmc_configure();
		davinci_setup_mmc(1, &dm365evm_mmc_config);

		/* ... and ENET ... */
		dm365evm_emac_configure();
		soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
		soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
		resets &= ~BIT(3);

		/* ... and AIC33 */
		resets &= ~BIT(1);

		if (have_tvp7002()) {
			mux |= 2;
			resets &= ~BIT(2);
			label = "tvp7002 HD";
		} else {
			/* default to tvp5146 */
			mux |= 5;
			resets &= ~BIT(0);
			label = "tvp5146 SD";
		}
	}
	__raw_writeb(mux, cpld + CPLD_MUX);
	__raw_writeb(resets, cpld + CPLD_RESETS);
	pr_info("EVM: %s video input\n", label);

	/* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
}

static struct davinci_uart_config uart_config __initdata = {
	.enabled_uarts = (1 << 0),
};

static void __init dm365_evm_map_io(void)
{
	/* setup input configuration for VPFE input devices */
	dm365_set_vpfe_config(&vpfe_cfg);
	dm365_init();
}

static struct spi_eeprom at25640 = {
	.byte_len	= SZ_64K / 8,
	.name		= "at25640",
	.page_size	= 32,
	.flags		= EE_ADDR2,
};

static struct spi_board_info dm365_evm_spi_info[] __initconst = {
	{
		.modalias	= "at25",
		.platform_data	= &at25640,
		.max_speed_hz	= 10 * 1000 * 1000,
		.bus_num	= 0,
		.chip_select	= 0,
		.mode		= SPI_MODE_0,
	},
};

static __init void dm365_evm_init(void)
{
	evm_init_i2c();
	davinci_serial_init(&uart_config);

	dm365evm_emac_configure();
	dm365evm_mmc_configure();

	davinci_setup_mmc(0, &dm365evm_mmc_config);

	/* maybe setup mmc1/etc ... _after_ mmc0 */
	evm_init_cpld();

	dm365_init_asp(&dm365_evm_snd_data);
	dm365_init_rtc();
	dm365_init_ks(&dm365evm_ks_data);

	dm365_init_spi0(BIT(0), dm365_evm_spi_info,
			ARRAY_SIZE(dm365_evm_spi_info));
}

static __init void dm365_evm_irq_init(void)
{
	davinci_irq_init();
}

MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
	.phys_io	= IO_PHYS,
	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
	.boot_params	= (0x80000100),
	.map_io		= dm365_evm_map_io,
	.init_irq	= dm365_evm_irq_init,
	.timer		= &davinci_timer,
	.init_machine	= dm365_evm_init,
MACHINE_END
Commit	Line	Data
37dd0095 SP	1	/*
	2	* TI DaVinci DM365 EVM board support
	3	*
	4	* Copyright (C) 2009 Texas Instruments Incorporated
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation version 2.
	9	*
	10	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	11	* kind, whether express or implied; without even the implied warranty
	12	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15	#include <linux/kernel.h>
37dd0095	16	#include <linux/init.h>
42d399e4	17	#include <linux/err.h>
37dd0095 SP	18	#include <linux/i2c.h>
	19	#include <linux/io.h>
	20	#include <linux/clk.h>
8ed0a9d4	21	#include <linux/i2c/at24.h>
ff255c6c	22	#include <linux/leds.h>
37b798da SP	23	#include <linux/mtd/mtd.h>
	24	#include <linux/mtd/partitions.h>
	25	#include <linux/mtd/nand.h>
990c09d5	26	#include <linux/input.h>
5f19daa1 SP	27	#include <linux/spi/spi.h>
5f19daa1 SP	28	#include <linux/spi/eeprom.h>
42d399e4	29
37dd0095 SP	30	#include <asm/mach-types.h>
37dd0095 SP	31	#include <asm/mach/arch.h>
42d399e4	32
8ed0a9d4	33	#include <mach/mux.h>
37dd0095	34	#include <mach/dm365.h>
37dd0095 SP	35	#include <mach/common.h>
37dd0095 SP	36	#include <mach/i2c.h>
37dd0095	37	#include <mach/serial.h>
a45c8ba3	38	#include <mach/mmc.h>
37b798da	39	#include <mach/nand.h>
990c09d5	40	#include <mach/keyscan.h>
37b798da	41
f2a4c59d MK	42	#include <media/tvp514x.h>
f2a4c59d MK	43
ff255c6c DB	44	static inline int have_imager(void)
	45	{
	46	/* REVISIT when it's supported, trigger via Kconfig */
	47	return 0;
	48	}
	49
	50	static inline int have_tvp7002(void)
	51	{
	52	/* REVISIT when it's supported, trigger via Kconfig */
	53	return 0;
	54	}
	55
	56
37b798da SP	57	#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
37b798da SP	58	#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
ff255c6c	59	#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
37dd0095	60
8ed0a9d4 SP	61	#define DM365_EVM_PHY_MASK (0x2)
	62	#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
	63
ff255c6c DB	64	/*
	65	* A MAX-II CPLD is used for various board control functions.
	66	*/
	67	#define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
	68
	69	#define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
	70	#define CPLD_TEST CPLD_OFFSET(0,1)
	71	#define CPLD_LEDS CPLD_OFFSET(0,2)
	72	#define CPLD_MUX CPLD_OFFSET(0,3)
	73	#define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
	74	#define CPLD_POWER CPLD_OFFSET(1,1)
	75	#define CPLD_VIDEO CPLD_OFFSET(1,2)
	76	#define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
	77
	78	#define CPLD_DILC_OUT CPLD_OFFSET(2,0)
	79	#define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
	80
	81	#define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
	82	#define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
	83	#define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
	84	#define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
	85	#define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
	86	#define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
	87	#define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
	88	#define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
	89	#define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
	90
	91	#define CPLD_RESETS CPLD_OFFSET(4,3)
	92
	93	#define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
	94	#define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
	95	#define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
	96	#define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
	97	#define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
	98	#define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
	99
	100	static void __iomem *cpld;
	101
	102
37b798da SP	103	/* NOTE: this is geared for the standard config, with a socketed
	104	* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
	105	* swap chips with a different block size, partitioning will
	106	* need to be changed. This NAND chip MT29F16G08FAA is the default
	107	* NAND shipped with the Spectrum Digital DM365 EVM
	108	*/
	109	#define NAND_BLOCK_SIZE SZ_128K
	110
	111	static struct mtd_partition davinci_nand_partitions[] = {
	112	{
	113	/* UBL (a few copies) plus U-Boot */
	114	.name = "bootloader",
	115	.offset = 0,
	116	.size = 28 * NAND_BLOCK_SIZE,
	117	.mask_flags = MTD_WRITEABLE, /* force read-only */
	118	}, {
	119	/* U-Boot environment */
	120	.name = "params",
	121	.offset = MTDPART_OFS_APPEND,
	122	.size = 2 * NAND_BLOCK_SIZE,
	123	.mask_flags = 0,
	124	}, {
	125	.name = "kernel",
	126	.offset = MTDPART_OFS_APPEND,
	127	.size = SZ_4M,
	128	.mask_flags = 0,
	129	}, {
	130	.name = "filesystem1",
	131	.offset = MTDPART_OFS_APPEND,
	132	.size = SZ_512M,
	133	.mask_flags = 0,
	134	}, {
	135	.name = "filesystem2",
	136	.offset = MTDPART_OFS_APPEND,
	137	.size = MTDPART_SIZ_FULL,
	138	.mask_flags = 0,
	139	}
	140	/* two blocks with bad block table (and mirror) at the end */
	141	};
	142
	143	static struct davinci_nand_pdata davinci_nand_data = {
	144	.mask_chipsel = BIT(14),
	145	.parts = davinci_nand_partitions,
	146	.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
	147	.ecc_mode = NAND_ECC_HW,
	148	.options = NAND_USE_FLASH_BBT,
dc4c05a5	149	.ecc_bits = 4,
37b798da SP	150	};
	151
	152	static struct resource davinci_nand_resources[] = {
	153	{
	154	.start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
	155	.end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
	156	.flags = IORESOURCE_MEM,
	157	}, {
	158	.start = DM365_ASYNC_EMIF_CONTROL_BASE,
	159	.end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
	160	.flags = IORESOURCE_MEM,
	161	},
	162	};
	163
	164	static struct platform_device davinci_nand_device = {
	165	.name = "davinci_nand",
	166	.id = 0,
	167	.num_resources = ARRAY_SIZE(davinci_nand_resources),
	168	.resource = davinci_nand_resources,
	169	.dev = {
	170	.platform_data = &davinci_nand_data,
	171	},
	172	};
	173
8ed0a9d4 SP	174	static struct at24_platform_data eeprom_info = {
	175	.byte_len = (256*1024) / 8,
	176	.page_size = 64,
	177	.flags = AT24_FLAG_ADDR16,
	178	.setup = davinci_get_mac_addr,
	179	.context = (void *)0x7f00,
	180	};
	181
e9ab3214 MA	182	static struct snd_platform_data dm365_evm_snd_data;
e9ab3214 MA	183
8ed0a9d4 SP	184	static struct i2c_board_info i2c_info[] = {
	185	{
	186	I2C_BOARD_INFO("24c256", 0x50),
	187	.platform_data = &eeprom_info,
	188	},
e9ab3214 MA	189	{
	190	I2C_BOARD_INFO("tlv320aic3x", 0x18),
	191	},
8ed0a9d4 SP	192	};
8ed0a9d4 SP	193
37dd0095 SP	194	static struct davinci_i2c_platform_data i2c_pdata = {
	195	.bus_freq = 400 /* kHz */,
	196	.bus_delay = 0 /* usec */,
	197	};
	198
c92b29ec MA	199	static int dm365evm_keyscan_enable(struct device *dev)
	200	{
	201	return davinci_cfg_reg(DM365_KEYSCAN);
	202	}
	203
990c09d5 MA	204	static unsigned short dm365evm_keymap[] = {
	205	KEY_KP2,
	206	KEY_LEFT,
	207	KEY_EXIT,
	208	KEY_DOWN,
	209	KEY_ENTER,
	210	KEY_UP,
	211	KEY_KP1,
	212	KEY_RIGHT,
	213	KEY_MENU,
	214	KEY_RECORD,
	215	KEY_REWIND,
	216	KEY_KPMINUS,
	217	KEY_STOP,
	218	KEY_FASTFORWARD,
	219	KEY_KPPLUS,
	220	KEY_PLAYPAUSE,
	221	0
	222	};
	223
	224	static struct davinci_ks_platform_data dm365evm_ks_data = {
c92b29ec	225	.device_enable = dm365evm_keyscan_enable,
990c09d5 MA	226	.keymap = dm365evm_keymap,
	227	.keymapsize = ARRAY_SIZE(dm365evm_keymap),
	228	.rep = 1,
	229	/* Scan period = strobe + interval */
	230	.strobe = 0x5,
	231	.interval = 0x2,
	232	.matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
	233	};
990c09d5	234
ff255c6c DB	235	static int cpld_mmc_get_cd(int module)
	236	{
	237	if (!cpld)
	238	return -ENXIO;
	239
	240	/* low == card present */
	241	return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
	242	}
	243
	244	static int cpld_mmc_get_ro(int module)
	245	{
	246	if (!cpld)
	247	return -ENXIO;
	248
	249	/* high == card's write protect switch active */
	250	return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
	251	}
	252
a45c8ba3	253	static struct davinci_mmc_config dm365evm_mmc_config = {
ff255c6c DB	254	.get_cd = cpld_mmc_get_cd,
ff255c6c DB	255	.get_ro = cpld_mmc_get_ro,
a45c8ba3 SP	256	.wires = 4,
	257	.max_freq = 50000000,
	258	.caps = MMC_CAP_MMC_HIGHSPEED \| MMC_CAP_SD_HIGHSPEED,
	259	.version = MMC_CTLR_VERSION_2,
	260	};
	261
8ed0a9d4 SP	262	static void dm365evm_emac_configure(void)
	263	{
	264	/*
	265	* EMAC pins are multiplexed with GPIO and UART
	266	* Further details are available at the DM365 ARM
	267	* Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
	268	*/
	269	davinci_cfg_reg(DM365_EMAC_TX_EN);
	270	davinci_cfg_reg(DM365_EMAC_TX_CLK);
	271	davinci_cfg_reg(DM365_EMAC_COL);
	272	davinci_cfg_reg(DM365_EMAC_TXD3);
	273	davinci_cfg_reg(DM365_EMAC_TXD2);
	274	davinci_cfg_reg(DM365_EMAC_TXD1);
	275	davinci_cfg_reg(DM365_EMAC_TXD0);
	276	davinci_cfg_reg(DM365_EMAC_RXD3);
	277	davinci_cfg_reg(DM365_EMAC_RXD2);
	278	davinci_cfg_reg(DM365_EMAC_RXD1);
	279	davinci_cfg_reg(DM365_EMAC_RXD0);
	280	davinci_cfg_reg(DM365_EMAC_RX_CLK);
	281	davinci_cfg_reg(DM365_EMAC_RX_DV);
	282	davinci_cfg_reg(DM365_EMAC_RX_ER);
	283	davinci_cfg_reg(DM365_EMAC_CRS);
	284	davinci_cfg_reg(DM365_EMAC_MDIO);
	285	davinci_cfg_reg(DM365_EMAC_MDCLK);
	286
	287	/*
	288	* EMAC interrupts are multiplexed with GPIO interrupts
	289	* Details are available at the DM365 ARM
	290	* Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
	291	*/
	292	davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
	293	davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
	294	davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
	295	davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
	296	}
	297
a45c8ba3 SP	298	static void dm365evm_mmc_configure(void)
	299	{
	300	/*
	301	* MMC/SD pins are multiplexed with GPIO and EMIF
	302	* Further details are available at the DM365 ARM
	303	* Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
	304	*/
	305	davinci_cfg_reg(DM365_SD1_CLK);
	306	davinci_cfg_reg(DM365_SD1_CMD);
	307	davinci_cfg_reg(DM365_SD1_DATA3);
	308	davinci_cfg_reg(DM365_SD1_DATA2);
	309	davinci_cfg_reg(DM365_SD1_DATA1);
	310	davinci_cfg_reg(DM365_SD1_DATA0);
	311	}
	312
f2a4c59d MK	313	static struct tvp514x_platform_data tvp5146_pdata = {
	314	.clk_polarity = 0,
	315	.hs_polarity = 1,
	316	.vs_polarity = 1
	317	};
	318
	319	#define TVP514X_STD_ALL (V4L2_STD_NTSC \| V4L2_STD_PAL)
	320	/* Inputs available at the TVP5146 */
	321	static struct v4l2_input tvp5146_inputs[] = {
	322	{
	323	.index = 0,
	324	.name = "Composite",
	325	.type = V4L2_INPUT_TYPE_CAMERA,
	326	.std = TVP514X_STD_ALL,
	327	},
	328	{
	329	.index = 1,
	330	.name = "S-Video",
	331	.type = V4L2_INPUT_TYPE_CAMERA,
	332	.std = TVP514X_STD_ALL,
	333	},
	334	};
	335
	336	/*
	337	* this is the route info for connecting each input to decoder
	338	* ouput that goes to vpfe. There is a one to one correspondence
	339	* with tvp5146_inputs
	340	*/
	341	static struct vpfe_route tvp5146_routes[] = {
	342	{
	343	.input = INPUT_CVBS_VI2B,
	344	.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
	345	},
	346	{
	347	.input = INPUT_SVIDEO_VI2C_VI1C,
	348	.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
	349	},
	350	};
	351
	352	static struct vpfe_subdev_info vpfe_sub_devs[] = {
	353	{
	354	.name = "tvp5146",
	355	.grp_id = 0,
	356	.num_inputs = ARRAY_SIZE(tvp5146_inputs),
	357	.inputs = tvp5146_inputs,
	358	.routes = tvp5146_routes,
	359	.can_route = 1,
	360	.ccdc_if_params = {
	361	.if_type = VPFE_BT656,
	362	.hdpol = VPFE_PINPOL_POSITIVE,
	363	.vdpol = VPFE_PINPOL_POSITIVE,
	364	},
	365	.board_info = {
	366	I2C_BOARD_INFO("tvp5146", 0x5d),
	367	.platform_data = &tvp5146_pdata,
	368	},
	369	},
	370	};
	371
	372	static struct vpfe_config vpfe_cfg = {
	373	.num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
	374	.sub_devs = vpfe_sub_devs,
	375	.i2c_adapter_id = 1,
	376	.card_name = "DM365 EVM",
377	.ccdc = "ISIF",
378	};
379
37dd0095 SP	380	static void __init evm_init_i2c(void)
	381	{
	382	davinci_init_i2c(&i2c_pdata);
8ed0a9d4	383	i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
37dd0095 SP	384	}
37dd0095 SP	385
ff255c6c	386	static struct platform_device *dm365_evm_nand_devices[] __initdata = {
37b798da SP	387	&davinci_nand_device,
	388	};
	389
ff255c6c DB	390	static inline int have_leds(void)
	391	{
	392	#ifdef CONFIG_LEDS_CLASS
	393	return 1;
	394	#else
	395	return 0;
	396	#endif
	397	}
	398
	399	struct cpld_led {
	400	struct led_classdev cdev;
	401	u8 mask;
	402	};
	403
	404	static const struct {
	405	const char *name;
	406	const char *trigger;
	407	} cpld_leds[] = {
	408	{ "dm365evm::ds2", },
	409	{ "dm365evm::ds3", },
	410	{ "dm365evm::ds4", },
	411	{ "dm365evm::ds5", },
	412	{ "dm365evm::ds6", "nand-disk", },
	413	{ "dm365evm::ds7", "mmc1", },
	414	{ "dm365evm::ds8", "mmc0", },
	415	{ "dm365evm::ds9", "heartbeat", },
	416	};
	417
	418	static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
	419	{
	420	struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
	421	u8 reg = __raw_readb(cpld + CPLD_LEDS);
	422
	423	if (b != LED_OFF)
	424	reg &= ~led->mask;
	425	else
	426	reg \|= led->mask;
	427	__raw_writeb(reg, cpld + CPLD_LEDS);
	428	}
	429
	430	static enum led_brightness cpld_led_get(struct led_classdev *cdev)
	431	{
	432	struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
	433	u8 reg = __raw_readb(cpld + CPLD_LEDS);
	434
	435	return (reg & led->mask) ? LED_OFF : LED_FULL;
	436	}
	437
	438	static int __init cpld_leds_init(void)
	439	{
	440	int i;
	441
	442	if (!have_leds() \|\| !cpld)
	443	return 0;
	444
	445	/* setup LEDs */
	446	__raw_writeb(0xff, cpld + CPLD_LEDS);
	447	for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
	448	struct cpld_led *led;
	449
	450	led = kzalloc(sizeof(*led), GFP_KERNEL);
	451	if (!led)
	452	break;
	453
454	led->cdev.name = cpld_leds[i].name;
455	led->cdev.brightness_set = cpld_led_set;
456	led->cdev.brightness_get = cpld_led_get;
457	led->cdev.default_trigger = cpld_leds[i].trigger;
458	led->mask = BIT(i);
459
460	if (led_classdev_register(NULL, &led->cdev) < 0) {
461	kfree(led);
462	break;
463	}
464	}
465
466	return 0;
467	}
468	/* run after subsys_initcall() for LEDs */
469	fs_initcall(cpld_leds_init);
470
471
472	static void __init evm_init_cpld(void)
473	{
474	u8 mux, resets;
475	const char *label;
476	struct clk *aemif_clk;
477
478	/* Make sure we can configure the CPLD through CS1. Then
479	* leave it on for later access to MMC and LED registers.
480	*/
481	aemif_clk = clk_get(NULL, "aemif");
482	if (IS_ERR(aemif_clk))
483	return;
484	clk_enable(aemif_clk);
485
486	if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
487	"cpld") == NULL)
488	goto fail;
489	cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
490	if (!cpld) {
491	release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
492	SECTION_SIZE);
493	fail:
494	pr_err("ERROR: can't map CPLD\n");
495	clk_disable(aemif_clk);
496	return;
497	}
498
499	/* External muxing for some signals */
500	mux = 0;
501
502	/* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
503	* NOTE: SW4 bus width setting must match!
504	*/
505	if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
506	/* external keypad mux */
507	mux \|= BIT(7);
508
509	platform_add_devices(dm365_evm_nand_devices,
510	ARRAY_SIZE(dm365_evm_nand_devices));
511	} else {
512	/* no OneNAND support yet */
513	}
514
515	/* Leave external chips in reset when unused. */
516	resets = BIT(3) \| BIT(2) \| BIT(1) \| BIT(0);
517
518	/* Static video input config with SN74CBT16214 1-of-3 mux:
519	* - port b1 == tvp7002 (mux lowbits == 1 or 6)
520	* - port b2 == imager (mux lowbits == 2 or 7)
521	* - port b3 == tvp5146 (mux lowbits == 5)
522	*
523	* Runtime switching could work too, with limitations.
524	*/
525	if (have_imager()) {
526	label = "HD imager";
527	mux \|= 1;
528
529	/* externally mux MMC1/ENET/AIC33 to imager */
530	mux \|= BIT(6) \| BIT(5) \| BIT(3);
531	} else {
532	struct davinci_soc_info *soc_info = &davinci_soc_info;
533
534	/* we can use MMC1 ... */
535	dm365evm_mmc_configure();
536	davinci_setup_mmc(1, &dm365evm_mmc_config);
537
538	/* ... and ENET ... */
539	dm365evm_emac_configure();
540	soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
541	soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
542	resets &= ~BIT(3);
543
544	/* ... and AIC33 */
545	resets &= ~BIT(1);
546
547	if (have_tvp7002()) {
548	mux \|= 2;
549	resets &= ~BIT(2);
550	label = "tvp7002 HD";
551	} else {
552	/* default to tvp5146 */
553	mux \|= 5;
554	resets &= ~BIT(0);
555	label = "tvp5146 SD";
556	}
557	}
558	__raw_writeb(mux, cpld + CPLD_MUX);
559	__raw_writeb(resets, cpld + CPLD_RESETS);
560	pr_info("EVM: %s video input\n", label);
561
562	/* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
563	}
564
37dd0095 SP	565	static struct davinci_uart_config uart_config __initdata = {
	566	.enabled_uarts = (1 << 0),
	567	};
	568
	569	static void __init dm365_evm_map_io(void)
	570	{
f2a4c59d MK	571	/* setup input configuration for VPFE input devices */
f2a4c59d MK	572	dm365_set_vpfe_config(&vpfe_cfg);
37dd0095 SP	573	dm365_init();
	574	}
	575
5f19daa1 SP	576	static struct spi_eeprom at25640 = {
	577	.byte_len = SZ_64K / 8,
	578	.name = "at25640",
	579	.page_size = 32,
	580	.flags = EE_ADDR2,
	581	};
	582
	583	static struct spi_board_info dm365_evm_spi_info[] __initconst = {
	584	{
	585	.modalias = "at25",
	586	.platform_data = &at25640,
	587	.max_speed_hz = 10 * 1000 * 1000,
	588	.bus_num = 0,
	589	.chip_select = 0,
	590	.mode = SPI_MODE_0,
	591	},
	592	};
	593
37dd0095 SP	594	static __init void dm365_evm_init(void)
	595	{
	596	evm_init_i2c();
	597	davinci_serial_init(&uart_config);
8ed0a9d4 SP	598
8ed0a9d4 SP	599	dm365evm_emac_configure();
a45c8ba3 SP	600	dm365evm_mmc_configure();
	601
	602	davinci_setup_mmc(0, &dm365evm_mmc_config);
8ed0a9d4	603
ff255c6c DB	604	/* maybe setup mmc1/etc ... _after_ mmc0 */
ff255c6c DB	605	evm_init_cpld();
e9ab3214 MA	606
e9ab3214 MA	607	dm365_init_asp(&dm365_evm_snd_data);
99381b4f	608	dm365_init_rtc();
990c09d5	609	dm365_init_ks(&dm365evm_ks_data);
5f19daa1 SP	610
	611	dm365_init_spi0(BIT(0), dm365_evm_spi_info,
	612	ARRAY_SIZE(dm365_evm_spi_info));
37dd0095 SP	613	}
	614
	615	static __init void dm365_evm_irq_init(void)
	616	{
	617	davinci_irq_init();
	618	}
	619
	620	MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
	621	.phys_io = IO_PHYS,
	622	.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
	623	.boot_params = (0x80000100),
	624	.map_io = dm365_evm_map_io,
	625	.init_irq = dm365_evm_irq_init,
	626	.timer = &davinci_timer,
	627	.init_machine = dm365_evm_init,
	628	MACHINE_END
	629