Commit | Line | Data |
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55c79a40 MG |
1 | /* |
2 | * DA8XX/OMAP L1XX platform device data | |
3 | * | |
4 | * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> | |
5 | * Derived from code that was: | |
6 | * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
55c79a40 MG |
13 | #include <linux/init.h> |
14 | #include <linux/platform_device.h> | |
5c71d618 | 15 | #include <linux/dma-contiguous.h> |
55c79a40 | 16 | #include <linux/serial_8250.h> |
cbb2c961 SN |
17 | #include <linux/ahci_platform.h> |
18 | #include <linux/clk.h> | |
7b6d864b | 19 | #include <linux/reboot.h> |
55c79a40 MG |
20 | |
21 | #include <mach/cputype.h> | |
22 | #include <mach/common.h> | |
23 | #include <mach/time.h> | |
24 | #include <mach/da8xx.h> | |
1960e693 | 25 | #include <mach/cpuidle.h> |
8e0d72d2 | 26 | #include <mach/sram.h> |
55c79a40 MG |
27 | |
28 | #include "clock.h" | |
896f66b7 | 29 | #include "asp.h" |
55c79a40 MG |
30 | |
31 | #define DA8XX_TPCC_BASE 0x01c00000 | |
32 | #define DA8XX_TPTC0_BASE 0x01c08000 | |
33 | #define DA8XX_TPTC1_BASE 0x01c08400 | |
34 | #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ | |
35 | #define DA8XX_I2C0_BASE 0x01c22000 | |
8ac764e3 | 36 | #define DA8XX_RTC_BASE 0x01c23000 |
8e0d72d2 | 37 | #define DA8XX_PRUSS_MEM_BASE 0x01c30000 |
8ac764e3 SS |
38 | #define DA8XX_MMCSD0_BASE 0x01c40000 |
39 | #define DA8XX_SPI0_BASE 0x01c41000 | |
40 | #define DA830_SPI1_BASE 0x01e12000 | |
41 | #define DA8XX_LCD_CNTRL_BASE 0x01e13000 | |
cbb2c961 | 42 | #define DA850_SATA_BASE 0x01e18000 |
8ac764e3 | 43 | #define DA850_MMCSD1_BASE 0x01e1b000 |
55c79a40 MG |
44 | #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 |
45 | #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 | |
46 | #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 | |
47 | #define DA8XX_EMAC_MDIO_BASE 0x01e24000 | |
55c79a40 | 48 | #define DA8XX_I2C1_BASE 0x01e28000 |
8ac764e3 SS |
49 | #define DA850_TPCC1_BASE 0x01e30000 |
50 | #define DA850_TPTC2_BASE 0x01e38000 | |
9e7d24f6 | 51 | #define DA850_SPI1_BASE 0x01f0e000 |
8ac764e3 | 52 | #define DA8XX_DDR2_CTL_BASE 0xb0000000 |
55c79a40 MG |
53 | |
54 | #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 | |
55 | #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 | |
56 | #define DA8XX_EMAC_RAM_OFFSET 0x0000 | |
55c79a40 MG |
57 | #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K |
58 | ||
54ce6883 MW |
59 | #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14) |
60 | #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15) | |
e38c2b22 MW |
61 | #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16) |
62 | #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17) | |
54ce6883 MW |
63 | #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18) |
64 | #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19) | |
e38c2b22 MW |
65 | #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28) |
66 | #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29) | |
67 | ||
d2de0582 SN |
68 | void __iomem *da8xx_syscfg0_base; |
69 | void __iomem *da8xx_syscfg1_base; | |
6a28adef | 70 | |
19955c3d | 71 | static struct plat_serial8250_port da8xx_serial0_pdata[] = { |
55c79a40 MG |
72 | { |
73 | .mapbase = DA8XX_UART0_BASE, | |
74 | .irq = IRQ_DA8XX_UARTINT0, | |
75 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
76 | UPF_IOREMAP, | |
77 | .iotype = UPIO_MEM, | |
78 | .regshift = 2, | |
79 | }, | |
19955c3d MP |
80 | { |
81 | .flags = 0, | |
82 | } | |
83 | }; | |
84 | static struct plat_serial8250_port da8xx_serial1_pdata[] = { | |
55c79a40 MG |
85 | { |
86 | .mapbase = DA8XX_UART1_BASE, | |
87 | .irq = IRQ_DA8XX_UARTINT1, | |
88 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
89 | UPF_IOREMAP, | |
90 | .iotype = UPIO_MEM, | |
91 | .regshift = 2, | |
92 | }, | |
19955c3d MP |
93 | { |
94 | .flags = 0, | |
95 | } | |
96 | }; | |
97 | static struct plat_serial8250_port da8xx_serial2_pdata[] = { | |
55c79a40 MG |
98 | { |
99 | .mapbase = DA8XX_UART2_BASE, | |
100 | .irq = IRQ_DA8XX_UARTINT2, | |
101 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
102 | UPF_IOREMAP, | |
103 | .iotype = UPIO_MEM, | |
104 | .regshift = 2, | |
105 | }, | |
106 | { | |
107 | .flags = 0, | |
19955c3d | 108 | } |
55c79a40 MG |
109 | }; |
110 | ||
19955c3d MP |
111 | struct platform_device da8xx_serial_device[] = { |
112 | { | |
113 | .name = "serial8250", | |
114 | .id = PLAT8250_DEV_PLATFORM, | |
115 | .dev = { | |
116 | .platform_data = da8xx_serial0_pdata, | |
117 | } | |
118 | }, | |
119 | { | |
120 | .name = "serial8250", | |
121 | .id = PLAT8250_DEV_PLATFORM1, | |
122 | .dev = { | |
123 | .platform_data = da8xx_serial1_pdata, | |
124 | } | |
55c79a40 | 125 | }, |
19955c3d MP |
126 | { |
127 | .name = "serial8250", | |
128 | .id = PLAT8250_DEV_PLATFORM2, | |
129 | .dev = { | |
130 | .platform_data = da8xx_serial2_pdata, | |
131 | } | |
132 | }, | |
133 | { | |
134 | } | |
55c79a40 MG |
135 | }; |
136 | ||
6cba4355 | 137 | static s8 da8xx_queue_priority_mapping[][2] = { |
55c79a40 MG |
138 | /* {event queue no, Priority} */ |
139 | {0, 3}, | |
140 | {1, 7}, | |
141 | {-1, -1} | |
142 | }; | |
143 | ||
6cba4355 | 144 | static s8 da850_queue_priority_mapping[][2] = { |
3f995f2f SR |
145 | /* {event queue no, Priority} */ |
146 | {0, 3}, | |
147 | {-1, -1} | |
148 | }; | |
149 | ||
bc3ac9f3 | 150 | static struct edma_soc_info da830_edma_cc0_info = { |
bc3ac9f3 | 151 | .queue_priority_mapping = da8xx_queue_priority_mapping, |
f23fe857 | 152 | .default_queue = EVENTQ_1, |
bc3ac9f3 SN |
153 | }; |
154 | ||
155 | static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = { | |
156 | &da830_edma_cc0_info, | |
55c79a40 MG |
157 | }; |
158 | ||
bc3ac9f3 | 159 | static struct edma_soc_info da850_edma_cc_info[] = { |
3f995f2f | 160 | { |
3f995f2f | 161 | .queue_priority_mapping = da8xx_queue_priority_mapping, |
f23fe857 | 162 | .default_queue = EVENTQ_1, |
3f995f2f SR |
163 | }, |
164 | { | |
3f995f2f | 165 | .queue_priority_mapping = da850_queue_priority_mapping, |
f23fe857 | 166 | .default_queue = EVENTQ_0, |
3f995f2f SR |
167 | }, |
168 | }; | |
169 | ||
bc3ac9f3 SN |
170 | static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = { |
171 | &da850_edma_cc_info[0], | |
172 | &da850_edma_cc_info[1], | |
173 | }; | |
174 | ||
3f995f2f | 175 | static struct resource da830_edma_resources[] = { |
55c79a40 MG |
176 | { |
177 | .name = "edma_cc0", | |
178 | .start = DA8XX_TPCC_BASE, | |
179 | .end = DA8XX_TPCC_BASE + SZ_32K - 1, | |
180 | .flags = IORESOURCE_MEM, | |
181 | }, | |
182 | { | |
183 | .name = "edma_tc0", | |
184 | .start = DA8XX_TPTC0_BASE, | |
185 | .end = DA8XX_TPTC0_BASE + SZ_1K - 1, | |
186 | .flags = IORESOURCE_MEM, | |
187 | }, | |
188 | { | |
189 | .name = "edma_tc1", | |
190 | .start = DA8XX_TPTC1_BASE, | |
191 | .end = DA8XX_TPTC1_BASE + SZ_1K - 1, | |
192 | .flags = IORESOURCE_MEM, | |
193 | }, | |
194 | { | |
195 | .name = "edma0", | |
2259bbd4 | 196 | .start = IRQ_DA8XX_CCINT0, |
55c79a40 MG |
197 | .flags = IORESOURCE_IRQ, |
198 | }, | |
199 | { | |
200 | .name = "edma0_err", | |
201 | .start = IRQ_DA8XX_CCERRINT, | |
202 | .flags = IORESOURCE_IRQ, | |
203 | }, | |
204 | }; | |
205 | ||
3f995f2f SR |
206 | static struct resource da850_edma_resources[] = { |
207 | { | |
208 | .name = "edma_cc0", | |
209 | .start = DA8XX_TPCC_BASE, | |
210 | .end = DA8XX_TPCC_BASE + SZ_32K - 1, | |
211 | .flags = IORESOURCE_MEM, | |
212 | }, | |
213 | { | |
214 | .name = "edma_tc0", | |
215 | .start = DA8XX_TPTC0_BASE, | |
216 | .end = DA8XX_TPTC0_BASE + SZ_1K - 1, | |
217 | .flags = IORESOURCE_MEM, | |
218 | }, | |
219 | { | |
220 | .name = "edma_tc1", | |
221 | .start = DA8XX_TPTC1_BASE, | |
222 | .end = DA8XX_TPTC1_BASE + SZ_1K - 1, | |
223 | .flags = IORESOURCE_MEM, | |
224 | }, | |
225 | { | |
226 | .name = "edma_cc1", | |
227 | .start = DA850_TPCC1_BASE, | |
228 | .end = DA850_TPCC1_BASE + SZ_32K - 1, | |
229 | .flags = IORESOURCE_MEM, | |
230 | }, | |
231 | { | |
232 | .name = "edma_tc2", | |
233 | .start = DA850_TPTC2_BASE, | |
234 | .end = DA850_TPTC2_BASE + SZ_1K - 1, | |
235 | .flags = IORESOURCE_MEM, | |
236 | }, | |
237 | { | |
238 | .name = "edma0", | |
239 | .start = IRQ_DA8XX_CCINT0, | |
240 | .flags = IORESOURCE_IRQ, | |
241 | }, | |
242 | { | |
243 | .name = "edma0_err", | |
244 | .start = IRQ_DA8XX_CCERRINT, | |
245 | .flags = IORESOURCE_IRQ, | |
246 | }, | |
247 | { | |
248 | .name = "edma1", | |
249 | .start = IRQ_DA850_CCINT1, | |
250 | .flags = IORESOURCE_IRQ, | |
251 | }, | |
252 | { | |
253 | .name = "edma1_err", | |
254 | .start = IRQ_DA850_CCERRINT1, | |
255 | .flags = IORESOURCE_IRQ, | |
256 | }, | |
257 | }; | |
258 | ||
259 | static struct platform_device da830_edma_device = { | |
55c79a40 MG |
260 | .name = "edma", |
261 | .id = -1, | |
262 | .dev = { | |
3f995f2f | 263 | .platform_data = da830_edma_info, |
55c79a40 | 264 | }, |
3f995f2f SR |
265 | .num_resources = ARRAY_SIZE(da830_edma_resources), |
266 | .resource = da830_edma_resources, | |
267 | }; | |
268 | ||
269 | static struct platform_device da850_edma_device = { | |
270 | .name = "edma", | |
271 | .id = -1, | |
272 | .dev = { | |
273 | .platform_data = da850_edma_info, | |
274 | }, | |
275 | .num_resources = ARRAY_SIZE(da850_edma_resources), | |
276 | .resource = da850_edma_resources, | |
55c79a40 MG |
277 | }; |
278 | ||
a941c503 | 279 | int __init da830_register_edma(struct edma_rsv_info *rsv) |
55c79a40 | 280 | { |
a941c503 | 281 | da830_edma_cc0_info.rsv = rsv; |
3f995f2f | 282 | |
a941c503 RS |
283 | return platform_device_register(&da830_edma_device); |
284 | } | |
285 | ||
286 | int __init da850_register_edma(struct edma_rsv_info *rsv[2]) | |
287 | { | |
288 | if (rsv) { | |
289 | da850_edma_cc_info[0].rsv = rsv[0]; | |
290 | da850_edma_cc_info[1].rsv = rsv[1]; | |
291 | } | |
3f995f2f | 292 | |
a941c503 | 293 | return platform_device_register(&da850_edma_device); |
55c79a40 MG |
294 | } |
295 | ||
296 | static struct resource da8xx_i2c_resources0[] = { | |
297 | { | |
298 | .start = DA8XX_I2C0_BASE, | |
299 | .end = DA8XX_I2C0_BASE + SZ_4K - 1, | |
300 | .flags = IORESOURCE_MEM, | |
301 | }, | |
302 | { | |
303 | .start = IRQ_DA8XX_I2CINT0, | |
304 | .end = IRQ_DA8XX_I2CINT0, | |
305 | .flags = IORESOURCE_IRQ, | |
306 | }, | |
307 | }; | |
308 | ||
309 | static struct platform_device da8xx_i2c_device0 = { | |
310 | .name = "i2c_davinci", | |
311 | .id = 1, | |
312 | .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), | |
313 | .resource = da8xx_i2c_resources0, | |
314 | }; | |
315 | ||
316 | static struct resource da8xx_i2c_resources1[] = { | |
317 | { | |
318 | .start = DA8XX_I2C1_BASE, | |
319 | .end = DA8XX_I2C1_BASE + SZ_4K - 1, | |
320 | .flags = IORESOURCE_MEM, | |
321 | }, | |
322 | { | |
323 | .start = IRQ_DA8XX_I2CINT1, | |
324 | .end = IRQ_DA8XX_I2CINT1, | |
325 | .flags = IORESOURCE_IRQ, | |
326 | }, | |
327 | }; | |
328 | ||
329 | static struct platform_device da8xx_i2c_device1 = { | |
330 | .name = "i2c_davinci", | |
331 | .id = 2, | |
332 | .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), | |
333 | .resource = da8xx_i2c_resources1, | |
334 | }; | |
335 | ||
336 | int __init da8xx_register_i2c(int instance, | |
337 | struct davinci_i2c_platform_data *pdata) | |
338 | { | |
339 | struct platform_device *pdev; | |
340 | ||
341 | if (instance == 0) | |
342 | pdev = &da8xx_i2c_device0; | |
343 | else if (instance == 1) | |
344 | pdev = &da8xx_i2c_device1; | |
345 | else | |
346 | return -EINVAL; | |
347 | ||
348 | pdev->dev.platform_data = pdata; | |
349 | return platform_device_register(pdev); | |
350 | } | |
351 | ||
352 | static struct resource da8xx_watchdog_resources[] = { | |
353 | { | |
354 | .start = DA8XX_WDOG_BASE, | |
355 | .end = DA8XX_WDOG_BASE + SZ_4K - 1, | |
356 | .flags = IORESOURCE_MEM, | |
357 | }, | |
358 | }; | |
359 | ||
19c7c0d8 | 360 | static struct platform_device da8xx_wdt_device = { |
84374812 | 361 | .name = "davinci-wdt", |
55c79a40 MG |
362 | .id = -1, |
363 | .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), | |
364 | .resource = da8xx_watchdog_resources, | |
365 | }; | |
366 | ||
7b6d864b | 367 | void da8xx_restart(enum reboot_mode mode, const char *cmd) |
c6121ddd | 368 | { |
19c7c0d8 KA |
369 | struct device *dev; |
370 | ||
84374812 | 371 | dev = bus_find_device_by_name(&platform_bus_type, NULL, "davinci-wdt"); |
19c7c0d8 KA |
372 | if (!dev) { |
373 | pr_err("%s: failed to find watchdog device\n", __func__); | |
374 | return; | |
375 | } | |
376 | ||
377 | davinci_watchdog_reset(to_platform_device(dev)); | |
c6121ddd SN |
378 | } |
379 | ||
55c79a40 MG |
380 | int __init da8xx_register_watchdog(void) |
381 | { | |
c78a5bc2 | 382 | return platform_device_register(&da8xx_wdt_device); |
55c79a40 MG |
383 | } |
384 | ||
385 | static struct resource da8xx_emac_resources[] = { | |
386 | { | |
387 | .start = DA8XX_EMAC_CPPI_PORT_BASE, | |
d22960c8 | 388 | .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1, |
55c79a40 MG |
389 | .flags = IORESOURCE_MEM, |
390 | }, | |
391 | { | |
392 | .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, | |
393 | .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, | |
394 | .flags = IORESOURCE_IRQ, | |
395 | }, | |
396 | { | |
397 | .start = IRQ_DA8XX_C0_RX_PULSE, | |
398 | .end = IRQ_DA8XX_C0_RX_PULSE, | |
399 | .flags = IORESOURCE_IRQ, | |
400 | }, | |
401 | { | |
402 | .start = IRQ_DA8XX_C0_TX_PULSE, | |
403 | .end = IRQ_DA8XX_C0_TX_PULSE, | |
404 | .flags = IORESOURCE_IRQ, | |
405 | }, | |
406 | { | |
407 | .start = IRQ_DA8XX_C0_MISC_PULSE, | |
408 | .end = IRQ_DA8XX_C0_MISC_PULSE, | |
409 | .flags = IORESOURCE_IRQ, | |
410 | }, | |
411 | }; | |
412 | ||
413 | struct emac_platform_data da8xx_emac_pdata = { | |
414 | .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, | |
415 | .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, | |
416 | .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, | |
55c79a40 MG |
417 | .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, |
418 | .version = EMAC_VERSION_2, | |
419 | }; | |
420 | ||
421 | static struct platform_device da8xx_emac_device = { | |
422 | .name = "davinci_emac", | |
423 | .id = 1, | |
424 | .dev = { | |
425 | .platform_data = &da8xx_emac_pdata, | |
426 | }, | |
427 | .num_resources = ARRAY_SIZE(da8xx_emac_resources), | |
428 | .resource = da8xx_emac_resources, | |
429 | }; | |
430 | ||
d22960c8 CC |
431 | static struct resource da8xx_mdio_resources[] = { |
432 | { | |
433 | .start = DA8XX_EMAC_MDIO_BASE, | |
434 | .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, | |
435 | .flags = IORESOURCE_MEM, | |
436 | }, | |
437 | }; | |
438 | ||
439 | static struct platform_device da8xx_mdio_device = { | |
440 | .name = "davinci_mdio", | |
441 | .id = 0, | |
442 | .num_resources = ARRAY_SIZE(da8xx_mdio_resources), | |
443 | .resource = da8xx_mdio_resources, | |
444 | }; | |
445 | ||
31f53cf3 MG |
446 | int __init da8xx_register_emac(void) |
447 | { | |
d22960c8 CC |
448 | int ret; |
449 | ||
450 | ret = platform_device_register(&da8xx_mdio_device); | |
451 | if (ret < 0) | |
452 | return ret; | |
46c18334 LP |
453 | |
454 | return platform_device_register(&da8xx_emac_device); | |
31f53cf3 MG |
455 | } |
456 | ||
e33ef5e3 C |
457 | static struct resource da830_mcasp1_resources[] = { |
458 | { | |
ee880dbd | 459 | .name = "mpu", |
e33ef5e3 C |
460 | .start = DAVINCI_DA830_MCASP1_REG_BASE, |
461 | .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, | |
462 | .flags = IORESOURCE_MEM, | |
463 | }, | |
464 | /* TX event */ | |
465 | { | |
184981d2 | 466 | .name = "tx", |
e33ef5e3 C |
467 | .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, |
468 | .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, | |
469 | .flags = IORESOURCE_DMA, | |
470 | }, | |
471 | /* RX event */ | |
472 | { | |
184981d2 | 473 | .name = "rx", |
e33ef5e3 C |
474 | .start = DAVINCI_DA830_DMA_MCASP1_AREVT, |
475 | .end = DAVINCI_DA830_DMA_MCASP1_AREVT, | |
476 | .flags = IORESOURCE_DMA, | |
477 | }, | |
80f7d0e0 PU |
478 | { |
479 | .name = "common", | |
480 | .start = IRQ_DA8XX_MCASPINT, | |
481 | .flags = IORESOURCE_IRQ, | |
482 | }, | |
e33ef5e3 C |
483 | }; |
484 | ||
485 | static struct platform_device da830_mcasp1_device = { | |
486 | .name = "davinci-mcasp", | |
487 | .id = 1, | |
488 | .num_resources = ARRAY_SIZE(da830_mcasp1_resources), | |
489 | .resource = da830_mcasp1_resources, | |
490 | }; | |
491 | ||
491214e1 C |
492 | static struct resource da850_mcasp_resources[] = { |
493 | { | |
ee880dbd | 494 | .name = "mpu", |
491214e1 C |
495 | .start = DAVINCI_DA8XX_MCASP0_REG_BASE, |
496 | .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, | |
497 | .flags = IORESOURCE_MEM, | |
498 | }, | |
499 | /* TX event */ | |
500 | { | |
184981d2 | 501 | .name = "tx", |
491214e1 C |
502 | .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, |
503 | .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, | |
504 | .flags = IORESOURCE_DMA, | |
505 | }, | |
506 | /* RX event */ | |
507 | { | |
184981d2 | 508 | .name = "rx", |
491214e1 C |
509 | .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, |
510 | .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, | |
511 | .flags = IORESOURCE_DMA, | |
512 | }, | |
80f7d0e0 PU |
513 | { |
514 | .name = "common", | |
515 | .start = IRQ_DA8XX_MCASPINT, | |
516 | .flags = IORESOURCE_IRQ, | |
517 | }, | |
491214e1 C |
518 | }; |
519 | ||
520 | static struct platform_device da850_mcasp_device = { | |
521 | .name = "davinci-mcasp", | |
522 | .id = 0, | |
523 | .num_resources = ARRAY_SIZE(da850_mcasp_resources), | |
524 | .resource = da850_mcasp_resources, | |
525 | }; | |
526 | ||
b8864aa4 | 527 | void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) |
e33ef5e3 | 528 | { |
c96aacb1 PU |
529 | struct platform_device *pdev; |
530 | ||
531 | switch (id) { | |
532 | case 0: | |
533 | /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */ | |
534 | pdev = &da850_mcasp_device; | |
535 | break; | |
536 | case 1: | |
537 | /* Valid for DA830/OMAP-L137 only */ | |
538 | if (!cpu_is_davinci_da830()) | |
539 | return; | |
540 | pdev = &da830_mcasp1_device; | |
541 | break; | |
542 | default: | |
543 | return; | |
e33ef5e3 | 544 | } |
c96aacb1 PU |
545 | |
546 | pdev->dev.platform_data = pdata; | |
547 | platform_device_register(pdev); | |
e33ef5e3 | 548 | } |
5cbdf276 | 549 | |
8e0d72d2 MP |
550 | static struct resource da8xx_pruss_resources[] = { |
551 | { | |
552 | .start = DA8XX_PRUSS_MEM_BASE, | |
553 | .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF, | |
554 | .flags = IORESOURCE_MEM, | |
555 | }, | |
556 | { | |
557 | .start = IRQ_DA8XX_EVTOUT0, | |
558 | .end = IRQ_DA8XX_EVTOUT0, | |
559 | .flags = IORESOURCE_IRQ, | |
560 | }, | |
561 | { | |
562 | .start = IRQ_DA8XX_EVTOUT1, | |
563 | .end = IRQ_DA8XX_EVTOUT1, | |
564 | .flags = IORESOURCE_IRQ, | |
565 | }, | |
566 | { | |
567 | .start = IRQ_DA8XX_EVTOUT2, | |
568 | .end = IRQ_DA8XX_EVTOUT2, | |
569 | .flags = IORESOURCE_IRQ, | |
570 | }, | |
571 | { | |
572 | .start = IRQ_DA8XX_EVTOUT3, | |
573 | .end = IRQ_DA8XX_EVTOUT3, | |
574 | .flags = IORESOURCE_IRQ, | |
575 | }, | |
576 | { | |
577 | .start = IRQ_DA8XX_EVTOUT4, | |
578 | .end = IRQ_DA8XX_EVTOUT4, | |
579 | .flags = IORESOURCE_IRQ, | |
580 | }, | |
581 | { | |
582 | .start = IRQ_DA8XX_EVTOUT5, | |
583 | .end = IRQ_DA8XX_EVTOUT5, | |
584 | .flags = IORESOURCE_IRQ, | |
585 | }, | |
586 | { | |
587 | .start = IRQ_DA8XX_EVTOUT6, | |
588 | .end = IRQ_DA8XX_EVTOUT6, | |
589 | .flags = IORESOURCE_IRQ, | |
590 | }, | |
591 | { | |
592 | .start = IRQ_DA8XX_EVTOUT7, | |
593 | .end = IRQ_DA8XX_EVTOUT7, | |
594 | .flags = IORESOURCE_IRQ, | |
595 | }, | |
596 | }; | |
597 | ||
598 | static struct uio_pruss_pdata da8xx_uio_pruss_pdata = { | |
599 | .pintc_base = 0x4000, | |
600 | }; | |
601 | ||
602 | static struct platform_device da8xx_uio_pruss_dev = { | |
603 | .name = "pruss_uio", | |
604 | .id = -1, | |
605 | .num_resources = ARRAY_SIZE(da8xx_pruss_resources), | |
606 | .resource = da8xx_pruss_resources, | |
607 | .dev = { | |
608 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
609 | .platform_data = &da8xx_uio_pruss_pdata, | |
610 | } | |
611 | }; | |
612 | ||
613 | int __init da8xx_register_uio_pruss(void) | |
614 | { | |
615 | da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool(); | |
616 | return platform_device_register(&da8xx_uio_pruss_dev); | |
617 | } | |
618 | ||
5cbdf276 | 619 | static struct lcd_ctrl_config lcd_cfg = { |
3b43ad20 | 620 | .panel_shade = COLOR_ACTIVE, |
5cbdf276 | 621 | .bpp = 16, |
5cbdf276 SR |
622 | }; |
623 | ||
b9e6342b MG |
624 | struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { |
625 | .manu_name = "sharp", | |
626 | .controller_data = &lcd_cfg, | |
627 | .type = "Sharp_LCD035Q3DG01", | |
628 | }; | |
629 | ||
630 | struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { | |
631 | .manu_name = "sharp", | |
632 | .controller_data = &lcd_cfg, | |
633 | .type = "Sharp_LK043T1DG01", | |
5cbdf276 SR |
634 | }; |
635 | ||
636 | static struct resource da8xx_lcdc_resources[] = { | |
637 | [0] = { /* registers */ | |
638 | .start = DA8XX_LCD_CNTRL_BASE, | |
639 | .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, | |
640 | .flags = IORESOURCE_MEM, | |
641 | }, | |
642 | [1] = { /* interrupt */ | |
643 | .start = IRQ_DA8XX_LCDINT, | |
644 | .end = IRQ_DA8XX_LCDINT, | |
645 | .flags = IORESOURCE_IRQ, | |
646 | }, | |
647 | }; | |
648 | ||
b9e6342b | 649 | static struct platform_device da8xx_lcdc_device = { |
5cbdf276 SR |
650 | .name = "da8xx_lcdc", |
651 | .id = 0, | |
652 | .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), | |
653 | .resource = da8xx_lcdc_resources, | |
5cbdf276 SR |
654 | }; |
655 | ||
b9e6342b | 656 | int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) |
5cbdf276 | 657 | { |
b9e6342b MG |
658 | da8xx_lcdc_device.dev.platform_data = pdata; |
659 | return platform_device_register(&da8xx_lcdc_device); | |
5cbdf276 | 660 | } |
700691f2 | 661 | |
f606d38d KS |
662 | static struct resource da8xx_gpio_resources[] = { |
663 | { /* registers */ | |
664 | .start = DA8XX_GPIO_BASE, | |
665 | .end = DA8XX_GPIO_BASE + SZ_4K - 1, | |
666 | .flags = IORESOURCE_MEM, | |
667 | }, | |
668 | { /* interrupt */ | |
669 | .start = IRQ_DA8XX_GPIO0, | |
670 | .end = IRQ_DA8XX_GPIO8, | |
671 | .flags = IORESOURCE_IRQ, | |
672 | }, | |
673 | }; | |
674 | ||
675 | static struct platform_device da8xx_gpio_device = { | |
676 | .name = "davinci_gpio", | |
677 | .id = -1, | |
678 | .num_resources = ARRAY_SIZE(da8xx_gpio_resources), | |
679 | .resource = da8xx_gpio_resources, | |
680 | }; | |
681 | ||
682 | int __init da8xx_register_gpio(void *pdata) | |
683 | { | |
684 | da8xx_gpio_device.dev.platform_data = pdata; | |
685 | return platform_device_register(&da8xx_gpio_device); | |
686 | } | |
687 | ||
700691f2 SR |
688 | static struct resource da8xx_mmcsd0_resources[] = { |
689 | { /* registers */ | |
690 | .start = DA8XX_MMCSD0_BASE, | |
691 | .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, | |
692 | .flags = IORESOURCE_MEM, | |
693 | }, | |
694 | { /* interrupt */ | |
695 | .start = IRQ_DA8XX_MMCSDINT0, | |
696 | .end = IRQ_DA8XX_MMCSDINT0, | |
697 | .flags = IORESOURCE_IRQ, | |
698 | }, | |
699 | { /* DMA RX */ | |
e38c2b22 MW |
700 | .start = DA8XX_DMA_MMCSD0_RX, |
701 | .end = DA8XX_DMA_MMCSD0_RX, | |
700691f2 SR |
702 | .flags = IORESOURCE_DMA, |
703 | }, | |
704 | { /* DMA TX */ | |
e38c2b22 MW |
705 | .start = DA8XX_DMA_MMCSD0_TX, |
706 | .end = DA8XX_DMA_MMCSD0_TX, | |
700691f2 SR |
707 | .flags = IORESOURCE_DMA, |
708 | }, | |
709 | }; | |
710 | ||
711 | static struct platform_device da8xx_mmcsd0_device = { | |
d7ca4c75 | 712 | .name = "da830-mmc", |
700691f2 SR |
713 | .id = 0, |
714 | .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), | |
715 | .resource = da8xx_mmcsd0_resources, | |
716 | }; | |
717 | ||
718 | int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) | |
719 | { | |
720 | da8xx_mmcsd0_device.dev.platform_data = config; | |
721 | return platform_device_register(&da8xx_mmcsd0_device); | |
722 | } | |
c51df70b | 723 | |
b8241aef JK |
724 | #ifdef CONFIG_ARCH_DAVINCI_DA850 |
725 | static struct resource da850_mmcsd1_resources[] = { | |
726 | { /* registers */ | |
727 | .start = DA850_MMCSD1_BASE, | |
728 | .end = DA850_MMCSD1_BASE + SZ_4K - 1, | |
729 | .flags = IORESOURCE_MEM, | |
730 | }, | |
731 | { /* interrupt */ | |
732 | .start = IRQ_DA850_MMCSDINT0_1, | |
733 | .end = IRQ_DA850_MMCSDINT0_1, | |
734 | .flags = IORESOURCE_IRQ, | |
735 | }, | |
736 | { /* DMA RX */ | |
e38c2b22 MW |
737 | .start = DA850_DMA_MMCSD1_RX, |
738 | .end = DA850_DMA_MMCSD1_RX, | |
b8241aef JK |
739 | .flags = IORESOURCE_DMA, |
740 | }, | |
741 | { /* DMA TX */ | |
e38c2b22 MW |
742 | .start = DA850_DMA_MMCSD1_TX, |
743 | .end = DA850_DMA_MMCSD1_TX, | |
b8241aef JK |
744 | .flags = IORESOURCE_DMA, |
745 | }, | |
746 | }; | |
747 | ||
748 | static struct platform_device da850_mmcsd1_device = { | |
d7ca4c75 | 749 | .name = "da830-mmc", |
b8241aef JK |
750 | .id = 1, |
751 | .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), | |
752 | .resource = da850_mmcsd1_resources, | |
753 | }; | |
754 | ||
755 | int __init da850_register_mmcsd1(struct davinci_mmc_config *config) | |
756 | { | |
757 | da850_mmcsd1_device.dev.platform_data = config; | |
758 | return platform_device_register(&da850_mmcsd1_device); | |
759 | } | |
760 | #endif | |
761 | ||
5c71d618 RT |
762 | static struct resource da8xx_rproc_resources[] = { |
763 | { /* DSP boot address */ | |
764 | .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG, | |
765 | .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3, | |
766 | .flags = IORESOURCE_MEM, | |
767 | }, | |
768 | { /* DSP interrupt registers */ | |
769 | .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG, | |
770 | .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7, | |
771 | .flags = IORESOURCE_MEM, | |
772 | }, | |
773 | { /* dsp irq */ | |
774 | .start = IRQ_DA8XX_CHIPINT0, | |
775 | .end = IRQ_DA8XX_CHIPINT0, | |
776 | .flags = IORESOURCE_IRQ, | |
777 | }, | |
778 | }; | |
779 | ||
780 | static struct platform_device da8xx_dsp = { | |
781 | .name = "davinci-rproc", | |
782 | .dev = { | |
783 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
784 | }, | |
785 | .num_resources = ARRAY_SIZE(da8xx_rproc_resources), | |
786 | .resource = da8xx_rproc_resources, | |
787 | }; | |
788 | ||
789 | #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC) | |
790 | ||
791 | static phys_addr_t rproc_base __initdata; | |
792 | static unsigned long rproc_size __initdata; | |
793 | ||
794 | static int __init early_rproc_mem(char *p) | |
795 | { | |
796 | char *endp; | |
797 | ||
798 | if (p == NULL) | |
799 | return 0; | |
800 | ||
801 | rproc_size = memparse(p, &endp); | |
802 | if (*endp == '@') | |
803 | rproc_base = memparse(endp + 1, NULL); | |
804 | ||
805 | return 0; | |
806 | } | |
807 | early_param("rproc_mem", early_rproc_mem); | |
808 | ||
809 | void __init da8xx_rproc_reserve_cma(void) | |
810 | { | |
811 | int ret; | |
812 | ||
813 | if (!rproc_base || !rproc_size) { | |
814 | pr_err("%s: 'rproc_mem=nn@address' badly specified\n" | |
815 | " 'nn' and 'address' must both be non-zero\n", | |
816 | __func__); | |
817 | ||
818 | return; | |
819 | } | |
820 | ||
821 | pr_info("%s: reserving 0x%lx @ 0x%lx...\n", | |
822 | __func__, rproc_size, (unsigned long)rproc_base); | |
823 | ||
824 | ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0); | |
825 | if (ret) | |
826 | pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret); | |
827 | } | |
828 | ||
829 | #else | |
830 | ||
831 | void __init da8xx_rproc_reserve_cma(void) | |
832 | { | |
833 | } | |
834 | ||
835 | #endif | |
836 | ||
837 | int __init da8xx_register_rproc(void) | |
838 | { | |
839 | int ret; | |
840 | ||
841 | ret = platform_device_register(&da8xx_dsp); | |
842 | if (ret) | |
843 | pr_err("%s: can't register DSP device: %d\n", __func__, ret); | |
844 | ||
845 | return ret; | |
846 | }; | |
847 | ||
c51df70b MG |
848 | static struct resource da8xx_rtc_resources[] = { |
849 | { | |
850 | .start = DA8XX_RTC_BASE, | |
851 | .end = DA8XX_RTC_BASE + SZ_4K - 1, | |
852 | .flags = IORESOURCE_MEM, | |
853 | }, | |
854 | { /* timer irq */ | |
855 | .start = IRQ_DA8XX_RTC, | |
856 | .end = IRQ_DA8XX_RTC, | |
857 | .flags = IORESOURCE_IRQ, | |
858 | }, | |
859 | { /* alarm irq */ | |
860 | .start = IRQ_DA8XX_RTC, | |
861 | .end = IRQ_DA8XX_RTC, | |
862 | .flags = IORESOURCE_IRQ, | |
863 | }, | |
864 | }; | |
865 | ||
866 | static struct platform_device da8xx_rtc_device = { | |
852168c9 | 867 | .name = "da830-rtc", |
c51df70b MG |
868 | .id = -1, |
869 | .num_resources = ARRAY_SIZE(da8xx_rtc_resources), | |
870 | .resource = da8xx_rtc_resources, | |
871 | }; | |
872 | ||
873 | int da8xx_register_rtc(void) | |
874 | { | |
79eb1636 | 875 | return platform_device_register(&da8xx_rtc_device); |
c51df70b | 876 | } |
1960e693 | 877 | |
948c66df SN |
878 | static void __iomem *da8xx_ddr2_ctlr_base; |
879 | void __iomem * __init da8xx_get_mem_ctlr(void) | |
880 | { | |
881 | if (da8xx_ddr2_ctlr_base) | |
882 | return da8xx_ddr2_ctlr_base; | |
883 | ||
884 | da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K); | |
885 | if (!da8xx_ddr2_ctlr_base) | |
d2e0c18a | 886 | pr_warn("%s: Unable to map DDR2 controller", __func__); |
948c66df SN |
887 | |
888 | return da8xx_ddr2_ctlr_base; | |
889 | } | |
890 | ||
1960e693 SN |
891 | static struct resource da8xx_cpuidle_resources[] = { |
892 | { | |
893 | .start = DA8XX_DDR2_CTL_BASE, | |
894 | .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1, | |
895 | .flags = IORESOURCE_MEM, | |
896 | }, | |
897 | }; | |
898 | ||
899 | /* DA8XX devices support DDR2 power down */ | |
900 | static struct davinci_cpuidle_config da8xx_cpuidle_pdata = { | |
901 | .ddr2_pdown = 1, | |
902 | }; | |
903 | ||
904 | ||
905 | static struct platform_device da8xx_cpuidle_device = { | |
906 | .name = "cpuidle-davinci", | |
907 | .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources), | |
908 | .resource = da8xx_cpuidle_resources, | |
909 | .dev = { | |
910 | .platform_data = &da8xx_cpuidle_pdata, | |
911 | }, | |
912 | }; | |
913 | ||
914 | int __init da8xx_register_cpuidle(void) | |
915 | { | |
948c66df SN |
916 | da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr(); |
917 | ||
1960e693 SN |
918 | return platform_device_register(&da8xx_cpuidle_device); |
919 | } | |
54ce6883 MW |
920 | |
921 | static struct resource da8xx_spi0_resources[] = { | |
922 | [0] = { | |
923 | .start = DA8XX_SPI0_BASE, | |
924 | .end = DA8XX_SPI0_BASE + SZ_4K - 1, | |
925 | .flags = IORESOURCE_MEM, | |
926 | }, | |
927 | [1] = { | |
928 | .start = IRQ_DA8XX_SPINT0, | |
929 | .end = IRQ_DA8XX_SPINT0, | |
930 | .flags = IORESOURCE_IRQ, | |
931 | }, | |
932 | [2] = { | |
933 | .start = DA8XX_DMA_SPI0_RX, | |
934 | .end = DA8XX_DMA_SPI0_RX, | |
935 | .flags = IORESOURCE_DMA, | |
936 | }, | |
937 | [3] = { | |
938 | .start = DA8XX_DMA_SPI0_TX, | |
939 | .end = DA8XX_DMA_SPI0_TX, | |
940 | .flags = IORESOURCE_DMA, | |
941 | }, | |
942 | }; | |
943 | ||
944 | static struct resource da8xx_spi1_resources[] = { | |
945 | [0] = { | |
9e7d24f6 SS |
946 | .start = DA830_SPI1_BASE, |
947 | .end = DA830_SPI1_BASE + SZ_4K - 1, | |
54ce6883 MW |
948 | .flags = IORESOURCE_MEM, |
949 | }, | |
950 | [1] = { | |
951 | .start = IRQ_DA8XX_SPINT1, | |
952 | .end = IRQ_DA8XX_SPINT1, | |
953 | .flags = IORESOURCE_IRQ, | |
954 | }, | |
955 | [2] = { | |
956 | .start = DA8XX_DMA_SPI1_RX, | |
957 | .end = DA8XX_DMA_SPI1_RX, | |
958 | .flags = IORESOURCE_DMA, | |
959 | }, | |
960 | [3] = { | |
961 | .start = DA8XX_DMA_SPI1_TX, | |
962 | .end = DA8XX_DMA_SPI1_TX, | |
963 | .flags = IORESOURCE_DMA, | |
964 | }, | |
965 | }; | |
966 | ||
0273612c | 967 | static struct davinci_spi_platform_data da8xx_spi_pdata[] = { |
54ce6883 MW |
968 | [0] = { |
969 | .version = SPI_VERSION_2, | |
970 | .intr_line = 1, | |
971 | .dma_event_q = EVENTQ_0, | |
972 | }, | |
973 | [1] = { | |
974 | .version = SPI_VERSION_2, | |
975 | .intr_line = 1, | |
976 | .dma_event_q = EVENTQ_0, | |
977 | }, | |
978 | }; | |
979 | ||
980 | static struct platform_device da8xx_spi_device[] = { | |
981 | [0] = { | |
982 | .name = "spi_davinci", | |
983 | .id = 0, | |
984 | .num_resources = ARRAY_SIZE(da8xx_spi0_resources), | |
985 | .resource = da8xx_spi0_resources, | |
986 | .dev = { | |
987 | .platform_data = &da8xx_spi_pdata[0], | |
988 | }, | |
989 | }, | |
990 | [1] = { | |
991 | .name = "spi_davinci", | |
992 | .id = 1, | |
993 | .num_resources = ARRAY_SIZE(da8xx_spi1_resources), | |
994 | .resource = da8xx_spi1_resources, | |
995 | .dev = { | |
996 | .platform_data = &da8xx_spi_pdata[1], | |
997 | }, | |
998 | }, | |
999 | }; | |
1000 | ||
0273612c | 1001 | int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect) |
54ce6883 | 1002 | { |
54ce6883 MW |
1003 | if (instance < 0 || instance > 1) |
1004 | return -EINVAL; | |
1005 | ||
0273612c | 1006 | da8xx_spi_pdata[instance].num_chipselect = num_chipselect; |
54ce6883 | 1007 | |
9e7d24f6 SS |
1008 | if (instance == 1 && cpu_is_davinci_da850()) { |
1009 | da8xx_spi1_resources[0].start = DA850_SPI1_BASE; | |
1010 | da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; | |
1011 | } | |
1012 | ||
54ce6883 MW |
1013 | return platform_device_register(&da8xx_spi_device[instance]); |
1014 | } | |
cbb2c961 SN |
1015 | |
1016 | #ifdef CONFIG_ARCH_DAVINCI_DA850 | |
cbb2c961 SN |
1017 | static struct resource da850_sata_resources[] = { |
1018 | { | |
1019 | .start = DA850_SATA_BASE, | |
1020 | .end = DA850_SATA_BASE + 0x1fff, | |
1021 | .flags = IORESOURCE_MEM, | |
1022 | }, | |
080c492d BZ |
1023 | { |
1024 | .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG, | |
1025 | .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3, | |
1026 | .flags = IORESOURCE_MEM, | |
1027 | }, | |
cbb2c961 SN |
1028 | { |
1029 | .start = IRQ_DA850_SATAINT, | |
1030 | .flags = IORESOURCE_IRQ, | |
1031 | }, | |
1032 | }; | |
1033 | ||
cbb2c961 SN |
1034 | static u64 da850_sata_dmamask = DMA_BIT_MASK(32); |
1035 | ||
1036 | static struct platform_device da850_sata_device = { | |
080c492d | 1037 | .name = "ahci_da850", |
cbb2c961 SN |
1038 | .id = -1, |
1039 | .dev = { | |
cbb2c961 SN |
1040 | .dma_mask = &da850_sata_dmamask, |
1041 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1042 | }, | |
1043 | .num_resources = ARRAY_SIZE(da850_sata_resources), | |
1044 | .resource = da850_sata_resources, | |
1045 | }; | |
1046 | ||
1047 | int __init da850_register_sata(unsigned long refclkpn) | |
1048 | { | |
080c492d BZ |
1049 | /* please see comment in drivers/ata/ahci_da850.c */ |
1050 | BUG_ON(refclkpn != 100 * 1000 * 1000); | |
cbb2c961 SN |
1051 | |
1052 | return platform_device_register(&da850_sata_device); | |
1053 | } | |
1054 | #endif |