[deliverable/linux.git] / arch / arm / mach-davinci / dm355.c

/*
 * TI DaVinci DM355 chip specific setup
 *
 * Author: Kevin Hilman, Deep Root Systems, LLC
 *
 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>

#include <linux/spi/spi.h>

#include <mach/dm355.h>
#include <mach/clock.h>
#include <mach/cputype.h>
#include <mach/edma.h>
#include <mach/psc.h>
#include <mach/mux.h>
#include <mach/irqs.h>

#include "clock.h"
#include "mux.h"

/*
 * Device specific clocks
 */
#define DM355_REF_FREQ		24000000	/* 24 or 36 MHz */

static struct pll_data pll1_data = {
	.num       = 1,
	.phys_base = DAVINCI_PLL1_BASE,
	.flags     = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
};

static struct pll_data pll2_data = {
	.num       = 2,
	.phys_base = DAVINCI_PLL2_BASE,
	.flags     = PLL_HAS_PREDIV,
};

static struct clk ref_clk = {
	.name = "ref_clk",
	/* FIXME -- crystal rate is board-specific */
	.rate = DM355_REF_FREQ,
};

static struct clk pll1_clk = {
	.name = "pll1",
	.parent = &ref_clk,
	.flags = CLK_PLL,
	.pll_data = &pll1_data,
};

static struct clk pll1_aux_clk = {
	.name = "pll1_aux_clk",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
};

static struct clk pll1_sysclk1 = {
	.name = "pll1_sysclk1",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk pll1_sysclk2 = {
	.name = "pll1_sysclk2",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV2,
};

static struct clk pll1_sysclk3 = {
	.name = "pll1_sysclk3",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV3,
};

static struct clk pll1_sysclk4 = {
	.name = "pll1_sysclk4",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV4,
};

static struct clk pll1_sysclkbp = {
	.name = "pll1_sysclkbp",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
	.div_reg = BPDIV
};

static struct clk vpss_dac_clk = {
	.name = "vpss_dac",
	.parent = &pll1_sysclk3,
	.lpsc = DM355_LPSC_VPSS_DAC,
};

static struct clk vpss_master_clk = {
	.name = "vpss_master",
	.parent = &pll1_sysclk4,
	.lpsc = DAVINCI_LPSC_VPSSMSTR,
	.flags = CLK_PSC,
};

static struct clk vpss_slave_clk = {
	.name = "vpss_slave",
	.parent = &pll1_sysclk4,
	.lpsc = DAVINCI_LPSC_VPSSSLV,
};


static struct clk clkout1_clk = {
	.name = "clkout1",
	.parent = &pll1_aux_clk,
	/* NOTE:  clkout1 can be externally gated by muxing GPIO-18 */
};

static struct clk clkout2_clk = {
	.name = "clkout2",
	.parent = &pll1_sysclkbp,
};

static struct clk pll2_clk = {
	.name = "pll2",
	.parent = &ref_clk,
	.flags = CLK_PLL,
	.pll_data = &pll2_data,
};

static struct clk pll2_sysclk1 = {
	.name = "pll2_sysclk1",
	.parent = &pll2_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk pll2_sysclkbp = {
	.name = "pll2_sysclkbp",
	.parent = &pll2_clk,
	.flags = CLK_PLL | PRE_PLL,
	.div_reg = BPDIV
};

static struct clk clkout3_clk = {
	.name = "clkout3",
	.parent = &pll2_sysclkbp,
	/* NOTE:  clkout3 can be externally gated by muxing GPIO-16 */
};

static struct clk arm_clk = {
	.name = "arm_clk",
	.parent = &pll1_sysclk1,
	.lpsc = DAVINCI_LPSC_ARM,
	.flags = ALWAYS_ENABLED,
};

/*
 * NOT LISTED below, and not touched by Linux
 *   - in SyncReset state by default
 *	.lpsc = DAVINCI_LPSC_TPCC,
 *	.lpsc = DAVINCI_LPSC_TPTC0,
 *	.lpsc = DAVINCI_LPSC_TPTC1,
 *	.lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
 *	.lpsc = DAVINCI_LPSC_MEMSTICK,
 *   - in Enabled state by default
 *	.lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
 *	.lpsc = DAVINCI_LPSC_SCR2,	// "bus"
 *	.lpsc = DAVINCI_LPSC_SCR3,	// "bus"
 *	.lpsc = DAVINCI_LPSC_SCR4,	// "bus"
 *	.lpsc = DAVINCI_LPSC_CROSSBAR,	// "emulation"
 *	.lpsc = DAVINCI_LPSC_CFG27,	// "test"
 *	.lpsc = DAVINCI_LPSC_CFG3,	// "test"
 *	.lpsc = DAVINCI_LPSC_CFG5,	// "test"
 */

static struct clk mjcp_clk = {
	.name = "mjcp",
	.parent = &pll1_sysclk1,
	.lpsc = DAVINCI_LPSC_IMCOP,
};

static struct clk uart0_clk = {
	.name = "uart0",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_UART0,
};

static struct clk uart1_clk = {
	.name = "uart1",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_UART1,
};

static struct clk uart2_clk = {
	.name = "uart2",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_UART2,
};

static struct clk i2c_clk = {
	.name = "i2c",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_I2C,
};

static struct clk asp0_clk = {
	.name = "asp0",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_McBSP,
};

static struct clk asp1_clk = {
	.name = "asp1",
	.parent = &pll1_sysclk2,
	.lpsc = DM355_LPSC_McBSP1,
};

static struct clk mmcsd0_clk = {
	.name = "mmcsd0",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_MMC_SD,
};

static struct clk mmcsd1_clk = {
	.name = "mmcsd1",
	.parent = &pll1_sysclk2,
	.lpsc = DM355_LPSC_MMC_SD1,
};

static struct clk spi0_clk = {
	.name = "spi0",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_SPI,
};

static struct clk spi1_clk = {
	.name = "spi1",
	.parent = &pll1_sysclk2,
	.lpsc = DM355_LPSC_SPI1,
};

static struct clk spi2_clk = {
	.name = "spi2",
	.parent = &pll1_sysclk2,
	.lpsc = DM355_LPSC_SPI2,
};

static struct clk gpio_clk = {
	.name = "gpio",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_GPIO,
};

static struct clk aemif_clk = {
	.name = "aemif",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_AEMIF,
};

static struct clk pwm0_clk = {
	.name = "pwm0",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_PWM0,
};

static struct clk pwm1_clk = {
	.name = "pwm1",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_PWM1,
};

static struct clk pwm2_clk = {
	.name = "pwm2",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_PWM2,
};

static struct clk pwm3_clk = {
	.name = "pwm3",
	.parent = &pll1_aux_clk,
	.lpsc = DM355_LPSC_PWM3,
};

static struct clk timer0_clk = {
	.name = "timer0",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_TIMER0,
};

static struct clk timer1_clk = {
	.name = "timer1",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_TIMER1,
};

static struct clk timer2_clk = {
	.name = "timer2",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_TIMER2,
	.usecount = 1,              /* REVISIT: why cant' this be disabled? */
};

static struct clk timer3_clk = {
	.name = "timer3",
	.parent = &pll1_aux_clk,
	.lpsc = DM355_LPSC_TIMER3,
};

static struct clk rto_clk = {
	.name = "rto",
	.parent = &pll1_aux_clk,
	.lpsc = DM355_LPSC_RTO,
};

static struct clk usb_clk = {
	.name = "usb",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_USB,
};

static struct davinci_clk dm355_clks[] = {
	CLK(NULL, "ref", &ref_clk),
	CLK(NULL, "pll1", &pll1_clk),
	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
	CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
	CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
	CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
	CLK(NULL, "pll1_aux", &pll1_aux_clk),
	CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
	CLK(NULL, "vpss_dac", &vpss_dac_clk),
	CLK(NULL, "vpss_master", &vpss_master_clk),
	CLK(NULL, "vpss_slave", &vpss_slave_clk),
	CLK(NULL, "clkout1", &clkout1_clk),
	CLK(NULL, "clkout2", &clkout2_clk),
	CLK(NULL, "pll2", &pll2_clk),
	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
	CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
	CLK(NULL, "clkout3", &clkout3_clk),
	CLK(NULL, "arm", &arm_clk),
	CLK(NULL, "mjcp", &mjcp_clk),
	CLK(NULL, "uart0", &uart0_clk),
	CLK(NULL, "uart1", &uart1_clk),
	CLK(NULL, "uart2", &uart2_clk),
	CLK("i2c_davinci.1", NULL, &i2c_clk),
	CLK("soc-audio.0", NULL, &asp0_clk),
	CLK("soc-audio.1", NULL, &asp1_clk),
	CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
	CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
	CLK(NULL, "spi0", &spi0_clk),
	CLK(NULL, "spi1", &spi1_clk),
	CLK(NULL, "spi2", &spi2_clk),
	CLK(NULL, "gpio", &gpio_clk),
	CLK(NULL, "aemif", &aemif_clk),
	CLK(NULL, "pwm0", &pwm0_clk),
	CLK(NULL, "pwm1", &pwm1_clk),
	CLK(NULL, "pwm2", &pwm2_clk),
	CLK(NULL, "pwm3", &pwm3_clk),
	CLK(NULL, "timer0", &timer0_clk),
	CLK(NULL, "timer1", &timer1_clk),
	CLK("watchdog", NULL, &timer2_clk),
	CLK(NULL, "timer3", &timer3_clk),
	CLK(NULL, "rto", &rto_clk),
	CLK(NULL, "usb", &usb_clk),
	CLK(NULL, NULL, NULL),
};

/*----------------------------------------------------------------------*/

static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);

static struct resource dm355_spi0_resources[] = {
	{
		.start = 0x01c66000,
		.end   = 0x01c667ff,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_DM355_SPINT0_1,
		.flags = IORESOURCE_IRQ,
	},
	/* Not yet used, so not included:
	 * IORESOURCE_IRQ:
	 *  - IRQ_DM355_SPINT0_0
	 * IORESOURCE_DMA:
	 *  - DAVINCI_DMA_SPI_SPIX
	 *  - DAVINCI_DMA_SPI_SPIR
	 */
};

static struct platform_device dm355_spi0_device = {
	.name = "spi_davinci",
	.id = 0,
	.dev = {
		.dma_mask = &dm355_spi0_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.num_resources = ARRAY_SIZE(dm355_spi0_resources),
	.resource = dm355_spi0_resources,
};

void __init dm355_init_spi0(unsigned chipselect_mask,
		struct spi_board_info *info, unsigned len)
{
	/* for now, assume we need MISO */
	davinci_cfg_reg(DM355_SPI0_SDI);

	/* not all slaves will be wired up */
	if (chipselect_mask & BIT(0))
		davinci_cfg_reg(DM355_SPI0_SDENA0);
	if (chipselect_mask & BIT(1))
		davinci_cfg_reg(DM355_SPI0_SDENA1);

	spi_register_board_info(info, len);

	platform_device_register(&dm355_spi0_device);
}

/*----------------------------------------------------------------------*/

/*
 * Device specific mux setup
 *
 *	soc	description	mux  mode   mode  mux	 dbg
 *				reg  offset mask  mode
 */
static const struct mux_config dm355_pins[] = {
MUX_CFG(DM355,	MMCSD0,		4,   2,     1,	  0,	 false)

MUX_CFG(DM355,	SD1_CLK,	3,   6,     1,	  1,	 false)
MUX_CFG(DM355,	SD1_CMD,	3,   7,     1,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA3,	3,   8,     3,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA2,	3,   10,    3,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA1,	3,   12,    3,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA0,	3,   14,    3,	  1,	 false)

MUX_CFG(DM355,	I2C_SDA,	3,   19,    1,	  1,	 false)
MUX_CFG(DM355,	I2C_SCL,	3,   20,    1,	  1,	 false)

MUX_CFG(DM355,	MCBSP0_BDX,	3,   0,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_X,	3,   1,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_BFSX,	3,   2,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_BDR,	3,   3,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_R,	3,   4,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_BFSR,	3,   5,     1,	  1,	 false)

MUX_CFG(DM355,	SPI0_SDI,	4,   1,     1,    0,	 false)
MUX_CFG(DM355,	SPI0_SDENA0,	4,   0,     1,    0,	 false)
MUX_CFG(DM355,	SPI0_SDENA1,	3,   28,    1,    1,	 false)

INT_CFG(DM355,  INT_EDMA_CC,	      2,    1,    1,     false)
INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)

EVT_CFG(DM355,  EVT8_ASP1_TX,	      0,    1,    0,     false)
EVT_CFG(DM355,  EVT9_ASP1_RX,	      1,    1,    0,     false)
EVT_CFG(DM355,  EVT26_MMC0_RX,	      2,    1,    0,     false)
};

/*----------------------------------------------------------------------*/

static const s8 dma_chan_dm355_no_event[] = {
	12, 13, 24, 56, 57,
	58, 59, 60, 61, 62,
	63,
	-1
};

static struct edma_soc_info dm355_edma_info = {
	.n_channel	= 64,
	.n_region	= 4,
	.n_slot		= 128,
	.n_tc		= 2,
	.noevent	= dma_chan_dm355_no_event,
};

static struct resource edma_resources[] = {
	{
		.name	= "edma_cc",
		.start	= 0x01c00000,
		.end	= 0x01c00000 + SZ_64K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc0",
		.start	= 0x01c10000,
		.end	= 0x01c10000 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc1",
		.start	= 0x01c10400,
		.end	= 0x01c10400 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_CCINT0,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_CCERRINT,
		.flags	= IORESOURCE_IRQ,
	},
	/* not using (or muxing) TC*_ERR */
};

static struct platform_device dm355_edma_device = {
	.name			= "edma",
	.id			= -1,
	.dev.platform_data	= &dm355_edma_info,
	.num_resources		= ARRAY_SIZE(edma_resources),
	.resource		= edma_resources,
};

/*----------------------------------------------------------------------*/

void __init dm355_init(void)
{
	davinci_clk_init(dm355_clks);
	davinci_mux_register(dm355_pins, ARRAY_SIZE(dm355_pins));;
}

static int __init dm355_init_devices(void)
{
	if (!cpu_is_davinci_dm355())
		return 0;

	davinci_cfg_reg(DM355_INT_EDMA_CC);
	platform_device_register(&dm355_edma_device);
	return 0;
}
postcore_initcall(dm355_init_devices);
Commit	Line	Data
95a3477f KH	1	/*
	2	* TI DaVinci DM355 chip specific setup
	3	*
	4	* Author: Kevin Hilman, Deep Root Systems, LLC
	5	*
	6	* 2007 (c) Deep Root Systems, LLC. This file is licensed under
	7	* the terms of the GNU General Public License version 2. This program
	8	* is licensed "as is" without any warranty of any kind, whether express
	9	* or implied.
	10	*/
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/clk.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/dma-mapping.h>
	16
	17	#include <linux/spi/spi.h>
	18
	19	#include <mach/dm355.h>
	20	#include <mach/clock.h>
	21	#include <mach/cputype.h>
	22	#include <mach/edma.h>
	23	#include <mach/psc.h>
	24	#include <mach/mux.h>
	25	#include <mach/irqs.h>
	26
	27	#include "clock.h"
	28	#include "mux.h"
	29
	30	/*
	31	* Device specific clocks
	32	*/
	33	#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
	34
	35	static struct pll_data pll1_data = {
	36	.num = 1,
	37	.phys_base = DAVINCI_PLL1_BASE,
	38	.flags = PLL_HAS_PREDIV \| PLL_HAS_POSTDIV,
	39	};
	40
	41	static struct pll_data pll2_data = {
	42	.num = 2,
	43	.phys_base = DAVINCI_PLL2_BASE,
	44	.flags = PLL_HAS_PREDIV,
	45	};
	46
	47	static struct clk ref_clk = {
	48	.name = "ref_clk",
	49	/* FIXME -- crystal rate is board-specific */
	50	.rate = DM355_REF_FREQ,
	51	};
	52
	53	static struct clk pll1_clk = {
	54	.name = "pll1",
	55	.parent = &ref_clk,
	56	.flags = CLK_PLL,
	57	.pll_data = &pll1_data,
	58	};
	59
	60	static struct clk pll1_aux_clk = {
	61	.name = "pll1_aux_clk",
	62	.parent = &pll1_clk,
	63	.flags = CLK_PLL \| PRE_PLL,
	64	};
65
66	static struct clk pll1_sysclk1 = {
67	.name = "pll1_sysclk1",
68	.parent = &pll1_clk,
69	.flags = CLK_PLL,
70	.div_reg = PLLDIV1,
71	};
72
73	static struct clk pll1_sysclk2 = {
74	.name = "pll1_sysclk2",
75	.parent = &pll1_clk,
76	.flags = CLK_PLL,
77	.div_reg = PLLDIV2,
78	};
79
80	static struct clk pll1_sysclk3 = {
81	.name = "pll1_sysclk3",
82	.parent = &pll1_clk,
83	.flags = CLK_PLL,
84	.div_reg = PLLDIV3,
85	};
86
87	static struct clk pll1_sysclk4 = {
88	.name = "pll1_sysclk4",
89	.parent = &pll1_clk,
90	.flags = CLK_PLL,
91	.div_reg = PLLDIV4,
92	};
93
94	static struct clk pll1_sysclkbp = {
95	.name = "pll1_sysclkbp",
96	.parent = &pll1_clk,
97	.flags = CLK_PLL \| PRE_PLL,
98	.div_reg = BPDIV
99	};
100
101	static struct clk vpss_dac_clk = {
102	.name = "vpss_dac",
103	.parent = &pll1_sysclk3,
104	.lpsc = DM355_LPSC_VPSS_DAC,
105	};
106
107	static struct clk vpss_master_clk = {
108	.name = "vpss_master",
109	.parent = &pll1_sysclk4,
110	.lpsc = DAVINCI_LPSC_VPSSMSTR,
111	.flags = CLK_PSC,
112	};
113
114	static struct clk vpss_slave_clk = {
115	.name = "vpss_slave",
116	.parent = &pll1_sysclk4,
117	.lpsc = DAVINCI_LPSC_VPSSSLV,
118	};
119
120
121	static struct clk clkout1_clk = {
122	.name = "clkout1",
123	.parent = &pll1_aux_clk,
124	/* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
125	};
126
127	static struct clk clkout2_clk = {
128	.name = "clkout2",
129	.parent = &pll1_sysclkbp,
130	};
131
132	static struct clk pll2_clk = {
133	.name = "pll2",
134	.parent = &ref_clk,
135	.flags = CLK_PLL,
136	.pll_data = &pll2_data,
137	};
138
139	static struct clk pll2_sysclk1 = {
140	.name = "pll2_sysclk1",
141	.parent = &pll2_clk,
142	.flags = CLK_PLL,
143	.div_reg = PLLDIV1,
144	};
145
146	static struct clk pll2_sysclkbp = {
147	.name = "pll2_sysclkbp",
148	.parent = &pll2_clk,
149	.flags = CLK_PLL \| PRE_PLL,
150	.div_reg = BPDIV
151	};
152
153	static struct clk clkout3_clk = {
154	.name = "clkout3",
155	.parent = &pll2_sysclkbp,
156	/* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
157	};
158
159	static struct clk arm_clk = {
160	.name = "arm_clk",
161	.parent = &pll1_sysclk1,
162	.lpsc = DAVINCI_LPSC_ARM,
163	.flags = ALWAYS_ENABLED,
164	};
165
166	/*
167	* NOT LISTED below, and not touched by Linux
168	* - in SyncReset state by default
169	* .lpsc = DAVINCI_LPSC_TPCC,
170	* .lpsc = DAVINCI_LPSC_TPTC0,
171	* .lpsc = DAVINCI_LPSC_TPTC1,
172	* .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
173	* .lpsc = DAVINCI_LPSC_MEMSTICK,
174	* - in Enabled state by default
175	* .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
176	* .lpsc = DAVINCI_LPSC_SCR2, // "bus"
177	* .lpsc = DAVINCI_LPSC_SCR3, // "bus"
178	* .lpsc = DAVINCI_LPSC_SCR4, // "bus"
179	* .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
180	* .lpsc = DAVINCI_LPSC_CFG27, // "test"
181	* .lpsc = DAVINCI_LPSC_CFG3, // "test"
182	* .lpsc = DAVINCI_LPSC_CFG5, // "test"
183	*/
184
185	static struct clk mjcp_clk = {
186	.name = "mjcp",
187	.parent = &pll1_sysclk1,
188	.lpsc = DAVINCI_LPSC_IMCOP,
189	};
190
191	static struct clk uart0_clk = {
192	.name = "uart0",
193	.parent = &pll1_aux_clk,
194	.lpsc = DAVINCI_LPSC_UART0,
195	};
196
197	static struct clk uart1_clk = {
198	.name = "uart1",
199	.parent = &pll1_aux_clk,
200	.lpsc = DAVINCI_LPSC_UART1,
201	};
202
203	static struct clk uart2_clk = {
204	.name = "uart2",
205	.parent = &pll1_sysclk2,
206	.lpsc = DAVINCI_LPSC_UART2,
207	};
208
209	static struct clk i2c_clk = {
210	.name = "i2c",
211	.parent = &pll1_aux_clk,
212	.lpsc = DAVINCI_LPSC_I2C,
213	};
214
215	static struct clk asp0_clk = {
216	.name = "asp0",
217	.parent = &pll1_sysclk2,
218	.lpsc = DAVINCI_LPSC_McBSP,
219	};
220
221	static struct clk asp1_clk = {
222	.name = "asp1",
223	.parent = &pll1_sysclk2,
224	.lpsc = DM355_LPSC_McBSP1,
225	};
226
227	static struct clk mmcsd0_clk = {
228	.name = "mmcsd0",
229	.parent = &pll1_sysclk2,
230	.lpsc = DAVINCI_LPSC_MMC_SD,
231	};
232
233	static struct clk mmcsd1_clk = {
234	.name = "mmcsd1",
235	.parent = &pll1_sysclk2,
236	.lpsc = DM355_LPSC_MMC_SD1,
237	};
238
239	static struct clk spi0_clk = {
240	.name = "spi0",
241	.parent = &pll1_sysclk2,
242	.lpsc = DAVINCI_LPSC_SPI,
243	};
244
245	static struct clk spi1_clk = {
246	.name = "spi1",
247	.parent = &pll1_sysclk2,
248	.lpsc = DM355_LPSC_SPI1,
249	};
250
251	static struct clk spi2_clk = {
252	.name = "spi2",
253	.parent = &pll1_sysclk2,
254	.lpsc = DM355_LPSC_SPI2,
255	};
256
257	static struct clk gpio_clk = {
258	.name = "gpio",
259	.parent = &pll1_sysclk2,
260	.lpsc = DAVINCI_LPSC_GPIO,
261	};
262
263	static struct clk aemif_clk = {
264	.name = "aemif",
265	.parent = &pll1_sysclk2,
266	.lpsc = DAVINCI_LPSC_AEMIF,
267	};
268
269	static struct clk pwm0_clk = {
270	.name = "pwm0",
271	.parent = &pll1_aux_clk,
272	.lpsc = DAVINCI_LPSC_PWM0,
273	};
274
275	static struct clk pwm1_clk = {
276	.name = "pwm1",
277	.parent = &pll1_aux_clk,
278	.lpsc = DAVINCI_LPSC_PWM1,
279	};
280
281	static struct clk pwm2_clk = {
282	.name = "pwm2",
283	.parent = &pll1_aux_clk,
284	.lpsc = DAVINCI_LPSC_PWM2,
285	};
286
287	static struct clk pwm3_clk = {
288	.name = "pwm3",
289	.parent = &pll1_aux_clk,
290	.lpsc = DM355_LPSC_PWM3,
291	};
292
293	static struct clk timer0_clk = {
294	.name = "timer0",
295	.parent = &pll1_aux_clk,
296	.lpsc = DAVINCI_LPSC_TIMER0,
297	};
298
299	static struct clk timer1_clk = {
300	.name = "timer1",
301	.parent = &pll1_aux_clk,
302	.lpsc = DAVINCI_LPSC_TIMER1,
303	};
304
305	static struct clk timer2_clk = {
306	.name = "timer2",
307	.parent = &pll1_aux_clk,
308	.lpsc = DAVINCI_LPSC_TIMER2,
309	.usecount = 1, /* REVISIT: why cant' this be disabled? */
310	};
311
312	static struct clk timer3_clk = {
313	.name = "timer3",
314	.parent = &pll1_aux_clk,
315	.lpsc = DM355_LPSC_TIMER3,
316	};
317
318	static struct clk rto_clk = {
319	.name = "rto",
320	.parent = &pll1_aux_clk,
321	.lpsc = DM355_LPSC_RTO,
322	};
323
324	static struct clk usb_clk = {
325	.name = "usb",
326	.parent = &pll1_sysclk2,
327	.lpsc = DAVINCI_LPSC_USB,
328	};
329
330	static struct davinci_clk dm355_clks[] = {
331	CLK(NULL, "ref", &ref_clk),
332	CLK(NULL, "pll1", &pll1_clk),
333	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
334	CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
335	CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
336	CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
337	CLK(NULL, "pll1_aux", &pll1_aux_clk),
338	CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
339	CLK(NULL, "vpss_dac", &vpss_dac_clk),
340	CLK(NULL, "vpss_master", &vpss_master_clk),
341	CLK(NULL, "vpss_slave", &vpss_slave_clk),
342	CLK(NULL, "clkout1", &clkout1_clk),
343	CLK(NULL, "clkout2", &clkout2_clk),
344	CLK(NULL, "pll2", &pll2_clk),
345	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
346	CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
347	CLK(NULL, "clkout3", &clkout3_clk),
348	CLK(NULL, "arm", &arm_clk),
349	CLK(NULL, "mjcp", &mjcp_clk),
350	CLK(NULL, "uart0", &uart0_clk),
351	CLK(NULL, "uart1", &uart1_clk),
352	CLK(NULL, "uart2", &uart2_clk),
353	CLK("i2c_davinci.1", NULL, &i2c_clk),
354	CLK("soc-audio.0", NULL, &asp0_clk),
355	CLK("soc-audio.1", NULL, &asp1_clk),
356	CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
357	CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
358	CLK(NULL, "spi0", &spi0_clk),
359	CLK(NULL, "spi1", &spi1_clk),
360	CLK(NULL, "spi2", &spi2_clk),
361	CLK(NULL, "gpio", &gpio_clk),
362	CLK(NULL, "aemif", &aemif_clk),
363	CLK(NULL, "pwm0", &pwm0_clk),
364	CLK(NULL, "pwm1", &pwm1_clk),
365	CLK(NULL, "pwm2", &pwm2_clk),
366	CLK(NULL, "pwm3", &pwm3_clk),
367	CLK(NULL, "timer0", &timer0_clk),
368	CLK(NULL, "timer1", &timer1_clk),
369	CLK("watchdog", NULL, &timer2_clk),
370	CLK(NULL, "timer3", &timer3_clk),
371	CLK(NULL, "rto", &rto_clk),
372	CLK(NULL, "usb", &usb_clk),
373	CLK(NULL, NULL, NULL),
374	};
375
376	/----------------------------------------------------------------------/
377
378	static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
379
380	static struct resource dm355_spi0_resources[] = {
381	{
382	.start = 0x01c66000,
383	.end = 0x01c667ff,
384	.flags = IORESOURCE_MEM,
385	},
386	{
387	.start = IRQ_DM355_SPINT0_1,
388	.flags = IORESOURCE_IRQ,
389	},
390	/* Not yet used, so not included:
391	* IORESOURCE_IRQ:
392	* - IRQ_DM355_SPINT0_0
393	* IORESOURCE_DMA:
394	* - DAVINCI_DMA_SPI_SPIX
395	* - DAVINCI_DMA_SPI_SPIR
396	*/
397	};
398
399	static struct platform_device dm355_spi0_device = {
400	.name = "spi_davinci",
401	.id = 0,
402	.dev = {
403	.dma_mask = &dm355_spi0_dma_mask,
404	.coherent_dma_mask = DMA_BIT_MASK(32),
405	},
406	.num_resources = ARRAY_SIZE(dm355_spi0_resources),
407	.resource = dm355_spi0_resources,
408	};
409
410	void __init dm355_init_spi0(unsigned chipselect_mask,
411	struct spi_board_info *info, unsigned len)
412	{
413	/* for now, assume we need MISO */
414	davinci_cfg_reg(DM355_SPI0_SDI);
415
416	/* not all slaves will be wired up */
417	if (chipselect_mask & BIT(0))
418	davinci_cfg_reg(DM355_SPI0_SDENA0);
419	if (chipselect_mask & BIT(1))
420	davinci_cfg_reg(DM355_SPI0_SDENA1);
421
422	spi_register_board_info(info, len);
423
424	platform_device_register(&dm355_spi0_device);
425	}
426
427	/----------------------------------------------------------------------/
428
429	/*
430	* Device specific mux setup
431	*
432	* soc description mux mode mode mux dbg
433	* reg offset mask mode
434	*/
435	static const struct mux_config dm355_pins[] = {
436	MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
437
438	MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
439	MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
440	MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
441	MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
442	MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
443	MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
444
445	MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
446	MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
447
448	MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
449	MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
450	MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
451	MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
452	MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
453	MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
454
455	MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
456	MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
457	MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
458
459	INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
460	INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
461	INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
462
463	EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
464	EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
465	EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
466	};
467
468	/----------------------------------------------------------------------/
469
470	static const s8 dma_chan_dm355_no_event[] = {
471	12, 13, 24, 56, 57,
472	58, 59, 60, 61, 62,
473	63,
474	-1
475	};
476
477	static struct edma_soc_info dm355_edma_info = {
478	.n_channel = 64,
479	.n_region = 4,
480	.n_slot = 128,
481	.n_tc = 2,
482	.noevent = dma_chan_dm355_no_event,
483	};
484
485	static struct resource edma_resources[] = {
486	{
487	.name = "edma_cc",
488	.start = 0x01c00000,
489	.end = 0x01c00000 + SZ_64K - 1,
490	.flags = IORESOURCE_MEM,
491	},
492	{
493	.name = "edma_tc0",
494	.start = 0x01c10000,
495	.end = 0x01c10000 + SZ_1K - 1,
496	.flags = IORESOURCE_MEM,
497	},
498	{
499	.name = "edma_tc1",
500	.start = 0x01c10400,
501	.end = 0x01c10400 + SZ_1K - 1,
502	.flags = IORESOURCE_MEM,
503	},
504	{
505	.start = IRQ_CCINT0,
506	.flags = IORESOURCE_IRQ,
507	},
508	{
509	.start = IRQ_CCERRINT,
510	.flags = IORESOURCE_IRQ,
511	},
512	/* not using (or muxing) TC_ERR /
513	};
514
515	static struct platform_device dm355_edma_device = {
516	.name = "edma",
517	.id = -1,
518	.dev.platform_data = &dm355_edma_info,
519	.num_resources = ARRAY_SIZE(edma_resources),
520	.resource = edma_resources,
521	};
522
523	/----------------------------------------------------------------------/
524
525	void __init dm355_init(void)
526	{
527	davinci_clk_init(dm355_clks);
528	davinci_mux_register(dm355_pins, ARRAY_SIZE(dm355_pins));;
529	}
530
531	static int __init dm355_init_devices(void)
532	{
533	if (!cpu_is_davinci_dm355())
534	return 0;
535
536	davinci_cfg_reg(DM355_INT_EDMA_CC);
537	platform_device_register(&dm355_edma_device);
538	return 0;
539	}
540	postcore_initcall(dm355_init_devices);