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d0e47fba KH |
1 | /* |
2 | * TI DaVinci DM644x chip specific setup | |
3 | * | |
4 | * Author: Kevin Hilman, Deep Root Systems, LLC | |
5 | * | |
6 | * 2007 (c) Deep Root Systems, LLC. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/platform_device.h> | |
15 | ||
79c3c0b7 MG |
16 | #include <asm/mach/map.h> |
17 | ||
d0e47fba KH |
18 | #include <mach/dm644x.h> |
19 | #include <mach/clock.h> | |
20 | #include <mach/cputype.h> | |
21 | #include <mach/edma.h> | |
22 | #include <mach/irqs.h> | |
23 | #include <mach/psc.h> | |
24 | #include <mach/mux.h> | |
79c3c0b7 | 25 | #include <mach/common.h> |
d0e47fba KH |
26 | |
27 | #include "clock.h" | |
28 | #include "mux.h" | |
29 | ||
30 | /* | |
31 | * Device specific clocks | |
32 | */ | |
33 | #define DM644X_REF_FREQ 27000000 | |
34 | ||
35 | static struct pll_data pll1_data = { | |
36 | .num = 1, | |
37 | .phys_base = DAVINCI_PLL1_BASE, | |
38 | }; | |
39 | ||
40 | static struct pll_data pll2_data = { | |
41 | .num = 2, | |
42 | .phys_base = DAVINCI_PLL2_BASE, | |
43 | }; | |
44 | ||
45 | static struct clk ref_clk = { | |
46 | .name = "ref_clk", | |
47 | .rate = DM644X_REF_FREQ, | |
48 | }; | |
49 | ||
50 | static struct clk pll1_clk = { | |
51 | .name = "pll1", | |
52 | .parent = &ref_clk, | |
53 | .pll_data = &pll1_data, | |
54 | .flags = CLK_PLL, | |
55 | }; | |
56 | ||
57 | static struct clk pll1_sysclk1 = { | |
58 | .name = "pll1_sysclk1", | |
59 | .parent = &pll1_clk, | |
60 | .flags = CLK_PLL, | |
61 | .div_reg = PLLDIV1, | |
62 | }; | |
63 | ||
64 | static struct clk pll1_sysclk2 = { | |
65 | .name = "pll1_sysclk2", | |
66 | .parent = &pll1_clk, | |
67 | .flags = CLK_PLL, | |
68 | .div_reg = PLLDIV2, | |
69 | }; | |
70 | ||
71 | static struct clk pll1_sysclk3 = { | |
72 | .name = "pll1_sysclk3", | |
73 | .parent = &pll1_clk, | |
74 | .flags = CLK_PLL, | |
75 | .div_reg = PLLDIV3, | |
76 | }; | |
77 | ||
78 | static struct clk pll1_sysclk5 = { | |
79 | .name = "pll1_sysclk5", | |
80 | .parent = &pll1_clk, | |
81 | .flags = CLK_PLL, | |
82 | .div_reg = PLLDIV5, | |
83 | }; | |
84 | ||
85 | static struct clk pll1_aux_clk = { | |
86 | .name = "pll1_aux_clk", | |
87 | .parent = &pll1_clk, | |
88 | .flags = CLK_PLL | PRE_PLL, | |
89 | }; | |
90 | ||
91 | static struct clk pll1_sysclkbp = { | |
92 | .name = "pll1_sysclkbp", | |
93 | .parent = &pll1_clk, | |
94 | .flags = CLK_PLL | PRE_PLL, | |
95 | .div_reg = BPDIV | |
96 | }; | |
97 | ||
98 | static struct clk pll2_clk = { | |
99 | .name = "pll2", | |
100 | .parent = &ref_clk, | |
101 | .pll_data = &pll2_data, | |
102 | .flags = CLK_PLL, | |
103 | }; | |
104 | ||
105 | static struct clk pll2_sysclk1 = { | |
106 | .name = "pll2_sysclk1", | |
107 | .parent = &pll2_clk, | |
108 | .flags = CLK_PLL, | |
109 | .div_reg = PLLDIV1, | |
110 | }; | |
111 | ||
112 | static struct clk pll2_sysclk2 = { | |
113 | .name = "pll2_sysclk2", | |
114 | .parent = &pll2_clk, | |
115 | .flags = CLK_PLL, | |
116 | .div_reg = PLLDIV2, | |
117 | }; | |
118 | ||
119 | static struct clk pll2_sysclkbp = { | |
120 | .name = "pll2_sysclkbp", | |
121 | .parent = &pll2_clk, | |
122 | .flags = CLK_PLL | PRE_PLL, | |
123 | .div_reg = BPDIV | |
124 | }; | |
125 | ||
126 | static struct clk dsp_clk = { | |
127 | .name = "dsp", | |
128 | .parent = &pll1_sysclk1, | |
129 | .lpsc = DAVINCI_LPSC_GEM, | |
130 | .flags = PSC_DSP, | |
131 | .usecount = 1, /* REVISIT how to disable? */ | |
132 | }; | |
133 | ||
134 | static struct clk arm_clk = { | |
135 | .name = "arm", | |
136 | .parent = &pll1_sysclk2, | |
137 | .lpsc = DAVINCI_LPSC_ARM, | |
138 | .flags = ALWAYS_ENABLED, | |
139 | }; | |
140 | ||
141 | static struct clk vicp_clk = { | |
142 | .name = "vicp", | |
143 | .parent = &pll1_sysclk2, | |
144 | .lpsc = DAVINCI_LPSC_IMCOP, | |
145 | .flags = PSC_DSP, | |
146 | .usecount = 1, /* REVISIT how to disable? */ | |
147 | }; | |
148 | ||
149 | static struct clk vpss_master_clk = { | |
150 | .name = "vpss_master", | |
151 | .parent = &pll1_sysclk3, | |
152 | .lpsc = DAVINCI_LPSC_VPSSMSTR, | |
153 | .flags = CLK_PSC, | |
154 | }; | |
155 | ||
156 | static struct clk vpss_slave_clk = { | |
157 | .name = "vpss_slave", | |
158 | .parent = &pll1_sysclk3, | |
159 | .lpsc = DAVINCI_LPSC_VPSSSLV, | |
160 | }; | |
161 | ||
162 | static struct clk uart0_clk = { | |
163 | .name = "uart0", | |
164 | .parent = &pll1_aux_clk, | |
165 | .lpsc = DAVINCI_LPSC_UART0, | |
166 | }; | |
167 | ||
168 | static struct clk uart1_clk = { | |
169 | .name = "uart1", | |
170 | .parent = &pll1_aux_clk, | |
171 | .lpsc = DAVINCI_LPSC_UART1, | |
172 | }; | |
173 | ||
174 | static struct clk uart2_clk = { | |
175 | .name = "uart2", | |
176 | .parent = &pll1_aux_clk, | |
177 | .lpsc = DAVINCI_LPSC_UART2, | |
178 | }; | |
179 | ||
180 | static struct clk emac_clk = { | |
181 | .name = "emac", | |
182 | .parent = &pll1_sysclk5, | |
183 | .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, | |
184 | }; | |
185 | ||
186 | static struct clk i2c_clk = { | |
187 | .name = "i2c", | |
188 | .parent = &pll1_aux_clk, | |
189 | .lpsc = DAVINCI_LPSC_I2C, | |
190 | }; | |
191 | ||
192 | static struct clk ide_clk = { | |
193 | .name = "ide", | |
194 | .parent = &pll1_sysclk5, | |
195 | .lpsc = DAVINCI_LPSC_ATA, | |
196 | }; | |
197 | ||
198 | static struct clk asp_clk = { | |
199 | .name = "asp0", | |
200 | .parent = &pll1_sysclk5, | |
201 | .lpsc = DAVINCI_LPSC_McBSP, | |
202 | }; | |
203 | ||
204 | static struct clk mmcsd_clk = { | |
205 | .name = "mmcsd", | |
206 | .parent = &pll1_sysclk5, | |
207 | .lpsc = DAVINCI_LPSC_MMC_SD, | |
208 | }; | |
209 | ||
210 | static struct clk spi_clk = { | |
211 | .name = "spi", | |
212 | .parent = &pll1_sysclk5, | |
213 | .lpsc = DAVINCI_LPSC_SPI, | |
214 | }; | |
215 | ||
216 | static struct clk gpio_clk = { | |
217 | .name = "gpio", | |
218 | .parent = &pll1_sysclk5, | |
219 | .lpsc = DAVINCI_LPSC_GPIO, | |
220 | }; | |
221 | ||
222 | static struct clk usb_clk = { | |
223 | .name = "usb", | |
224 | .parent = &pll1_sysclk5, | |
225 | .lpsc = DAVINCI_LPSC_USB, | |
226 | }; | |
227 | ||
228 | static struct clk vlynq_clk = { | |
229 | .name = "vlynq", | |
230 | .parent = &pll1_sysclk5, | |
231 | .lpsc = DAVINCI_LPSC_VLYNQ, | |
232 | }; | |
233 | ||
234 | static struct clk aemif_clk = { | |
235 | .name = "aemif", | |
236 | .parent = &pll1_sysclk5, | |
237 | .lpsc = DAVINCI_LPSC_AEMIF, | |
238 | }; | |
239 | ||
240 | static struct clk pwm0_clk = { | |
241 | .name = "pwm0", | |
242 | .parent = &pll1_aux_clk, | |
243 | .lpsc = DAVINCI_LPSC_PWM0, | |
244 | }; | |
245 | ||
246 | static struct clk pwm1_clk = { | |
247 | .name = "pwm1", | |
248 | .parent = &pll1_aux_clk, | |
249 | .lpsc = DAVINCI_LPSC_PWM1, | |
250 | }; | |
251 | ||
252 | static struct clk pwm2_clk = { | |
253 | .name = "pwm2", | |
254 | .parent = &pll1_aux_clk, | |
255 | .lpsc = DAVINCI_LPSC_PWM2, | |
256 | }; | |
257 | ||
258 | static struct clk timer0_clk = { | |
259 | .name = "timer0", | |
260 | .parent = &pll1_aux_clk, | |
261 | .lpsc = DAVINCI_LPSC_TIMER0, | |
262 | }; | |
263 | ||
264 | static struct clk timer1_clk = { | |
265 | .name = "timer1", | |
266 | .parent = &pll1_aux_clk, | |
267 | .lpsc = DAVINCI_LPSC_TIMER1, | |
268 | }; | |
269 | ||
270 | static struct clk timer2_clk = { | |
271 | .name = "timer2", | |
272 | .parent = &pll1_aux_clk, | |
273 | .lpsc = DAVINCI_LPSC_TIMER2, | |
274 | .usecount = 1, /* REVISIT: why cant' this be disabled? */ | |
275 | }; | |
276 | ||
277 | struct davinci_clk dm644x_clks[] = { | |
278 | CLK(NULL, "ref", &ref_clk), | |
279 | CLK(NULL, "pll1", &pll1_clk), | |
280 | CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), | |
281 | CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), | |
282 | CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), | |
283 | CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), | |
284 | CLK(NULL, "pll1_aux", &pll1_aux_clk), | |
285 | CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), | |
286 | CLK(NULL, "pll2", &pll2_clk), | |
287 | CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), | |
288 | CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), | |
289 | CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), | |
290 | CLK(NULL, "dsp", &dsp_clk), | |
291 | CLK(NULL, "arm", &arm_clk), | |
292 | CLK(NULL, "vicp", &vicp_clk), | |
293 | CLK(NULL, "vpss_master", &vpss_master_clk), | |
294 | CLK(NULL, "vpss_slave", &vpss_slave_clk), | |
295 | CLK(NULL, "arm", &arm_clk), | |
296 | CLK(NULL, "uart0", &uart0_clk), | |
297 | CLK(NULL, "uart1", &uart1_clk), | |
298 | CLK(NULL, "uart2", &uart2_clk), | |
299 | CLK("davinci_emac.1", NULL, &emac_clk), | |
300 | CLK("i2c_davinci.1", NULL, &i2c_clk), | |
301 | CLK("palm_bk3710", NULL, &ide_clk), | |
302 | CLK("soc-audio.0", NULL, &asp_clk), | |
303 | CLK("davinci_mmc.0", NULL, &mmcsd_clk), | |
304 | CLK(NULL, "spi", &spi_clk), | |
305 | CLK(NULL, "gpio", &gpio_clk), | |
306 | CLK(NULL, "usb", &usb_clk), | |
307 | CLK(NULL, "vlynq", &vlynq_clk), | |
308 | CLK(NULL, "aemif", &aemif_clk), | |
309 | CLK(NULL, "pwm0", &pwm0_clk), | |
310 | CLK(NULL, "pwm1", &pwm1_clk), | |
311 | CLK(NULL, "pwm2", &pwm2_clk), | |
312 | CLK(NULL, "timer0", &timer0_clk), | |
313 | CLK(NULL, "timer1", &timer1_clk), | |
314 | CLK("watchdog", NULL, &timer2_clk), | |
315 | CLK(NULL, NULL, NULL), | |
316 | }; | |
317 | ||
318 | #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE) | |
319 | ||
320 | static struct resource dm644x_emac_resources[] = { | |
321 | { | |
322 | .start = DM644X_EMAC_BASE, | |
323 | .end = DM644X_EMAC_BASE + 0x47ff, | |
324 | .flags = IORESOURCE_MEM, | |
325 | }, | |
326 | { | |
327 | .start = IRQ_EMACINT, | |
328 | .end = IRQ_EMACINT, | |
329 | .flags = IORESOURCE_IRQ, | |
330 | }, | |
331 | }; | |
332 | ||
333 | static struct platform_device dm644x_emac_device = { | |
334 | .name = "davinci_emac", | |
335 | .id = 1, | |
336 | .num_resources = ARRAY_SIZE(dm644x_emac_resources), | |
337 | .resource = dm644x_emac_resources, | |
338 | }; | |
339 | ||
340 | #endif | |
341 | ||
342 | /* | |
343 | * Device specific mux setup | |
344 | * | |
345 | * soc description mux mode mode mux dbg | |
346 | * reg offset mask mode | |
347 | */ | |
348 | static const struct mux_config dm644x_pins[] = { | |
0e585952 | 349 | #ifdef CONFIG_DAVINCI_MUX |
d0e47fba KH |
350 | MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true) |
351 | MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true) | |
352 | MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true) | |
353 | ||
354 | MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true) | |
355 | ||
356 | MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true) | |
357 | ||
358 | MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false) | |
359 | ||
360 | MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false) | |
361 | ||
362 | MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false) | |
363 | ||
364 | MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true) | |
365 | MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true) | |
366 | ||
367 | MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false) | |
368 | ||
369 | MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false) | |
370 | ||
371 | MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false) | |
372 | ||
373 | MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false) | |
374 | MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false) | |
375 | MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false) | |
376 | ||
377 | MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true) | |
378 | ||
379 | MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true) | |
380 | ||
381 | MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true) | |
382 | MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false) | |
383 | MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false) | |
384 | MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true) | |
385 | ||
386 | MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true) | |
387 | ||
388 | MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true) | |
389 | MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false) | |
0e585952 | 390 | #endif |
d0e47fba KH |
391 | }; |
392 | ||
d0e47fba KH |
393 | /*----------------------------------------------------------------------*/ |
394 | ||
395 | static const s8 dma_chan_dm644x_no_event[] = { | |
396 | 0, 1, 12, 13, 14, | |
397 | 15, 25, 30, 31, 45, | |
398 | 46, 47, 55, 56, 57, | |
399 | 58, 59, 60, 61, 62, | |
400 | 63, | |
401 | -1 | |
402 | }; | |
403 | ||
404 | static struct edma_soc_info dm644x_edma_info = { | |
405 | .n_channel = 64, | |
406 | .n_region = 4, | |
407 | .n_slot = 128, | |
408 | .n_tc = 2, | |
409 | .noevent = dma_chan_dm644x_no_event, | |
410 | }; | |
411 | ||
412 | static struct resource edma_resources[] = { | |
413 | { | |
414 | .name = "edma_cc", | |
415 | .start = 0x01c00000, | |
416 | .end = 0x01c00000 + SZ_64K - 1, | |
417 | .flags = IORESOURCE_MEM, | |
418 | }, | |
419 | { | |
420 | .name = "edma_tc0", | |
421 | .start = 0x01c10000, | |
422 | .end = 0x01c10000 + SZ_1K - 1, | |
423 | .flags = IORESOURCE_MEM, | |
424 | }, | |
425 | { | |
426 | .name = "edma_tc1", | |
427 | .start = 0x01c10400, | |
428 | .end = 0x01c10400 + SZ_1K - 1, | |
429 | .flags = IORESOURCE_MEM, | |
430 | }, | |
431 | { | |
432 | .start = IRQ_CCINT0, | |
433 | .flags = IORESOURCE_IRQ, | |
434 | }, | |
435 | { | |
436 | .start = IRQ_CCERRINT, | |
437 | .flags = IORESOURCE_IRQ, | |
438 | }, | |
439 | /* not using TC*_ERR */ | |
440 | }; | |
441 | ||
442 | static struct platform_device dm644x_edma_device = { | |
443 | .name = "edma", | |
444 | .id = -1, | |
445 | .dev.platform_data = &dm644x_edma_info, | |
446 | .num_resources = ARRAY_SIZE(edma_resources), | |
447 | .resource = edma_resources, | |
448 | }; | |
449 | ||
450 | /*----------------------------------------------------------------------*/ | |
ac7b75b5 KH |
451 | #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE) |
452 | ||
453 | void dm644x_init_emac(struct emac_platform_data *pdata) | |
454 | { | |
455 | pdata->ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET; | |
456 | pdata->ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET; | |
457 | pdata->ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET; | |
458 | pdata->mdio_reg_offset = DM644X_EMAC_MDIO_OFFSET; | |
459 | pdata->ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE; | |
460 | pdata->version = EMAC_VERSION_1; | |
461 | dm644x_emac_device.dev.platform_data = pdata; | |
462 | platform_device_register(&dm644x_emac_device); | |
463 | } | |
464 | #else | |
465 | ||
466 | void dm644x_init_emac(struct emac_platform_data *unused) {} | |
467 | ||
468 | #endif | |
469 | ||
79c3c0b7 MG |
470 | static struct map_desc dm644x_io_desc[] = { |
471 | { | |
472 | .virtual = IO_VIRT, | |
473 | .pfn = __phys_to_pfn(IO_PHYS), | |
474 | .length = IO_SIZE, | |
475 | .type = MT_DEVICE | |
476 | }, | |
477 | }; | |
478 | ||
b9ab1279 MG |
479 | /* Contents of JTAG ID register used to identify exact cpu type */ |
480 | static struct davinci_id dm644x_ids[] = { | |
481 | { | |
482 | .variant = 0x0, | |
483 | .part_no = 0xb700, | |
484 | .manufacturer = 0x017, | |
485 | .cpu_id = DAVINCI_CPU_ID_DM6446, | |
486 | .name = "dm6446", | |
487 | }, | |
488 | }; | |
489 | ||
d81d188c MG |
490 | static void __iomem *dm644x_psc_bases[] = { |
491 | IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), | |
492 | }; | |
493 | ||
79c3c0b7 MG |
494 | static struct davinci_soc_info davinci_soc_info_dm644x = { |
495 | .io_desc = dm644x_io_desc, | |
496 | .io_desc_num = ARRAY_SIZE(dm644x_io_desc), | |
b9ab1279 MG |
497 | .jtag_id_base = IO_ADDRESS(0x01c40028), |
498 | .ids = dm644x_ids, | |
499 | .ids_num = ARRAY_SIZE(dm644x_ids), | |
66e0c399 | 500 | .cpu_clks = dm644x_clks, |
d81d188c MG |
501 | .psc_bases = dm644x_psc_bases, |
502 | .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), | |
0e585952 MG |
503 | .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), |
504 | .pinmux_pins = dm644x_pins, | |
505 | .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), | |
79c3c0b7 MG |
506 | }; |
507 | ||
d0e47fba KH |
508 | void __init dm644x_init(void) |
509 | { | |
79c3c0b7 | 510 | davinci_common_init(&davinci_soc_info_dm644x); |
d0e47fba KH |
511 | } |
512 | ||
513 | static int __init dm644x_init_devices(void) | |
514 | { | |
515 | if (!cpu_is_davinci_dm644x()) | |
516 | return 0; | |
517 | ||
518 | platform_device_register(&dm644x_edma_device); | |
519 | return 0; | |
520 | } | |
521 | postcore_initcall(dm644x_init_devices); |