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ARM: davinci/common: Convert edma driver to handle one eDMA instance per driver
[deliverable/linux.git] / arch / arm / mach-davinci / dm644x.c
CommitLineData
d0e47fba
KH		 1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
d0e47fba
KH		 11#include <linux/init.h>
12#include <linux/clk.h>
65e866a9 13#include <linux/serial_8250.h>
d0e47fba 14#include <linux/platform_device.h>
3ad7a42d 15#include <linux/platform_data/edma.h>
9cc1515c 16#include <linux/platform_data/gpio-davinci.h>
d0e47fba 17
79c3c0b7
MG		 18#include <asm/mach/map.h>
19
d0e47fba 20#include <mach/cputype.h>
d0e47fba
KH		 21#include <mach/irqs.h>
22#include <mach/psc.h>
23#include <mach/mux.h>
f64691b3 24#include <mach/time.h>
65e866a9 25#include <mach/serial.h>
79c3c0b7 26#include <mach/common.h>
d0e47fba 27
39c6d2d1 28#include "davinci.h"
d0e47fba
KH		 29#include "clock.h"
30#include "mux.h"
896f66b7 31#include "asp.h"
d0e47fba
KH		 32
33/*
34 * Device specific clocks
35 */
36#define DM644X_REF_FREQ 27000000
37
887b8a93
MH		 38#define DM644X_EMAC_BASE 0x01c80000
39#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
40#define DM644X_EMAC_CNTRL_OFFSET 0x0000
41#define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
42#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
43#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
44
d0e47fba
KH		 45static struct pll_data pll1_data = {
46 .num = 1,
47 .phys_base = DAVINCI_PLL1_BASE,
48};
49
50static struct pll_data pll2_data = {
51 .num = 2,
52 .phys_base = DAVINCI_PLL2_BASE,
53};
54
55static struct clk ref_clk = {
56 .name = "ref_clk",
57 .rate = DM644X_REF_FREQ,
58};
59
60static struct clk pll1_clk = {
61 .name = "pll1",
62 .parent = &ref_clk,
63 .pll_data = &pll1_data,
64 .flags = CLK_PLL,
65};
66
67static struct clk pll1_sysclk1 = {
68 .name = "pll1_sysclk1",
69 .parent = &pll1_clk,
70 .flags = CLK_PLL,
71 .div_reg = PLLDIV1,
72};
73
74static struct clk pll1_sysclk2 = {
75 .name = "pll1_sysclk2",
76 .parent = &pll1_clk,
77 .flags = CLK_PLL,
78 .div_reg = PLLDIV2,
79};
80
81static struct clk pll1_sysclk3 = {
82 .name = "pll1_sysclk3",
83 .parent = &pll1_clk,
84 .flags = CLK_PLL,
85 .div_reg = PLLDIV3,
86};
87
88static struct clk pll1_sysclk5 = {
89 .name = "pll1_sysclk5",
90 .parent = &pll1_clk,
91 .flags = CLK_PLL,
92 .div_reg = PLLDIV5,
93};
94
95static struct clk pll1_aux_clk = {
96 .name = "pll1_aux_clk",
97 .parent = &pll1_clk,
98 .flags = CLK_PLL | PRE_PLL,
99};
100
101static struct clk pll1_sysclkbp = {
102 .name = "pll1_sysclkbp",
103 .parent = &pll1_clk,
104 .flags = CLK_PLL | PRE_PLL,
105 .div_reg = BPDIV
106};
107
108static struct clk pll2_clk = {
109 .name = "pll2",
110 .parent = &ref_clk,
111 .pll_data = &pll2_data,
112 .flags = CLK_PLL,
113};
114
115static struct clk pll2_sysclk1 = {
116 .name = "pll2_sysclk1",
117 .parent = &pll2_clk,
118 .flags = CLK_PLL,
119 .div_reg = PLLDIV1,
120};
121
122static struct clk pll2_sysclk2 = {
123 .name = "pll2_sysclk2",
124 .parent = &pll2_clk,
125 .flags = CLK_PLL,
126 .div_reg = PLLDIV2,
127};
128
129static struct clk pll2_sysclkbp = {
130 .name = "pll2_sysclkbp",
131 .parent = &pll2_clk,
132 .flags = CLK_PLL | PRE_PLL,
133 .div_reg = BPDIV
134};
135
136static struct clk dsp_clk = {
137 .name = "dsp",
138 .parent = &pll1_sysclk1,
139 .lpsc = DAVINCI_LPSC_GEM,
12221d43 140 .domain = DAVINCI_GPSC_DSPDOMAIN,
d0e47fba
KH		 141 .usecount = 1, /* REVISIT how to disable? */
142};
143
144static struct clk arm_clk = {
145 .name = "arm",
146 .parent = &pll1_sysclk2,
147 .lpsc = DAVINCI_LPSC_ARM,
148 .flags = ALWAYS_ENABLED,
149};
150
151static struct clk vicp_clk = {
152 .name = "vicp",
153 .parent = &pll1_sysclk2,
154 .lpsc = DAVINCI_LPSC_IMCOP,
12221d43 155 .domain = DAVINCI_GPSC_DSPDOMAIN,
d0e47fba
KH		 156 .usecount = 1, /* REVISIT how to disable? */
157};
158
159static struct clk vpss_master_clk = {
160 .name = "vpss_master",
161 .parent = &pll1_sysclk3,
162 .lpsc = DAVINCI_LPSC_VPSSMSTR,
163 .flags = CLK_PSC,
164};
165
166static struct clk vpss_slave_clk = {
167 .name = "vpss_slave",
168 .parent = &pll1_sysclk3,
169 .lpsc = DAVINCI_LPSC_VPSSSLV,
170};
171
172static struct clk uart0_clk = {
173 .name = "uart0",
174 .parent = &pll1_aux_clk,
175 .lpsc = DAVINCI_LPSC_UART0,
176};
177
178static struct clk uart1_clk = {
179 .name = "uart1",
180 .parent = &pll1_aux_clk,
181 .lpsc = DAVINCI_LPSC_UART1,
182};
183
184static struct clk uart2_clk = {
185 .name = "uart2",
186 .parent = &pll1_aux_clk,
187 .lpsc = DAVINCI_LPSC_UART2,
188};
189
190static struct clk emac_clk = {
191 .name = "emac",
192 .parent = &pll1_sysclk5,
193 .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
194};
195
196static struct clk i2c_clk = {
197 .name = "i2c",
198 .parent = &pll1_aux_clk,
199 .lpsc = DAVINCI_LPSC_I2C,
200};
201
202static struct clk ide_clk = {
203 .name = "ide",
204 .parent = &pll1_sysclk5,
205 .lpsc = DAVINCI_LPSC_ATA,
206};
207
208static struct clk asp_clk = {
209 .name = "asp0",
210 .parent = &pll1_sysclk5,
211 .lpsc = DAVINCI_LPSC_McBSP,
212};
213
214static struct clk mmcsd_clk = {
215 .name = "mmcsd",
216 .parent = &pll1_sysclk5,
217 .lpsc = DAVINCI_LPSC_MMC_SD,
218};
219
220static struct clk spi_clk = {
221 .name = "spi",
222 .parent = &pll1_sysclk5,
223 .lpsc = DAVINCI_LPSC_SPI,
224};
225
226static struct clk gpio_clk = {
227 .name = "gpio",
228 .parent = &pll1_sysclk5,
229 .lpsc = DAVINCI_LPSC_GPIO,
230};
231
232static struct clk usb_clk = {
233 .name = "usb",
234 .parent = &pll1_sysclk5,
235 .lpsc = DAVINCI_LPSC_USB,
236};
237
238static struct clk vlynq_clk = {
239 .name = "vlynq",
240 .parent = &pll1_sysclk5,
241 .lpsc = DAVINCI_LPSC_VLYNQ,
242};
243
244static struct clk aemif_clk = {
245 .name = "aemif",
246 .parent = &pll1_sysclk5,
247 .lpsc = DAVINCI_LPSC_AEMIF,
248};
249
250static struct clk pwm0_clk = {
251 .name = "pwm0",
252 .parent = &pll1_aux_clk,
253 .lpsc = DAVINCI_LPSC_PWM0,
254};
255
256static struct clk pwm1_clk = {
257 .name = "pwm1",
258 .parent = &pll1_aux_clk,
259 .lpsc = DAVINCI_LPSC_PWM1,
260};
261
262static struct clk pwm2_clk = {
263 .name = "pwm2",
264 .parent = &pll1_aux_clk,
265 .lpsc = DAVINCI_LPSC_PWM2,
266};
267
268static struct clk timer0_clk = {
269 .name = "timer0",
270 .parent = &pll1_aux_clk,
271 .lpsc = DAVINCI_LPSC_TIMER0,
272};
273
274static struct clk timer1_clk = {
275 .name = "timer1",
276 .parent = &pll1_aux_clk,
277 .lpsc = DAVINCI_LPSC_TIMER1,
278};
279
280static struct clk timer2_clk = {
281 .name = "timer2",
282 .parent = &pll1_aux_clk,
283 .lpsc = DAVINCI_LPSC_TIMER2,
e9c54999 284 .usecount = 1, /* REVISIT: why can't this be disabled? */
d0e47fba
KH		 285};
286
28552c2e 287static struct clk_lookup dm644x_clks[] = {
d0e47fba
KH		 288 CLK(NULL, "ref", &ref_clk),
289 CLK(NULL, "pll1", &pll1_clk),
290 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
291 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
292 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
293 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
294 CLK(NULL, "pll1_aux", &pll1_aux_clk),
295 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
296 CLK(NULL, "pll2", &pll2_clk),
297 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
298 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
299 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
300 CLK(NULL, "dsp", &dsp_clk),
301 CLK(NULL, "arm", &arm_clk),
302 CLK(NULL, "vicp", &vicp_clk),
9a3e89b1
LP		 303 CLK("vpss", "master", &vpss_master_clk),
304 CLK("vpss", "slave", &vpss_slave_clk),
d0e47fba 305 CLK(NULL, "arm", &arm_clk),
19955c3d
MP		 306 CLK("serial8250.0", NULL, &uart0_clk),
307 CLK("serial8250.1", NULL, &uart1_clk),
308 CLK("serial8250.2", NULL, &uart2_clk),
d0e47fba 309 CLK("davinci_emac.1", NULL, &emac_clk),
46c18334 310 CLK("davinci_mdio.0", "fck", &emac_clk),
d0e47fba
KH		 311 CLK("i2c_davinci.1", NULL, &i2c_clk),
312 CLK("palm_bk3710", NULL, &ide_clk),
bedad0ca 313 CLK("davinci-mcbsp", NULL, &asp_clk),
d7ca4c75 314 CLK("dm6441-mmc.0", NULL, &mmcsd_clk),
d0e47fba
KH		 315 CLK(NULL, "spi", &spi_clk),
316 CLK(NULL, "gpio", &gpio_clk),
317 CLK(NULL, "usb", &usb_clk),
318 CLK(NULL, "vlynq", &vlynq_clk),
319 CLK(NULL, "aemif", &aemif_clk),
320 CLK(NULL, "pwm0", &pwm0_clk),
321 CLK(NULL, "pwm1", &pwm1_clk),
322 CLK(NULL, "pwm2", &pwm2_clk),
323 CLK(NULL, "timer0", &timer0_clk),
324 CLK(NULL, "timer1", &timer1_clk),
84374812 325 CLK("davinci-wdt", NULL, &timer2_clk),
d0e47fba
KH		 326 CLK(NULL, NULL, NULL),
327};
328
972412b6
MG		 329static struct emac_platform_data dm644x_emac_pdata = {
330 .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
331 .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
332 .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
972412b6
MG		 333 .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
334 .version = EMAC_VERSION_1,
335};
d0e47fba
KH		 336
337static struct resource dm644x_emac_resources[] = {
338 {
339 .start = DM644X_EMAC_BASE,
d22960c8 340 .end = DM644X_EMAC_BASE + SZ_16K - 1,
d0e47fba
KH		 341 .flags = IORESOURCE_MEM,
342 },
343 {
344 .start = IRQ_EMACINT,
345 .end = IRQ_EMACINT,
346 .flags = IORESOURCE_IRQ,
347 },
348};
349
350static struct platform_device dm644x_emac_device = {
351 .name = "davinci_emac",
352 .id = 1,
972412b6
MG		 353 .dev = {
354 .platform_data = &dm644x_emac_pdata,
355 },
d0e47fba
KH		 356 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
357 .resource = dm644x_emac_resources,
358};
359
d22960c8
CC		 360static struct resource dm644x_mdio_resources[] = {
361 {
362 .start = DM644X_EMAC_MDIO_BASE,
363 .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
364 .flags = IORESOURCE_MEM,
365 },
366};
367
368static struct platform_device dm644x_mdio_device = {
369 .name = "davinci_mdio",
370 .id = 0,
371 .num_resources = ARRAY_SIZE(dm644x_mdio_resources),
372 .resource = dm644x_mdio_resources,
373};
374
d0e47fba
KH		 375/*
376 * Device specific mux setup
377 *
378 * soc description mux mode mode mux dbg
379 * reg offset mask mode
380 */
381static const struct mux_config dm644x_pins[] = {
0e585952 382#ifdef CONFIG_DAVINCI_MUX
d0e47fba
KH		 383MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
384MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
385MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
386
387MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
388
389MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
c16fe267
AP		 390MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
391MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
392MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
393MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
394MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
d0e47fba
KH		 395
396MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
397
398MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
399
400MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
401
402MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
403MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
404
405MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
406
407MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
408
409MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
410
411MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
412MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
413MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
414
415MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
416
417MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
418
419MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
420MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
421MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
422MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
423
424MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
425
426MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
427MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
0e585952 428#endif
d0e47fba
KH		 429};
430
673dd36f
MG		 431/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
432static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
433 [IRQ_VDINT0] = 2,
434 [IRQ_VDINT1] = 6,
435 [IRQ_VDINT2] = 6,
436 [IRQ_HISTINT] = 6,
437 [IRQ_H3AINT] = 6,
438 [IRQ_PRVUINT] = 6,
439 [IRQ_RSZINT] = 6,
440 [7] = 7,
441 [IRQ_VENCINT] = 6,
442 [IRQ_ASQINT] = 6,
443 [IRQ_IMXINT] = 6,
444 [IRQ_VLCDINT] = 6,
445 [IRQ_USBINT] = 4,
446 [IRQ_EMACINT] = 4,
447 [14] = 7,
448 [15] = 7,
449 [IRQ_CCINT0] = 5, /* dma */
450 [IRQ_CCERRINT] = 5, /* dma */
451 [IRQ_TCERRINT0] = 5, /* dma */
452 [IRQ_TCERRINT] = 5, /* dma */
453 [IRQ_PSCIN] = 7,
454 [21] = 7,
455 [IRQ_IDE] = 4,
456 [23] = 7,
457 [IRQ_MBXINT] = 7,
458 [IRQ_MBRINT] = 7,
459 [IRQ_MMCINT] = 7,
460 [IRQ_SDIOINT] = 7,
461 [28] = 7,
462 [IRQ_DDRINT] = 7,
463 [IRQ_AEMIFINT] = 7,
464 [IRQ_VLQINT] = 4,
465 [IRQ_TINT0_TINT12] = 2, /* clockevent */
466 [IRQ_TINT0_TINT34] = 2, /* clocksource */
467 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
468 [IRQ_TINT1_TINT34] = 7, /* system tick */
469 [IRQ_PWMINT0] = 7,
470 [IRQ_PWMINT1] = 7,
471 [IRQ_PWMINT2] = 7,
472 [IRQ_I2C] = 3,
473 [IRQ_UARTINT0] = 3,
474 [IRQ_UARTINT1] = 3,
475 [IRQ_UARTINT2] = 3,
476 [IRQ_SPINT0] = 3,
477 [IRQ_SPINT1] = 3,
478 [45] = 7,
479 [IRQ_DSP2ARM0] = 4,
480 [IRQ_DSP2ARM1] = 4,
481 [IRQ_GPIO0] = 7,
482 [IRQ_GPIO1] = 7,
483 [IRQ_GPIO2] = 7,
484 [IRQ_GPIO3] = 7,
485 [IRQ_GPIO4] = 7,
486 [IRQ_GPIO5] = 7,
487 [IRQ_GPIO6] = 7,
488 [IRQ_GPIO7] = 7,
489 [IRQ_GPIOBNK0] = 7,
490 [IRQ_GPIOBNK1] = 7,
491 [IRQ_GPIOBNK2] = 7,
492 [IRQ_GPIOBNK3] = 7,
493 [IRQ_GPIOBNK4] = 7,
494 [IRQ_COMMTX] = 7,
495 [IRQ_COMMRX] = 7,
496 [IRQ_EMUINT] = 7,
497};
498
d0e47fba
KH		 499/*----------------------------------------------------------------------*/
500
d4cb7f40 501static s8 queue_priority_mapping[][2] = {
60902a2c
SR		 502 /* {event queue no, Priority} */
503 {0, 3},
504 {1, 7},
505 {-1, -1},
506};
507
d4cb7f40 508static struct edma_soc_info dm644x_edma_pdata = {
bc3ac9f3 509 .queue_priority_mapping = queue_priority_mapping,
f23fe857 510 .default_queue = EVENTQ_1,
bc3ac9f3
SN		 511};
512
d0e47fba
KH		 513static struct resource edma_resources[] = {
514 {
d4cb7f40 515 .name = "edma3_cc",
d0e47fba
KH		 516 .start = 0x01c00000,
517 .end = 0x01c00000 + SZ_64K - 1,
518 .flags = IORESOURCE_MEM,
519 },
520 {
d4cb7f40 521 .name = "edma3_tc0",
d0e47fba
KH		 522 .start = 0x01c10000,
523 .end = 0x01c10000 + SZ_1K - 1,
524 .flags = IORESOURCE_MEM,
525 },
526 {
d4cb7f40 527 .name = "edma3_tc1",
d0e47fba
KH		 528 .start = 0x01c10400,
529 .end = 0x01c10400 + SZ_1K - 1,
530 .flags = IORESOURCE_MEM,
531 },
532 {
d4cb7f40 533 .name = "edma3_ccint",
d0e47fba
KH		 534 .start = IRQ_CCINT0,
535 .flags = IORESOURCE_IRQ,
536 },
537 {
d4cb7f40 538 .name = "edma3_ccerrint",
d0e47fba
KH		 539 .start = IRQ_CCERRINT,
540 .flags = IORESOURCE_IRQ,
541 },
542 /* not using TC*_ERR */
543};
544
545static struct platform_device dm644x_edma_device = {
546 .name = "edma",
60902a2c 547 .id = 0,
d4cb7f40 548 .dev.platform_data = &dm644x_edma_pdata,
d0e47fba
KH		 549 .num_resources = ARRAY_SIZE(edma_resources),
550 .resource = edma_resources,
551};
552
25acf553
C		 553/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
554static struct resource dm644x_asp_resources[] = {
555 {
ee880dbd 556 .name = "mpu",
25acf553
C		 557 .start = DAVINCI_ASP0_BASE,
558 .end = DAVINCI_ASP0_BASE + SZ_8K - 1,
559 .flags = IORESOURCE_MEM,
560 },
561 {
562 .start = DAVINCI_DMA_ASP0_TX,
563 .end = DAVINCI_DMA_ASP0_TX,
564 .flags = IORESOURCE_DMA,
565 },
566 {
567 .start = DAVINCI_DMA_ASP0_RX,
568 .end = DAVINCI_DMA_ASP0_RX,
569 .flags = IORESOURCE_DMA,
570 },
571};
572
573static struct platform_device dm644x_asp_device = {
bedad0ca 574 .name = "davinci-mcbsp",
25acf553
C		 575 .id = -1,
576 .num_resources = ARRAY_SIZE(dm644x_asp_resources),
577 .resource = dm644x_asp_resources,
578};
579
51f31cb3
MH		 580#define DM644X_VPSS_BASE 0x01c73400
581
ab8e8df8
MK		 582static struct resource dm644x_vpss_resources[] = {
583 {
584 /* VPSS Base address */
585 .name = "vpss",
51f31cb3
MH		 586 .start = DM644X_VPSS_BASE,
587 .end = DM644X_VPSS_BASE + 0xff,
588 .flags = IORESOURCE_MEM,
ab8e8df8
MK		 589 },
590};
591
592static struct platform_device dm644x_vpss_device = {
593 .name = "vpss",
594 .id = -1,
595 .dev.platform_data = "dm644x_vpss",
596 .num_resources = ARRAY_SIZE(dm644x_vpss_resources),
597 .resource = dm644x_vpss_resources,
598};
599
314d7389 600static struct resource dm644x_vpfe_resources[] = {
ab8e8df8
MK		 601 {
602 .start = IRQ_VDINT0,
603 .end = IRQ_VDINT0,
604 .flags = IORESOURCE_IRQ,
605 },
606 {
607 .start = IRQ_VDINT1,
608 .end = IRQ_VDINT1,
609 .flags = IORESOURCE_IRQ,
610 },
77c8b5fb
MK		 611};
612
af946f26 613static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
77c8b5fb
MK		 614static struct resource dm644x_ccdc_resource[] = {
615 /* CCDC Base address */
ab8e8df8
MK		 616 {
617 .start = 0x01c70400,
618 .end = 0x01c70400 + 0xff,
619 .flags = IORESOURCE_MEM,
620 },
621};
622
77c8b5fb
MK		 623static struct platform_device dm644x_ccdc_dev = {
624 .name = "dm644x_ccdc",
625 .id = -1,
626 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
627 .resource = dm644x_ccdc_resource,
628 .dev = {
af946f26 629 .dma_mask = &dm644x_video_dma_mask,
77c8b5fb
MK		 630 .coherent_dma_mask = DMA_BIT_MASK(32),
631 },
632};
633
314d7389 634static struct platform_device dm644x_vpfe_dev = {
ab8e8df8
MK		 635 .name = CAPTURE_DRV_NAME,
636 .id = -1,
314d7389
MH		 637 .num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
638 .resource = dm644x_vpfe_resources,
ab8e8df8 639 .dev = {
af946f26
MH		 640 .dma_mask = &dm644x_video_dma_mask,
641 .coherent_dma_mask = DMA_BIT_MASK(32),
642 },
643};
644
645#define DM644X_OSD_BASE 0x01c72600
646
647static struct resource dm644x_osd_resources[] = {
648 {
649 .start = DM644X_OSD_BASE,
650 .end = DM644X_OSD_BASE + 0x1ff,
651 .flags = IORESOURCE_MEM,
652 },
653};
654
af946f26 655static struct platform_device dm644x_osd_dev = {
caff80c3 656 .name = DM644X_VPBE_OSD_SUBDEV_NAME,
af946f26
MH		 657 .id = -1,
658 .num_resources = ARRAY_SIZE(dm644x_osd_resources),
659 .resource = dm644x_osd_resources,
660 .dev = {
661 .dma_mask = &dm644x_video_dma_mask,
662 .coherent_dma_mask = DMA_BIT_MASK(32),
af946f26
MH		 663 },
664};
665
666#define DM644X_VENC_BASE 0x01c72400
667
668static struct resource dm644x_venc_resources[] = {
669 {
670 .start = DM644X_VENC_BASE,
671 .end = DM644X_VENC_BASE + 0x17f,
672 .flags = IORESOURCE_MEM,
673 },
674};
675
676#define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
677#define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
678#define DM644X_VPSS_VENCLKEN BIT(3)
679#define DM644X_VPSS_DACCLKEN BIT(4)
680
681static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
36864082 682 unsigned int pclock)
af946f26
MH		 683{
684 int ret = 0;
685 u32 v = DM644X_VPSS_VENCLKEN;
686
687 switch (type) {
688 case VPBE_ENC_STD:
689 v |= DM644X_VPSS_DACCLKEN;
690 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
691 break;
ef2d41b1 692 case VPBE_ENC_DV_TIMINGS:
36864082 693 if (pclock <= 27000000) {
e37212aa 694 v |= DM644X_VPSS_DACCLKEN;
af946f26 695 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
36864082 696 } else {
af946f26
MH		 697 /*
698 * For HD, use external clock source since
699 * HD requires higher clock rate
700 */
701 v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
702 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
af946f26
MH		 703 }
704 break;
705 default:
706 ret = -EINVAL;
707 }
708
709 return ret;
710}
711
712static struct resource dm644x_v4l2_disp_resources[] = {
713 {
714 .start = IRQ_VENCINT,
715 .end = IRQ_VENCINT,
716 .flags = IORESOURCE_IRQ,
717 },
718};
719
720static struct platform_device dm644x_vpbe_display = {
721 .name = "vpbe-v4l2",
722 .id = -1,
723 .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
724 .resource = dm644x_v4l2_disp_resources,
725 .dev = {
726 .dma_mask = &dm644x_video_dma_mask,
727 .coherent_dma_mask = DMA_BIT_MASK(32),
728 },
729};
730
731static struct venc_platform_data dm644x_venc_pdata = {
af946f26
MH		 732 .setup_clock = dm644x_venc_setup_clock,
733};
734
735static struct platform_device dm644x_venc_dev = {
caff80c3 736 .name = DM644X_VPBE_VENC_SUBDEV_NAME,
af946f26
MH		 737 .id = -1,
738 .num_resources = ARRAY_SIZE(dm644x_venc_resources),
739 .resource = dm644x_venc_resources,
740 .dev = {
741 .dma_mask = &dm644x_video_dma_mask,
742 .coherent_dma_mask = DMA_BIT_MASK(32),
743 .platform_data = &dm644x_venc_pdata,
744 },
745};
746
747static struct platform_device dm644x_vpbe_dev = {
748 .name = "vpbe_controller",
749 .id = -1,
750 .dev = {
751 .dma_mask = &dm644x_video_dma_mask,
ab8e8df8
MK		 752 .coherent_dma_mask = DMA_BIT_MASK(32),
753 },
754};
755
9cc1515c
PA		 756static struct resource dm644_gpio_resources[] = {
757 { /* registers */
758 .start = DAVINCI_GPIO_BASE,
759 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
760 .flags = IORESOURCE_MEM,
761 },
762 { /* interrupt */
763 .start = IRQ_GPIOBNK0,
764 .end = IRQ_GPIOBNK4,
765 .flags = IORESOURCE_IRQ,
766 },
767};
768
769static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
770 .ngpio = 71,
9cc1515c
PA		 771};
772
773int __init dm644x_gpio_register(void)
774{
775 return davinci_gpio_register(dm644_gpio_resources,
e462f1f5 776 ARRAY_SIZE(dm644_gpio_resources),
9cc1515c
PA		 777 &dm644_gpio_platform_data);
778}
d0e47fba 779/*----------------------------------------------------------------------*/
ac7b75b5 780
79c3c0b7
MG		 781static struct map_desc dm644x_io_desc[] = {
782 {
783 .virtual = IO_VIRT,
784 .pfn = __phys_to_pfn(IO_PHYS),
785 .length = IO_SIZE,
786 .type = MT_DEVICE
787 },
788};
789
b9ab1279
MG		 790/* Contents of JTAG ID register used to identify exact cpu type */
791static struct davinci_id dm644x_ids[] = {
792 {
793 .variant = 0x0,
794 .part_no = 0xb700,
795 .manufacturer = 0x017,
796 .cpu_id = DAVINCI_CPU_ID_DM6446,
797 .name = "dm6446",
798 },
98d0e9fc
RS		 799 {
800 .variant = 0x1,
801 .part_no = 0xb700,
802 .manufacturer = 0x017,
803 .cpu_id = DAVINCI_CPU_ID_DM6446,
804 .name = "dm6446a",
805 },
b9ab1279
MG		 806};
807
e4c822c7 808static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
d81d188c 809
f64691b3
MG		 810/*
811 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
812 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
813 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
814 * T1_TOP: Timer 1, top : <unused>
815 */
28552c2e 816static struct davinci_timer_info dm644x_timer_info = {
f64691b3
MG		 817 .timers = davinci_timer_instance,
818 .clockevent_id = T0_BOT,
819 .clocksource_id = T0_TOP,
820};
821
19955c3d 822static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
65e866a9
MG		 823 {
824 .mapbase = DAVINCI_UART0_BASE,
825 .irq = IRQ_UARTINT0,
826 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
827 UPF_IOREMAP,
828 .iotype = UPIO_MEM,
829 .regshift = 2,
830 },
19955c3d
MP		 831 {
832 .flags = 0,
833 }
834};
835static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
65e866a9
MG		 836 {
837 .mapbase = DAVINCI_UART1_BASE,
838 .irq = IRQ_UARTINT1,
839 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
840 UPF_IOREMAP,
841 .iotype = UPIO_MEM,
842 .regshift = 2,
843 },
19955c3d
MP		 844 {
845 .flags = 0,
846 }
847};
848static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
65e866a9
MG		 849 {
850 .mapbase = DAVINCI_UART2_BASE,
851 .irq = IRQ_UARTINT2,
852 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
853 UPF_IOREMAP,
854 .iotype = UPIO_MEM,
855 .regshift = 2,
856 },
857 {
19955c3d
MP		 858 .flags = 0,
859 }
65e866a9
MG		 860};
861
fcf7157b 862struct platform_device dm644x_serial_device[] = {
19955c3d
MP		 863 {
864 .name = "serial8250",
865 .id = PLAT8250_DEV_PLATFORM,
866 .dev = {
867 .platform_data = dm644x_serial0_platform_data,
868 }
65e866a9 869 },
19955c3d
MP		 870 {
871 .name = "serial8250",
872 .id = PLAT8250_DEV_PLATFORM1,
873 .dev = {
874 .platform_data = dm644x_serial1_platform_data,
875 }
876 },
877 {
878 .name = "serial8250",
879 .id = PLAT8250_DEV_PLATFORM2,
880 .dev = {
881 .platform_data = dm644x_serial2_platform_data,
882 }
883 },
884 {
885 }
65e866a9
MG		 886};
887
79c3c0b7
MG		 888static struct davinci_soc_info davinci_soc_info_dm644x = {
889 .io_desc = dm644x_io_desc,
890 .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
3347db83 891 .jtag_id_reg = 0x01c40028,
b9ab1279
MG		 892 .ids = dm644x_ids,
893 .ids_num = ARRAY_SIZE(dm644x_ids),
66e0c399 894 .cpu_clks = dm644x_clks,
d81d188c
MG		 895 .psc_bases = dm644x_psc_bases,
896 .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
779b0d53 897 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
0e585952
MG		 898 .pinmux_pins = dm644x_pins,
899 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
bd808947 900 .intc_base = DAVINCI_ARM_INTC_BASE,
673dd36f
MG		 901 .intc_type = DAVINCI_INTC_TYPE_AINTC,
902 .intc_irq_prios = dm644x_default_priorities,
903 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3 904 .timer_info = &dm644x_timer_info,
972412b6 905 .emac_pdata = &dm644x_emac_pdata,
0d04eb47
DB		 906 .sram_dma = 0x00008000,
907 .sram_len = SZ_16K,
79c3c0b7
MG		 908};
909
25acf553
C		 910void __init dm644x_init_asp(struct snd_platform_data *pdata)
911{
912 davinci_cfg_reg(DM644X_MCBSP);
913 dm644x_asp_device.dev.platform_data = pdata;
914 platform_device_register(&dm644x_asp_device);
915}
916
d0e47fba
KH		 917void __init dm644x_init(void)
918{
79c3c0b7 919 davinci_common_init(&davinci_soc_info_dm644x);
5cfb19ac 920 davinci_map_sysmod();
d0e47fba
KH		 921}
922
af946f26
MH		 923int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
924 struct vpbe_config *vpbe_cfg)
d0e47fba 925{
af946f26
MH		 926 if (vpfe_cfg || vpbe_cfg)
927 platform_device_register(&dm644x_vpss_device);
928
929 if (vpfe_cfg) {
930 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
931 platform_device_register(&dm644x_ccdc_dev);
932 platform_device_register(&dm644x_vpfe_dev);
af946f26
MH		 933 }
934
935 if (vpbe_cfg) {
936 dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
937 platform_device_register(&dm644x_osd_dev);
938 platform_device_register(&dm644x_venc_dev);
939 platform_device_register(&dm644x_vpbe_dev);
940 platform_device_register(&dm644x_vpbe_display);
941 }
12db9588
MH		 942
943 return 0;
944}
945
946static int __init dm644x_init_devices(void)
947{
1233090c
SN		 948 int ret = 0;
949
12db9588
MH		 950 if (!cpu_is_davinci_dm644x())
951 return 0;
952
d0e47fba 953 platform_device_register(&dm644x_edma_device);
d22960c8
CC		 954
955 platform_device_register(&dm644x_mdio_device);
972412b6 956 platform_device_register(&dm644x_emac_device);
d22960c8 957
1233090c
SN		 958 ret = davinci_init_wdt();
959 if (ret)
960 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
961
962 return ret;
d0e47fba
KH		 963}
964postcore_initcall(dm644x_init_devices);
Linux kernel - Deliverables
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