Commit | Line | Data |
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7c6337e2 KH |
1 | /* |
2 | * Header for code common to all DaVinci machines. | |
3 | * | |
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
5 | * | |
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | */ | |
11 | ||
12 | #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H | |
13 | #define __ARCH_ARM_MACH_DAVINCI_COMMON_H | |
14 | ||
280faffb TK |
15 | #include <linux/compiler.h> |
16 | #include <linux/types.h> | |
7b6d864b | 17 | #include <linux/reboot.h> |
280faffb | 18 | |
6bb27d73 | 19 | extern void davinci_timer_init(void); |
7c6337e2 | 20 | |
d0e47fba | 21 | extern void davinci_irq_init(void); |
673dd36f | 22 | extern void __iomem *davinci_intc_base; |
0b0c4c2a | 23 | extern int davinci_intc_type; |
d0e47fba | 24 | |
f64691b3 | 25 | struct davinci_timer_instance { |
1bcd38ad | 26 | u32 base; |
f64691b3 MG |
27 | u32 bottom_irq; |
28 | u32 top_irq; | |
3abd5acf MG |
29 | unsigned long cmp_off; |
30 | unsigned int cmp_irq; | |
f64691b3 MG |
31 | }; |
32 | ||
33 | struct davinci_timer_info { | |
34 | struct davinci_timer_instance *timers; | |
35 | unsigned int clockevent_id; | |
36 | unsigned int clocksource_id; | |
37 | }; | |
38 | ||
c12f415a CC |
39 | struct davinci_gpio_controller; |
40 | ||
bcd6a1c6 CC |
41 | /* |
42 | * SoC info passed into common davinci modules. | |
43 | * | |
44 | * Base addresses in this structure should be physical and not virtual. | |
45 | * Modules that take such base addresses, should internally ioremap() them to | |
46 | * use. | |
47 | */ | |
79c3c0b7 MG |
48 | struct davinci_soc_info { |
49 | struct map_desc *io_desc; | |
50 | unsigned long io_desc_num; | |
b9ab1279 MG |
51 | u32 cpu_id; |
52 | u32 jtag_id; | |
3347db83 | 53 | u32 jtag_id_reg; |
b9ab1279 MG |
54 | struct davinci_id *ids; |
55 | unsigned long ids_num; | |
08aca087 | 56 | struct clk_lookup *cpu_clks; |
e4c822c7 | 57 | u32 *psc_bases; |
d81d188c | 58 | unsigned long psc_bases_num; |
779b0d53 | 59 | u32 pinmux_base; |
0e585952 MG |
60 | const struct mux_config *pinmux_pins; |
61 | unsigned long pinmux_pins_num; | |
bd808947 | 62 | u32 intc_base; |
673dd36f MG |
63 | int intc_type; |
64 | u8 *intc_irq_prios; | |
65 | unsigned long intc_irq_num; | |
bd808947 | 66 | u32 *intc_host_map; |
f64691b3 | 67 | struct davinci_timer_info *timer_info; |
686b634a | 68 | int gpio_type; |
b8d44293 | 69 | u32 gpio_base; |
a994955c MG |
70 | unsigned gpio_num; |
71 | unsigned gpio_irq; | |
7a36071e | 72 | unsigned gpio_unbanked; |
c12f415a CC |
73 | struct davinci_gpio_controller *gpio_ctlrs; |
74 | int gpio_ctlrs_num; | |
65e866a9 | 75 | struct platform_device *serial_dev; |
972412b6 | 76 | struct emac_platform_data *emac_pdata; |
0d04eb47 DB |
77 | dma_addr_t sram_dma; |
78 | unsigned sram_len; | |
79c3c0b7 MG |
79 | }; |
80 | ||
81 | extern struct davinci_soc_info davinci_soc_info; | |
82 | ||
83 | extern void davinci_common_init(struct davinci_soc_info *soc_info); | |
7a9978a1 | 84 | extern void davinci_init_ide(void); |
7b6d864b | 85 | void davinci_restart(enum reboot_mode mode, const char *cmd); |
3aa3e840 SG |
86 | void davinci_init_late(void); |
87 | ||
88 | #ifdef CONFIG_DAVINCI_RESET_CLOCKS | |
89 | int davinci_clk_disable_unused(void); | |
90 | #else | |
91 | static inline int davinci_clk_disable_unused(void) { return 0; } | |
92 | #endif | |
93 | ||
94 | #ifdef CONFIG_CPU_FREQ | |
95 | int davinci_cpufreq_init(void); | |
96 | #else | |
97 | static inline int davinci_cpufreq_init(void) { return 0; } | |
98 | #endif | |
99 | ||
100 | #ifdef CONFIG_SUSPEND | |
101 | int davinci_pm_init(void); | |
102 | #else | |
103 | static inline int davinci_pm_init(void) { return 0; } | |
104 | #endif | |
79c3c0b7 | 105 | |
0d04eb47 DB |
106 | #define SRAM_SIZE SZ_128K |
107 | ||
7c6337e2 | 108 | #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ |