[deliverable/linux.git] / arch / arm / mach-dove / pcie.c

/*
 * arch/arm/mach-dove/pcie.c
 *
 * PCIe functions for Marvell Dove 88AP510 SoC
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/clk.h>
#include <video/vga.h>
#include <asm/mach/pci.h>
#include <asm/mach/arch.h>
#include <asm/setup.h>
#include <asm/delay.h>
#include <plat/pcie.h>
#include <mach/irqs.h>
#include <mach/bridge-regs.h>
#include <plat/addr-map.h>
#include "common.h"

struct pcie_port {
	u8			index;
	u8			root_bus_nr;
	void __iomem		*base;
	spinlock_t		conf_lock;
	char			mem_space_name[16];
	struct resource		res;
};

static struct pcie_port pcie_port[2];
static int num_pcie_ports;


static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
{
	struct pcie_port *pp;

	if (nr >= num_pcie_ports)
		return 0;

	pp = &pcie_port[nr];
	sys->private_data = pp;
	pp->root_bus_nr = sys->busnr;

	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);

	orion_pcie_setup(pp->base);

	if (pp->index == 0)
		pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
	else
		pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);

	/*
	 * IORESOURCE_MEM
	 */
	snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
		 "PCIe %d MEM", pp->index);
	pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
	pp->res.name = pp->mem_space_name;
	if (pp->index == 0) {
		pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
		pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
	} else {
		pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
		pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
	}
	pp->res.flags = IORESOURCE_MEM;
	if (request_resource(&iomem_resource, &pp->res))
		panic("Request PCIe Memory resource failed\n");
	pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);

	return 1;
}

static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
{
	/*
	 * Don't go out when trying to access nonexisting devices
	 * on the local bus.
	 */
	if (bus == pp->root_bus_nr && dev > 1)
		return 0;

	return 1;
}

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
	struct pci_sys_data *sys = bus->sysdata;
	struct pcie_port *pp = sys->private_data;
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
	struct pci_sys_data *sys = bus->sysdata;
	struct pcie_port *pp = sys->private_data;
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};

static void rc_pci_fixup(struct pci_dev *dev)
{
	/*
	 * Prevent enumeration of root complex.
	 */
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

static struct pci_bus __init *
dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
{
	if (nr >= num_pcie_ports) {
		BUG();
		return NULL;
	}

	return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
				 &sys->resources);
}

static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	struct pci_sys_data *sys = dev->sysdata;
	struct pcie_port *pp = sys->private_data;

	return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
}

static struct hw_pci dove_pci __initdata = {
	.nr_controllers	= 2,
	.setup		= dove_pcie_setup,
	.scan		= dove_pcie_scan_bus,
	.map_irq	= dove_pcie_map_irq,
};

static void __init add_pcie_port(int index, void __iomem *base)
{
	printk(KERN_INFO "Dove PCIe port %d: ", index);

	if (orion_pcie_link_up(base)) {
		struct pcie_port *pp = &pcie_port[num_pcie_ports++];
		struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));

		if (!IS_ERR(clk))
			clk_prepare_enable(clk);

		printk(KERN_INFO "link up\n");

		pp->index = index;
		pp->root_bus_nr = -1;
		pp->base = base;
		spin_lock_init(&pp->conf_lock);
		memset(&pp->res, 0, sizeof(pp->res));
	} else {
		printk(KERN_INFO "link down, ignoring\n");
	}
}

void __init dove_pcie_init(int init_port0, int init_port1)
{
	vga_base = DOVE_PCIE0_MEM_PHYS_BASE;

	if (init_port0)
		add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);

	if (init_port1)
		add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);

	pci_common_init(&dove_pci);
}
Commit	Line	Data
edabd38e SB	1	/*
	2	* arch/arm/mach-dove/pcie.c
	3	*
	4	* PCIe functions for Marvell Dove 88AP510 SoC
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/pci.h>
529b89ef	13	#include <linux/clk.h>
cc22b4c1	14	#include <video/vga.h>
edabd38e SB	15	#include <asm/mach/pci.h>
	16	#include <asm/mach/arch.h>
	17	#include <asm/setup.h>
	18	#include <asm/delay.h>
	19	#include <plat/pcie.h>
	20	#include <mach/irqs.h>
	21	#include <mach/bridge-regs.h>
45173d5e	22	#include <plat/addr-map.h>
edabd38e SB	23	#include "common.h"
	24
	25	struct pcie_port {
	26	u8 index;
	27	u8 root_bus_nr;
	28	void __iomem *base;
	29	spinlock_t conf_lock;
edabd38e	30	char mem_space_name[16];
d191bb69	31	struct resource res;
edabd38e SB	32	};
	33
	34	static struct pcie_port pcie_port[2];
	35	static int num_pcie_ports;
	36
	37
	38	static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
	39	{
	40	struct pcie_port *pp;
	41
	42	if (nr >= num_pcie_ports)
	43	return 0;
	44
	45	pp = &pcie_port[nr];
43ba990b	46	sys->private_data = pp;
edabd38e SB	47	pp->root_bus_nr = sys->busnr;
	48
	49	/*
	50	* Generic PCIe unit setup.
	51	*/
	52	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
	53
63a9332b	54	orion_pcie_setup(pp->base);
edabd38e	55
d191bb69 RH	56	if (pp->index == 0)
	57	pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
	58	else
	59	pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
edabd38e SB	60
	61	/*
	62	* IORESOURCE_MEM
	63	*/
	64	snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
	65	"PCIe %d MEM", pp->index);
	66	pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
d191bb69	67	pp->res.name = pp->mem_space_name;
edabd38e	68	if (pp->index == 0) {
d191bb69 RH	69	pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
d191bb69 RH	70	pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
edabd38e	71	} else {
d191bb69 RH	72	pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
d191bb69 RH	73	pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
edabd38e	74	}
d191bb69 RH	75	pp->res.flags = IORESOURCE_MEM;
d191bb69 RH	76	if (request_resource(&iomem_resource, &pp->res))
edabd38e	77	panic("Request PCIe Memory resource failed\n");
d191bb69	78	pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
edabd38e SB	79
	80	return 1;
	81	}
	82
edabd38e SB	83	static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
	84	{
	85	/*
	86	* Don't go out when trying to access nonexisting devices
	87	* on the local bus.
	88	*/
	89	if (bus == pp->root_bus_nr && dev > 1)
	90	return 0;
	91
	92	return 1;
	93	}
	94
	95	static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
	96	int size, u32 *val)
	97	{
43ba990b RK	98	struct pci_sys_data *sys = bus->sysdata;
43ba990b RK	99	struct pcie_port *pp = sys->private_data;
edabd38e SB	100	unsigned long flags;
	101	int ret;
	102
	103	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
	104	*val = 0xffffffff;
	105	return PCIBIOS_DEVICE_NOT_FOUND;
	106	}
	107
	108	spin_lock_irqsave(&pp->conf_lock, flags);
	109	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
	110	spin_unlock_irqrestore(&pp->conf_lock, flags);
	111
	112	return ret;
	113	}
	114
	115	static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
	116	int where, int size, u32 val)
	117	{
43ba990b RK	118	struct pci_sys_data *sys = bus->sysdata;
43ba990b RK	119	struct pcie_port *pp = sys->private_data;
edabd38e SB	120	unsigned long flags;
	121	int ret;
	122
	123	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
	124	return PCIBIOS_DEVICE_NOT_FOUND;
	125
	126	spin_lock_irqsave(&pp->conf_lock, flags);
	127	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
	128	spin_unlock_irqrestore(&pp->conf_lock, flags);
	129
	130	return ret;
	131	}
	132
	133	static struct pci_ops pcie_ops = {
	134	.read = pcie_rd_conf,
	135	.write = pcie_wr_conf,
	136	};
	137
351a102d	138	static void rc_pci_fixup(struct pci_dev *dev)
edabd38e SB	139	{
	140	/*
	141	* Prevent enumeration of root complex.
	142	*/
	143	if (dev->bus->parent == NULL && dev->devfn == 0) {
	144	int i;
	145
	146	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
	147	dev->resource[i].start = 0;
	148	dev->resource[i].end = 0;
	149	dev->resource[i].flags = 0;
	150	}
	151	}
	152	}
	153	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
	154
	155	static struct pci_bus __init *
	156	dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
	157	{
9e808eb6	158	if (nr >= num_pcie_ports) {
edabd38e	159	BUG();
9e808eb6	160	return NULL;
edabd38e SB	161	}
edabd38e SB	162
9e808eb6 BH	163	return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
9e808eb6 BH	164	&sys->resources);
edabd38e SB	165	}
edabd38e SB	166
d5341942	167	static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
edabd38e	168	{
43ba990b RK	169	struct pci_sys_data *sys = dev->sysdata;
43ba990b RK	170	struct pcie_port *pp = sys->private_data;
edabd38e SB	171
	172	return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
	173	}
	174
	175	static struct hw_pci dove_pci __initdata = {
	176	.nr_controllers = 2,
edabd38e SB	177	.setup = dove_pcie_setup,
	178	.scan = dove_pcie_scan_bus,
	179	.map_irq = dove_pcie_map_irq,
	180	};
	181
c3c5a281	182	static void __init add_pcie_port(int index, void __iomem *base)
edabd38e SB	183	{
	184	printk(KERN_INFO "Dove PCIe port %d: ", index);
	185
c3c5a281	186	if (orion_pcie_link_up(base)) {
edabd38e	187	struct pcie_port *pp = &pcie_port[num_pcie_ports++];
529b89ef SH	188	struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
	189
	190	if (!IS_ERR(clk))
	191	clk_prepare_enable(clk);
edabd38e SB	192
	193	printk(KERN_INFO "link up\n");
	194
	195	pp->index = index;
	196	pp->root_bus_nr = -1;
c3c5a281	197	pp->base = base;
edabd38e	198	spin_lock_init(&pp->conf_lock);
d191bb69	199	memset(&pp->res, 0, sizeof(pp->res));
edabd38e SB	200	} else {
	201	printk(KERN_INFO "link down, ignoring\n");
	202	}
	203	}
	204
	205	void __init dove_pcie_init(int init_port0, int init_port1)
	206	{
cc22b4c1 RH	207	vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
cc22b4c1 RH	208
edabd38e SB	209	if (init_port0)
	210	add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
	211
	212	if (init_port1)
	213	add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
	214
	215	pci_common_init(&dove_pci);
	216	}