Commit | Line | Data |
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e7736d47 LB |
1 | /* |
2 | * arch/arm/mach-ep93xx/core.c | |
3 | * Core routines for Cirrus EP93xx chips. | |
4 | * | |
5 | * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> | |
3c9a071d | 6 | * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> |
e7736d47 LB |
7 | * |
8 | * Thanks go to Michael Burian and Ray Lehtiniemi for their key | |
9 | * role in the ep93xx linux community. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | */ | |
16 | ||
64d6882d HS |
17 | #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt |
18 | ||
e7736d47 LB |
19 | #include <linux/kernel.h> |
20 | #include <linux/init.h> | |
583ddafe | 21 | #include <linux/platform_device.h> |
e7736d47 | 22 | #include <linux/interrupt.h> |
63890a0e | 23 | #include <linux/dma-mapping.h> |
e7736d47 | 24 | #include <linux/timex.h> |
6bd4b382 | 25 | #include <linux/irq.h> |
583ddafe HS |
26 | #include <linux/io.h> |
27 | #include <linux/gpio.h> | |
3aa7a9a3 | 28 | #include <linux/leds.h> |
aee85fe8 | 29 | #include <linux/termios.h> |
e7736d47 | 30 | #include <linux/amba/bus.h> |
aee85fe8 | 31 | #include <linux/amba/serial.h> |
16bcf78f | 32 | #include <linux/mtd/physmap.h> |
d52a26a9 HS |
33 | #include <linux/i2c.h> |
34 | #include <linux/i2c-gpio.h> | |
4fec9978 | 35 | #include <linux/spi/spi.h> |
dc28094b | 36 | #include <linux/export.h> |
e7736d47 | 37 | |
a09e64fb | 38 | #include <mach/hardware.h> |
c6012189 | 39 | #include <mach/fb.h> |
12f56c68 | 40 | #include <mach/ep93xx_keypad.h> |
4fec9978 | 41 | #include <mach/ep93xx_spi.h> |
bd5f12a2 | 42 | #include <mach/gpio-ep93xx.h> |
e7736d47 LB |
43 | |
44 | #include <asm/mach/map.h> | |
45 | #include <asm/mach/time.h> | |
e7736d47 LB |
46 | |
47 | #include <asm/hardware/vic.h> | |
48 | ||
49 | ||
50 | /************************************************************************* | |
51 | * Static I/O mappings that are needed for all EP93xx platforms | |
52 | *************************************************************************/ | |
53 | static struct map_desc ep93xx_io_desc[] __initdata = { | |
54 | { | |
55 | .virtual = EP93XX_AHB_VIRT_BASE, | |
56 | .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE), | |
57 | .length = EP93XX_AHB_SIZE, | |
58 | .type = MT_DEVICE, | |
59 | }, { | |
60 | .virtual = EP93XX_APB_VIRT_BASE, | |
61 | .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE), | |
62 | .length = EP93XX_APB_SIZE, | |
63 | .type = MT_DEVICE, | |
64 | }, | |
65 | }; | |
66 | ||
67 | void __init ep93xx_map_io(void) | |
68 | { | |
69 | iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc)); | |
70 | } | |
71 | ||
72 | ||
73 | /************************************************************************* | |
74 | * Timer handling for EP93xx | |
75 | ************************************************************************* | |
76 | * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and | |
77 | * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate | |
78 | * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, | |
79 | * is free-running, and can't generate interrupts. | |
80 | * | |
81 | * The 508 kHz timers are ideal for use for the timer interrupt, as the | |
82 | * most common values of HZ divide 508 kHz nicely. We pick one of the 16 | |
83 | * bit timers (timer 1) since we don't need more than 16 bits of reload | |
84 | * value as long as HZ >= 8. | |
85 | * | |
86 | * The higher clock rate of timer 4 makes it a better choice than the | |
87 | * other timers for use in gettimeoffset(), while the fact that it can't | |
88 | * generate interrupts means we don't have to worry about not being able | |
89 | * to use this timer for something else. We also use timer 4 for keeping | |
90 | * track of lost jiffies. | |
91 | */ | |
1587a373 HS |
92 | #define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) |
93 | #define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) | |
94 | #define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) | |
95 | #define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) | |
96 | #define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7) | |
97 | #define EP93XX_TIMER123_CONTROL_MODE (1 << 6) | |
98 | #define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3) | |
99 | #define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) | |
100 | #define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) | |
101 | #define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) | |
102 | #define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) | |
103 | #define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) | |
104 | #define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) | |
105 | #define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) | |
106 | #define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8) | |
107 | #define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) | |
108 | #define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) | |
109 | #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) | |
110 | #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) | |
111 | ||
112 | #define EP93XX_TIMER123_CLOCK 508469 | |
113 | #define EP93XX_TIMER4_CLOCK 983040 | |
114 | ||
115 | #define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1) | |
af1057ab | 116 | #define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ) |
e7736d47 | 117 | |
1587a373 HS |
118 | static unsigned int last_jiffy_time; |
119 | ||
d5565f76 | 120 | static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) |
e7736d47 | 121 | { |
1587a373 | 122 | /* Writing any value clears the timer interrupt */ |
e7736d47 | 123 | __raw_writel(1, EP93XX_TIMER1_CLEAR); |
1587a373 HS |
124 | |
125 | /* Recover lost jiffies */ | |
f869afab LB |
126 | while ((signed long) |
127 | (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time) | |
e7736d47 LB |
128 | >= TIMER4_TICKS_PER_JIFFY) { |
129 | last_jiffy_time += TIMER4_TICKS_PER_JIFFY; | |
0cd61b68 | 130 | timer_tick(); |
e7736d47 LB |
131 | } |
132 | ||
e7736d47 LB |
133 | return IRQ_HANDLED; |
134 | } | |
135 | ||
136 | static struct irqaction ep93xx_timer_irq = { | |
137 | .name = "ep93xx timer", | |
b30fabad | 138 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
e7736d47 LB |
139 | .handler = ep93xx_timer_interrupt, |
140 | }; | |
141 | ||
142 | static void __init ep93xx_timer_init(void) | |
143 | { | |
1587a373 HS |
144 | u32 tmode = EP93XX_TIMER123_CONTROL_MODE | |
145 | EP93XX_TIMER123_CONTROL_CLKSEL; | |
146 | ||
e7736d47 | 147 | /* Enable periodic HZ timer. */ |
1587a373 HS |
148 | __raw_writel(tmode, EP93XX_TIMER1_CONTROL); |
149 | __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD); | |
150 | __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, | |
151 | EP93XX_TIMER1_CONTROL); | |
e7736d47 LB |
152 | |
153 | /* Enable lost jiffy timer. */ | |
1587a373 HS |
154 | __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, |
155 | EP93XX_TIMER4_VALUE_HIGH); | |
e7736d47 LB |
156 | |
157 | setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq); | |
158 | } | |
159 | ||
160 | static unsigned long ep93xx_gettimeoffset(void) | |
161 | { | |
162 | int offset; | |
163 | ||
164 | offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time; | |
165 | ||
166 | /* Calculate (1000000 / 983040) * offset. */ | |
167 | return offset + (53 * offset / 3072); | |
168 | } | |
169 | ||
170 | struct sys_timer ep93xx_timer = { | |
171 | .init = ep93xx_timer_init, | |
172 | .offset = ep93xx_gettimeoffset, | |
173 | }; | |
174 | ||
175 | ||
176 | /************************************************************************* | |
177 | * EP93xx IRQ handling | |
178 | *************************************************************************/ | |
179 | void __init ep93xx_init_irq(void) | |
180 | { | |
5396730b HS |
181 | vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); |
182 | vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); | |
e7736d47 LB |
183 | } |
184 | ||
185 | ||
02239f0a HS |
186 | /************************************************************************* |
187 | * EP93xx System Controller Software Locked register handling | |
188 | *************************************************************************/ | |
189 | ||
190 | /* | |
191 | * syscon_swlock prevents anything else from writing to the syscon | |
192 | * block while a software locked register is being written. | |
193 | */ | |
194 | static DEFINE_SPINLOCK(syscon_swlock); | |
195 | ||
fbeeea53 | 196 | void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg) |
02239f0a HS |
197 | { |
198 | unsigned long flags; | |
199 | ||
200 | spin_lock_irqsave(&syscon_swlock, flags); | |
201 | ||
202 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | |
203 | __raw_writel(val, reg); | |
204 | ||
205 | spin_unlock_irqrestore(&syscon_swlock, flags); | |
206 | } | |
207 | EXPORT_SYMBOL(ep93xx_syscon_swlocked_write); | |
208 | ||
209 | void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits) | |
210 | { | |
211 | unsigned long flags; | |
212 | unsigned int val; | |
213 | ||
214 | spin_lock_irqsave(&syscon_swlock, flags); | |
215 | ||
216 | val = __raw_readl(EP93XX_SYSCON_DEVCFG); | |
02239f0a | 217 | val &= ~clear_bits; |
a0fb007b | 218 | val |= set_bits; |
02239f0a HS |
219 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); |
220 | __raw_writel(val, EP93XX_SYSCON_DEVCFG); | |
221 | ||
222 | spin_unlock_irqrestore(&syscon_swlock, flags); | |
223 | } | |
224 | EXPORT_SYMBOL(ep93xx_devcfg_set_clear); | |
225 | ||
99e6a23a MW |
226 | /** |
227 | * ep93xx_chip_revision() - returns the EP93xx chip revision | |
228 | * | |
229 | * See <mach/platform.h> for more information. | |
230 | */ | |
231 | unsigned int ep93xx_chip_revision(void) | |
232 | { | |
233 | unsigned int v; | |
234 | ||
235 | v = __raw_readl(EP93XX_SYSCON_SYSCFG); | |
236 | v &= EP93XX_SYSCON_SYSCFG_REV_MASK; | |
237 | v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT; | |
238 | return v; | |
239 | } | |
02239f0a | 240 | |
1e4c8842 HS |
241 | /************************************************************************* |
242 | * EP93xx GPIO | |
243 | *************************************************************************/ | |
244 | static struct resource ep93xx_gpio_resource[] = { | |
245 | { | |
246 | .start = EP93XX_GPIO_PHYS_BASE, | |
247 | .end = EP93XX_GPIO_PHYS_BASE + 0xcc - 1, | |
248 | .flags = IORESOURCE_MEM, | |
249 | }, | |
250 | }; | |
251 | ||
252 | static struct platform_device ep93xx_gpio_device = { | |
253 | .name = "gpio-ep93xx", | |
254 | .id = -1, | |
255 | .num_resources = ARRAY_SIZE(ep93xx_gpio_resource), | |
256 | .resource = ep93xx_gpio_resource, | |
257 | }; | |
258 | ||
e7736d47 LB |
259 | /************************************************************************* |
260 | * EP93xx peripheral handling | |
261 | *************************************************************************/ | |
aee85fe8 LB |
262 | #define EP93XX_UART_MCR_OFFSET (0x0100) |
263 | ||
264 | static void ep93xx_uart_set_mctrl(struct amba_device *dev, | |
265 | void __iomem *base, unsigned int mctrl) | |
266 | { | |
267 | unsigned int mcr; | |
268 | ||
269 | mcr = 0; | |
186dcaa4 | 270 | if (mctrl & TIOCM_RTS) |
aee85fe8 | 271 | mcr |= 2; |
186dcaa4 | 272 | if (mctrl & TIOCM_DTR) |
aee85fe8 LB |
273 | mcr |= 1; |
274 | ||
275 | __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); | |
276 | } | |
277 | ||
278 | static struct amba_pl010_data ep93xx_uart_data = { | |
279 | .set_mctrl = ep93xx_uart_set_mctrl, | |
280 | }; | |
281 | ||
282 | static struct amba_device uart1_device = { | |
283 | .dev = { | |
1d559e29 | 284 | .init_name = "apb:uart1", |
aee85fe8 LB |
285 | .platform_data = &ep93xx_uart_data, |
286 | }, | |
287 | .res = { | |
288 | .start = EP93XX_UART1_PHYS_BASE, | |
289 | .end = EP93XX_UART1_PHYS_BASE + 0x0fff, | |
290 | .flags = IORESOURCE_MEM, | |
291 | }, | |
292 | .irq = { IRQ_EP93XX_UART1, NO_IRQ }, | |
293 | .periphid = 0x00041010, | |
294 | }; | |
295 | ||
296 | static struct amba_device uart2_device = { | |
297 | .dev = { | |
1d559e29 | 298 | .init_name = "apb:uart2", |
aee85fe8 LB |
299 | .platform_data = &ep93xx_uart_data, |
300 | }, | |
301 | .res = { | |
302 | .start = EP93XX_UART2_PHYS_BASE, | |
303 | .end = EP93XX_UART2_PHYS_BASE + 0x0fff, | |
304 | .flags = IORESOURCE_MEM, | |
305 | }, | |
306 | .irq = { IRQ_EP93XX_UART2, NO_IRQ }, | |
307 | .periphid = 0x00041010, | |
308 | }; | |
309 | ||
310 | static struct amba_device uart3_device = { | |
311 | .dev = { | |
1d559e29 | 312 | .init_name = "apb:uart3", |
aee85fe8 LB |
313 | .platform_data = &ep93xx_uart_data, |
314 | }, | |
315 | .res = { | |
316 | .start = EP93XX_UART3_PHYS_BASE, | |
317 | .end = EP93XX_UART3_PHYS_BASE + 0x0fff, | |
318 | .flags = IORESOURCE_MEM, | |
319 | }, | |
320 | .irq = { IRQ_EP93XX_UART3, NO_IRQ }, | |
321 | .periphid = 0x00041010, | |
322 | }; | |
323 | ||
41658132 | 324 | |
38f7b009 HS |
325 | static struct resource ep93xx_rtc_resource[] = { |
326 | { | |
327 | .start = EP93XX_RTC_PHYS_BASE, | |
328 | .end = EP93XX_RTC_PHYS_BASE + 0x10c - 1, | |
329 | .flags = IORESOURCE_MEM, | |
330 | }, | |
331 | }; | |
332 | ||
41658132 | 333 | static struct platform_device ep93xx_rtc_device = { |
38f7b009 HS |
334 | .name = "ep93xx-rtc", |
335 | .id = -1, | |
336 | .num_resources = ARRAY_SIZE(ep93xx_rtc_resource), | |
337 | .resource = ep93xx_rtc_resource, | |
41658132 LB |
338 | }; |
339 | ||
340 | ||
1f64eb37 LB |
341 | static struct resource ep93xx_ohci_resources[] = { |
342 | [0] = { | |
343 | .start = EP93XX_USB_PHYS_BASE, | |
344 | .end = EP93XX_USB_PHYS_BASE + 0x0fff, | |
345 | .flags = IORESOURCE_MEM, | |
346 | }, | |
347 | [1] = { | |
348 | .start = IRQ_EP93XX_USB, | |
349 | .end = IRQ_EP93XX_USB, | |
350 | .flags = IORESOURCE_IRQ, | |
351 | }, | |
352 | }; | |
353 | ||
63890a0e | 354 | |
1f64eb37 LB |
355 | static struct platform_device ep93xx_ohci_device = { |
356 | .name = "ep93xx-ohci", | |
357 | .id = -1, | |
358 | .dev = { | |
63890a0e MK |
359 | .dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask, |
360 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1f64eb37 LB |
361 | }, |
362 | .num_resources = ARRAY_SIZE(ep93xx_ohci_resources), | |
363 | .resource = ep93xx_ohci_resources, | |
364 | }; | |
365 | ||
b370e082 | 366 | |
16bcf78f HS |
367 | /************************************************************************* |
368 | * EP93xx physmap'ed flash | |
369 | *************************************************************************/ | |
370 | static struct physmap_flash_data ep93xx_flash_data; | |
371 | ||
372 | static struct resource ep93xx_flash_resource = { | |
373 | .flags = IORESOURCE_MEM, | |
374 | }; | |
375 | ||
376 | static struct platform_device ep93xx_flash = { | |
377 | .name = "physmap-flash", | |
378 | .id = 0, | |
379 | .dev = { | |
380 | .platform_data = &ep93xx_flash_data, | |
381 | }, | |
382 | .num_resources = 1, | |
383 | .resource = &ep93xx_flash_resource, | |
384 | }; | |
385 | ||
386 | /** | |
387 | * ep93xx_register_flash() - Register the external flash device. | |
388 | * @width: bank width in octets | |
389 | * @start: resource start address | |
390 | * @size: resource size | |
391 | */ | |
392 | void __init ep93xx_register_flash(unsigned int width, | |
393 | resource_size_t start, resource_size_t size) | |
394 | { | |
395 | ep93xx_flash_data.width = width; | |
396 | ||
397 | ep93xx_flash_resource.start = start; | |
398 | ep93xx_flash_resource.end = start + size - 1; | |
399 | ||
400 | platform_device_register(&ep93xx_flash); | |
401 | } | |
402 | ||
403 | ||
b370e082 HS |
404 | /************************************************************************* |
405 | * EP93xx ethernet peripheral handling | |
406 | *************************************************************************/ | |
a0a08fdc HS |
407 | static struct ep93xx_eth_data ep93xx_eth_data; |
408 | ||
409 | static struct resource ep93xx_eth_resource[] = { | |
410 | { | |
411 | .start = EP93XX_ETHERNET_PHYS_BASE, | |
412 | .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff, | |
413 | .flags = IORESOURCE_MEM, | |
414 | }, { | |
415 | .start = IRQ_EP93XX_ETHERNET, | |
416 | .end = IRQ_EP93XX_ETHERNET, | |
417 | .flags = IORESOURCE_IRQ, | |
418 | } | |
419 | }; | |
420 | ||
fa70cf47 MW |
421 | static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32); |
422 | ||
a0a08fdc HS |
423 | static struct platform_device ep93xx_eth_device = { |
424 | .name = "ep93xx-eth", | |
425 | .id = -1, | |
426 | .dev = { | |
fa70cf47 MW |
427 | .platform_data = &ep93xx_eth_data, |
428 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
429 | .dma_mask = &ep93xx_eth_dma_mask, | |
a0a08fdc HS |
430 | }, |
431 | .num_resources = ARRAY_SIZE(ep93xx_eth_resource), | |
432 | .resource = ep93xx_eth_resource, | |
433 | }; | |
434 | ||
b370e082 HS |
435 | /** |
436 | * ep93xx_register_eth - Register the built-in ethernet platform device. | |
437 | * @data: platform specific ethernet configuration (__initdata) | |
438 | * @copy_addr: flag indicating that the MAC address should be copied | |
439 | * from the IndAd registers (as programmed by the bootloader) | |
440 | */ | |
a0a08fdc HS |
441 | void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr) |
442 | { | |
5b1c3c85 HS |
443 | if (copy_addr) |
444 | memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6); | |
a0a08fdc HS |
445 | |
446 | ep93xx_eth_data = *data; | |
447 | platform_device_register(&ep93xx_eth_device); | |
448 | } | |
449 | ||
6531a991 HS |
450 | |
451 | /************************************************************************* | |
452 | * EP93xx i2c peripheral handling | |
453 | *************************************************************************/ | |
454 | static struct i2c_gpio_platform_data ep93xx_i2c_data; | |
d52a26a9 HS |
455 | |
456 | static struct platform_device ep93xx_i2c_device = { | |
b370e082 HS |
457 | .name = "i2c-gpio", |
458 | .id = 0, | |
459 | .dev = { | |
460 | .platform_data = &ep93xx_i2c_data, | |
461 | }, | |
d52a26a9 HS |
462 | }; |
463 | ||
b370e082 HS |
464 | /** |
465 | * ep93xx_register_i2c - Register the i2c platform device. | |
466 | * @data: platform specific i2c-gpio configuration (__initdata) | |
467 | * @devices: platform specific i2c bus device information (__initdata) | |
468 | * @num: the number of devices on the i2c bus | |
469 | */ | |
6531a991 HS |
470 | void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data, |
471 | struct i2c_board_info *devices, int num) | |
d52a26a9 | 472 | { |
6531a991 HS |
473 | /* |
474 | * Set the EEPROM interface pin drive type control. | |
475 | * Defines the driver type for the EECLK and EEDAT pins as either | |
476 | * open drain, which will require an external pull-up, or a normal | |
477 | * CMOS driver. | |
478 | */ | |
479 | if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT) | |
64d6882d | 480 | pr_warning("sda != EEDAT, open drain has no effect\n"); |
6531a991 | 481 | if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK) |
64d6882d | 482 | pr_warning("scl != EECLK, open drain has no effect\n"); |
6531a991 HS |
483 | |
484 | __raw_writel((data->sda_is_open_drain << 1) | | |
485 | (data->scl_is_open_drain << 0), | |
486 | EP93XX_GPIO_EEDRIVE); | |
487 | ||
488 | ep93xx_i2c_data = *data; | |
d52a26a9 HS |
489 | i2c_register_board_info(0, devices, num); |
490 | platform_device_register(&ep93xx_i2c_device); | |
491 | } | |
492 | ||
4fec9978 MW |
493 | /************************************************************************* |
494 | * EP93xx SPI peripheral handling | |
495 | *************************************************************************/ | |
496 | static struct ep93xx_spi_info ep93xx_spi_master_data; | |
497 | ||
498 | static struct resource ep93xx_spi_resources[] = { | |
499 | { | |
500 | .start = EP93XX_SPI_PHYS_BASE, | |
501 | .end = EP93XX_SPI_PHYS_BASE + 0x18 - 1, | |
502 | .flags = IORESOURCE_MEM, | |
503 | }, | |
504 | { | |
505 | .start = IRQ_EP93XX_SSP, | |
506 | .end = IRQ_EP93XX_SSP, | |
507 | .flags = IORESOURCE_IRQ, | |
508 | }, | |
509 | }; | |
510 | ||
626a96db MW |
511 | static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32); |
512 | ||
4fec9978 MW |
513 | static struct platform_device ep93xx_spi_device = { |
514 | .name = "ep93xx-spi", | |
515 | .id = 0, | |
516 | .dev = { | |
626a96db MW |
517 | .platform_data = &ep93xx_spi_master_data, |
518 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
519 | .dma_mask = &ep93xx_spi_dma_mask, | |
4fec9978 MW |
520 | }, |
521 | .num_resources = ARRAY_SIZE(ep93xx_spi_resources), | |
522 | .resource = ep93xx_spi_resources, | |
523 | }; | |
524 | ||
525 | /** | |
526 | * ep93xx_register_spi() - registers spi platform device | |
527 | * @info: ep93xx board specific spi master info (__initdata) | |
528 | * @devices: SPI devices to register (__initdata) | |
529 | * @num: number of SPI devices to register | |
530 | * | |
531 | * This function registers platform device for the EP93xx SPI controller and | |
532 | * also makes sure that SPI pins are muxed so that I2S is not using those pins. | |
533 | */ | |
534 | void __init ep93xx_register_spi(struct ep93xx_spi_info *info, | |
535 | struct spi_board_info *devices, int num) | |
536 | { | |
537 | /* | |
538 | * When SPI is used, we need to make sure that I2S is muxed off from | |
539 | * SPI pins. | |
540 | */ | |
541 | ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP); | |
542 | ||
543 | ep93xx_spi_master_data = *info; | |
544 | spi_register_board_info(devices, num); | |
545 | platform_device_register(&ep93xx_spi_device); | |
546 | } | |
3aa7a9a3 HS |
547 | |
548 | /************************************************************************* | |
549 | * EP93xx LEDs | |
550 | *************************************************************************/ | |
551 | static struct gpio_led ep93xx_led_pins[] = { | |
552 | { | |
b370e082 HS |
553 | .name = "platform:grled", |
554 | .gpio = EP93XX_GPIO_LINE_GRLED, | |
3aa7a9a3 | 555 | }, { |
b370e082 HS |
556 | .name = "platform:rdled", |
557 | .gpio = EP93XX_GPIO_LINE_RDLED, | |
3aa7a9a3 HS |
558 | }, |
559 | }; | |
560 | ||
561 | static struct gpio_led_platform_data ep93xx_led_data = { | |
562 | .num_leds = ARRAY_SIZE(ep93xx_led_pins), | |
563 | .leds = ep93xx_led_pins, | |
564 | }; | |
565 | ||
566 | static struct platform_device ep93xx_leds = { | |
567 | .name = "leds-gpio", | |
568 | .id = -1, | |
569 | .dev = { | |
570 | .platform_data = &ep93xx_led_data, | |
571 | }, | |
572 | }; | |
573 | ||
574 | ||
ef12379f HS |
575 | /************************************************************************* |
576 | * EP93xx pwm peripheral handling | |
577 | *************************************************************************/ | |
578 | static struct resource ep93xx_pwm0_resource[] = { | |
579 | { | |
580 | .start = EP93XX_PWM_PHYS_BASE, | |
581 | .end = EP93XX_PWM_PHYS_BASE + 0x10 - 1, | |
582 | .flags = IORESOURCE_MEM, | |
583 | }, | |
584 | }; | |
585 | ||
586 | static struct platform_device ep93xx_pwm0_device = { | |
587 | .name = "ep93xx-pwm", | |
588 | .id = 0, | |
589 | .num_resources = ARRAY_SIZE(ep93xx_pwm0_resource), | |
590 | .resource = ep93xx_pwm0_resource, | |
591 | }; | |
592 | ||
593 | static struct resource ep93xx_pwm1_resource[] = { | |
594 | { | |
595 | .start = EP93XX_PWM_PHYS_BASE + 0x20, | |
596 | .end = EP93XX_PWM_PHYS_BASE + 0x30 - 1, | |
597 | .flags = IORESOURCE_MEM, | |
598 | }, | |
599 | }; | |
600 | ||
601 | static struct platform_device ep93xx_pwm1_device = { | |
602 | .name = "ep93xx-pwm", | |
603 | .id = 1, | |
604 | .num_resources = ARRAY_SIZE(ep93xx_pwm1_resource), | |
605 | .resource = ep93xx_pwm1_resource, | |
606 | }; | |
607 | ||
608 | void __init ep93xx_register_pwm(int pwm0, int pwm1) | |
609 | { | |
610 | if (pwm0) | |
611 | platform_device_register(&ep93xx_pwm0_device); | |
612 | ||
613 | /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */ | |
614 | if (pwm1) | |
615 | platform_device_register(&ep93xx_pwm1_device); | |
616 | } | |
617 | ||
618 | int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) | |
619 | { | |
620 | int err; | |
621 | ||
622 | if (pdev->id == 0) { | |
623 | err = 0; | |
624 | } else if (pdev->id == 1) { | |
625 | err = gpio_request(EP93XX_GPIO_LINE_EGPIO14, | |
626 | dev_name(&pdev->dev)); | |
627 | if (err) | |
628 | return err; | |
629 | err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0); | |
630 | if (err) | |
631 | goto fail; | |
632 | ||
633 | /* PWM 1 output on EGPIO[14] */ | |
634 | ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG); | |
635 | } else { | |
636 | err = -ENODEV; | |
637 | } | |
638 | ||
639 | return err; | |
640 | ||
641 | fail: | |
642 | gpio_free(EP93XX_GPIO_LINE_EGPIO14); | |
643 | return err; | |
644 | } | |
645 | EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio); | |
646 | ||
647 | void ep93xx_pwm_release_gpio(struct platform_device *pdev) | |
648 | { | |
649 | if (pdev->id == 1) { | |
650 | gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14); | |
651 | gpio_free(EP93XX_GPIO_LINE_EGPIO14); | |
652 | ||
653 | /* EGPIO[14] used for GPIO */ | |
654 | ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG); | |
655 | } | |
656 | } | |
657 | EXPORT_SYMBOL(ep93xx_pwm_release_gpio); | |
658 | ||
659 | ||
c6012189 RM |
660 | /************************************************************************* |
661 | * EP93xx video peripheral handling | |
662 | *************************************************************************/ | |
663 | static struct ep93xxfb_mach_info ep93xxfb_data; | |
664 | ||
665 | static struct resource ep93xx_fb_resource[] = { | |
666 | { | |
667 | .start = EP93XX_RASTER_PHYS_BASE, | |
668 | .end = EP93XX_RASTER_PHYS_BASE + 0x800 - 1, | |
669 | .flags = IORESOURCE_MEM, | |
670 | }, | |
671 | }; | |
672 | ||
673 | static struct platform_device ep93xx_fb_device = { | |
674 | .name = "ep93xx-fb", | |
675 | .id = -1, | |
676 | .dev = { | |
b370e082 | 677 | .platform_data = &ep93xxfb_data, |
c6012189 RM |
678 | .coherent_dma_mask = DMA_BIT_MASK(32), |
679 | .dma_mask = &ep93xx_fb_device.dev.coherent_dma_mask, | |
680 | }, | |
681 | .num_resources = ARRAY_SIZE(ep93xx_fb_resource), | |
682 | .resource = ep93xx_fb_resource, | |
683 | }; | |
684 | ||
6ea4b741 HS |
685 | static struct platform_device ep93xx_bl_device = { |
686 | .name = "ep93xx-bl", | |
687 | .id = -1, | |
688 | }; | |
689 | ||
b370e082 HS |
690 | /** |
691 | * ep93xx_register_fb - Register the framebuffer platform device. | |
692 | * @data: platform specific framebuffer configuration (__initdata) | |
693 | */ | |
c6012189 RM |
694 | void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data) |
695 | { | |
696 | ep93xxfb_data = *data; | |
697 | platform_device_register(&ep93xx_fb_device); | |
6ea4b741 | 698 | platform_device_register(&ep93xx_bl_device); |
c6012189 RM |
699 | } |
700 | ||
12f56c68 HS |
701 | |
702 | /************************************************************************* | |
703 | * EP93xx matrix keypad peripheral handling | |
704 | *************************************************************************/ | |
b370e082 HS |
705 | static struct ep93xx_keypad_platform_data ep93xx_keypad_data; |
706 | ||
12f56c68 HS |
707 | static struct resource ep93xx_keypad_resource[] = { |
708 | { | |
709 | .start = EP93XX_KEY_MATRIX_PHYS_BASE, | |
710 | .end = EP93XX_KEY_MATRIX_PHYS_BASE + 0x0c - 1, | |
711 | .flags = IORESOURCE_MEM, | |
712 | }, { | |
713 | .start = IRQ_EP93XX_KEY, | |
714 | .end = IRQ_EP93XX_KEY, | |
715 | .flags = IORESOURCE_IRQ, | |
716 | }, | |
717 | }; | |
718 | ||
719 | static struct platform_device ep93xx_keypad_device = { | |
b370e082 HS |
720 | .name = "ep93xx-keypad", |
721 | .id = -1, | |
722 | .dev = { | |
723 | .platform_data = &ep93xx_keypad_data, | |
724 | }, | |
725 | .num_resources = ARRAY_SIZE(ep93xx_keypad_resource), | |
726 | .resource = ep93xx_keypad_resource, | |
12f56c68 HS |
727 | }; |
728 | ||
b370e082 HS |
729 | /** |
730 | * ep93xx_register_keypad - Register the keypad platform device. | |
731 | * @data: platform specific keypad configuration (__initdata) | |
732 | */ | |
12f56c68 HS |
733 | void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data) |
734 | { | |
b370e082 | 735 | ep93xx_keypad_data = *data; |
12f56c68 HS |
736 | platform_device_register(&ep93xx_keypad_device); |
737 | } | |
738 | ||
739 | int ep93xx_keypad_acquire_gpio(struct platform_device *pdev) | |
740 | { | |
741 | int err; | |
742 | int i; | |
743 | ||
744 | for (i = 0; i < 8; i++) { | |
745 | err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev)); | |
746 | if (err) | |
747 | goto fail_gpio_c; | |
748 | err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev)); | |
749 | if (err) | |
750 | goto fail_gpio_d; | |
751 | } | |
752 | ||
753 | /* Enable the keypad controller; GPIO ports C and D used for keypad */ | |
754 | ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS | | |
755 | EP93XX_SYSCON_DEVCFG_GONK); | |
756 | ||
757 | return 0; | |
758 | ||
759 | fail_gpio_d: | |
760 | gpio_free(EP93XX_GPIO_LINE_C(i)); | |
761 | fail_gpio_c: | |
762 | for ( ; i >= 0; --i) { | |
763 | gpio_free(EP93XX_GPIO_LINE_C(i)); | |
764 | gpio_free(EP93XX_GPIO_LINE_D(i)); | |
765 | } | |
766 | return err; | |
767 | } | |
768 | EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio); | |
769 | ||
770 | void ep93xx_keypad_release_gpio(struct platform_device *pdev) | |
771 | { | |
772 | int i; | |
773 | ||
774 | for (i = 0; i < 8; i++) { | |
775 | gpio_free(EP93XX_GPIO_LINE_C(i)); | |
776 | gpio_free(EP93XX_GPIO_LINE_D(i)); | |
777 | } | |
778 | ||
779 | /* Disable the keypad controller; GPIO ports C and D used for GPIO */ | |
780 | ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS | | |
781 | EP93XX_SYSCON_DEVCFG_GONK); | |
782 | } | |
783 | EXPORT_SYMBOL(ep93xx_keypad_release_gpio); | |
784 | ||
ed67ea82 RM |
785 | /************************************************************************* |
786 | * EP93xx I2S audio peripheral handling | |
787 | *************************************************************************/ | |
788 | static struct resource ep93xx_i2s_resource[] = { | |
789 | { | |
790 | .start = EP93XX_I2S_PHYS_BASE, | |
791 | .end = EP93XX_I2S_PHYS_BASE + 0x100 - 1, | |
792 | .flags = IORESOURCE_MEM, | |
793 | }, | |
794 | }; | |
795 | ||
796 | static struct platform_device ep93xx_i2s_device = { | |
797 | .name = "ep93xx-i2s", | |
798 | .id = -1, | |
799 | .num_resources = ARRAY_SIZE(ep93xx_i2s_resource), | |
800 | .resource = ep93xx_i2s_resource, | |
801 | }; | |
802 | ||
f0fba2ad LG |
803 | static struct platform_device ep93xx_pcm_device = { |
804 | .name = "ep93xx-pcm-audio", | |
805 | .id = -1, | |
806 | }; | |
807 | ||
ed67ea82 RM |
808 | void __init ep93xx_register_i2s(void) |
809 | { | |
810 | platform_device_register(&ep93xx_i2s_device); | |
f0fba2ad | 811 | platform_device_register(&ep93xx_pcm_device); |
ed67ea82 RM |
812 | } |
813 | ||
814 | #define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \ | |
815 | EP93XX_SYSCON_DEVCFG_I2SONAC97) | |
816 | ||
817 | #define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \ | |
818 | EP93XX_SYSCON_I2SCLKDIV_SPOL) | |
819 | ||
820 | int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config) | |
821 | { | |
822 | unsigned val; | |
823 | ||
824 | /* Sanity check */ | |
825 | if (i2s_pins & ~EP93XX_SYSCON_DEVCFG_I2S_MASK) | |
826 | return -EINVAL; | |
827 | if (i2s_config & ~EP93XX_I2SCLKDIV_MASK) | |
828 | return -EINVAL; | |
829 | ||
830 | /* Must have only one of I2SONSSP/I2SONAC97 set */ | |
831 | if ((i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONSSP) == | |
832 | (i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONAC97)) | |
833 | return -EINVAL; | |
834 | ||
835 | ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK); | |
836 | ep93xx_devcfg_set_bits(i2s_pins); | |
837 | ||
838 | /* | |
839 | * This is potentially racy with the clock api for i2s_mclk, sclk and | |
840 | * lrclk. Since the i2s driver is the only user of those clocks we | |
841 | * rely on it to prevent parallel use of this function and the | |
842 | * clock api for the i2s clocks. | |
843 | */ | |
844 | val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV); | |
845 | val &= ~EP93XX_I2SCLKDIV_MASK; | |
846 | val |= i2s_config; | |
847 | ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV); | |
848 | ||
849 | return 0; | |
850 | } | |
851 | EXPORT_SYMBOL(ep93xx_i2s_acquire); | |
852 | ||
853 | void ep93xx_i2s_release(void) | |
854 | { | |
855 | ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK); | |
856 | } | |
857 | EXPORT_SYMBOL(ep93xx_i2s_release); | |
12f56c68 | 858 | |
534bc7fa MW |
859 | /************************************************************************* |
860 | * EP93xx AC97 audio peripheral handling | |
861 | *************************************************************************/ | |
862 | static struct resource ep93xx_ac97_resources[] = { | |
863 | { | |
864 | .start = EP93XX_AAC_PHYS_BASE, | |
ec11594f | 865 | .end = EP93XX_AAC_PHYS_BASE + 0xac - 1, |
534bc7fa MW |
866 | .flags = IORESOURCE_MEM, |
867 | }, | |
868 | { | |
869 | .start = IRQ_EP93XX_AACINTR, | |
870 | .end = IRQ_EP93XX_AACINTR, | |
871 | .flags = IORESOURCE_IRQ, | |
872 | }, | |
873 | }; | |
874 | ||
875 | static struct platform_device ep93xx_ac97_device = { | |
876 | .name = "ep93xx-ac97", | |
877 | .id = -1, | |
878 | .num_resources = ARRAY_SIZE(ep93xx_ac97_resources), | |
879 | .resource = ep93xx_ac97_resources, | |
880 | }; | |
881 | ||
882 | void __init ep93xx_register_ac97(void) | |
883 | { | |
884 | /* | |
885 | * Make sure that the AC97 pins are not used by I2S. | |
886 | */ | |
887 | ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97); | |
888 | ||
889 | platform_device_register(&ep93xx_ac97_device); | |
890 | platform_device_register(&ep93xx_pcm_device); | |
891 | } | |
892 | ||
e7736d47 LB |
893 | void __init ep93xx_init_devices(void) |
894 | { | |
02239f0a HS |
895 | /* Disallow access to MaverickCrunch initially */ |
896 | ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); | |
aee85fe8 | 897 | |
1e4c8842 HS |
898 | /* Get the GPIO working early, other devices need it */ |
899 | platform_device_register(&ep93xx_gpio_device); | |
b685004f | 900 | |
aee85fe8 LB |
901 | amba_device_register(&uart1_device, &iomem_resource); |
902 | amba_device_register(&uart2_device, &iomem_resource); | |
903 | amba_device_register(&uart3_device, &iomem_resource); | |
41658132 LB |
904 | |
905 | platform_device_register(&ep93xx_rtc_device); | |
1f64eb37 | 906 | platform_device_register(&ep93xx_ohci_device); |
3aa7a9a3 | 907 | platform_device_register(&ep93xx_leds); |
e7736d47 | 908 | } |