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arm: convert core files from module.h to export.h
[deliverable/linux.git] / arch / arm / mach-ep93xx / core.c
CommitLineData
e7736d47
LB		 1/*
2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
3c9a071d 6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
e7736d47
LB		 7 *
8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9 * role in the ep93xx linux community.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 */
16
64d6882d
HS		 17#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
18
e7736d47
LB		 19#include <linux/kernel.h>
20#include <linux/init.h>
583ddafe 21#include <linux/platform_device.h>
e7736d47 22#include <linux/interrupt.h>
63890a0e 23#include <linux/dma-mapping.h>
e7736d47 24#include <linux/timex.h>
6bd4b382 25#include <linux/irq.h>
583ddafe
HS		 26#include <linux/io.h>
27#include <linux/gpio.h>
3aa7a9a3 28#include <linux/leds.h>
aee85fe8 29#include <linux/termios.h>
e7736d47 30#include <linux/amba/bus.h>
aee85fe8 31#include <linux/amba/serial.h>
16bcf78f 32#include <linux/mtd/physmap.h>
d52a26a9
HS		 33#include <linux/i2c.h>
34#include <linux/i2c-gpio.h>
4fec9978 35#include <linux/spi/spi.h>
e7736d47 36
a09e64fb 37#include <mach/hardware.h>
c6012189 38#include <mach/fb.h>
12f56c68 39#include <mach/ep93xx_keypad.h>
4fec9978 40#include <mach/ep93xx_spi.h>
bd5f12a2 41#include <mach/gpio-ep93xx.h>
e7736d47
LB		 42
43#include <asm/mach/map.h>
44#include <asm/mach/time.h>
e7736d47
LB		 45
46#include <asm/hardware/vic.h>
47
48
49/*************************************************************************
50 * Static I/O mappings that are needed for all EP93xx platforms
51 *************************************************************************/
52static struct map_desc ep93xx_io_desc[] __initdata = {
53 {
54 .virtual = EP93XX_AHB_VIRT_BASE,
55 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
56 .length = EP93XX_AHB_SIZE,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = EP93XX_APB_VIRT_BASE,
60 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
61 .length = EP93XX_APB_SIZE,
62 .type = MT_DEVICE,
63 },
64};
65
66void __init ep93xx_map_io(void)
67{
68 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
69}
70
71
72/*************************************************************************
73 * Timer handling for EP93xx
74 *************************************************************************
75 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
76 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
77 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
78 * is free-running, and can't generate interrupts.
79 *
80 * The 508 kHz timers are ideal for use for the timer interrupt, as the
81 * most common values of HZ divide 508 kHz nicely. We pick one of the 16
82 * bit timers (timer 1) since we don't need more than 16 bits of reload
83 * value as long as HZ >= 8.
84 *
85 * The higher clock rate of timer 4 makes it a better choice than the
86 * other timers for use in gettimeoffset(), while the fact that it can't
87 * generate interrupts means we don't have to worry about not being able
88 * to use this timer for something else. We also use timer 4 for keeping
89 * track of lost jiffies.
90 */
1587a373
HS		 91#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
92#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
93#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
94#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
95#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
96#define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
97#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
98#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
99#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
100#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
101#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
102#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
103#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
104#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
105#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
106#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
107#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
108#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
109#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
110
111#define EP93XX_TIMER123_CLOCK 508469
112#define EP93XX_TIMER4_CLOCK 983040
113
114#define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1)
af1057ab 115#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
e7736d47 116
1587a373
HS		 117static unsigned int last_jiffy_time;
118
d5565f76 119static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
e7736d47 120{
1587a373 121 /* Writing any value clears the timer interrupt */
e7736d47 122 __raw_writel(1, EP93XX_TIMER1_CLEAR);
1587a373
HS		 123
124 /* Recover lost jiffies */
f869afab
LB		 125 while ((signed long)
126 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
e7736d47
LB		 127 >= TIMER4_TICKS_PER_JIFFY) {
128 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
0cd61b68 129 timer_tick();
e7736d47
LB		 130 }
131
e7736d47
LB		 132 return IRQ_HANDLED;
133}
134
135static struct irqaction ep93xx_timer_irq = {
136 .name = "ep93xx timer",
b30fabad 137 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
e7736d47
LB		 138 .handler = ep93xx_timer_interrupt,
139};
140
141static void __init ep93xx_timer_init(void)
142{
1587a373
HS		 143 u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
144 EP93XX_TIMER123_CONTROL_CLKSEL;
145
e7736d47 146 /* Enable periodic HZ timer. */
1587a373
HS		 147 __raw_writel(tmode, EP93XX_TIMER1_CONTROL);
148 __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
149 __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
150 EP93XX_TIMER1_CONTROL);
e7736d47
LB		 151
152 /* Enable lost jiffy timer. */
1587a373
HS		 153 __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
154 EP93XX_TIMER4_VALUE_HIGH);
e7736d47
LB		 155
156 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
157}
158
159static unsigned long ep93xx_gettimeoffset(void)
160{
161 int offset;
162
163 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
164
165 /* Calculate (1000000 / 983040) * offset. */
166 return offset + (53 * offset / 3072);
167}
168
169struct sys_timer ep93xx_timer = {
170 .init = ep93xx_timer_init,
171 .offset = ep93xx_gettimeoffset,
172};
173
174
175/*************************************************************************
176 * EP93xx IRQ handling
177 *************************************************************************/
178void __init ep93xx_init_irq(void)
179{
5396730b
HS		 180 vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
181 vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
e7736d47
LB		 182}
183
184
02239f0a
HS		 185/*************************************************************************
186 * EP93xx System Controller Software Locked register handling
187 *************************************************************************/
188
189/*
190 * syscon_swlock prevents anything else from writing to the syscon
191 * block while a software locked register is being written.
192 */
193static DEFINE_SPINLOCK(syscon_swlock);
194
fbeeea53 195void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
02239f0a
HS		 196{
197 unsigned long flags;
198
199 spin_lock_irqsave(&syscon_swlock, flags);
200
201 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
202 __raw_writel(val, reg);
203
204 spin_unlock_irqrestore(&syscon_swlock, flags);
205}
206EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
207
208void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
209{
210 unsigned long flags;
211 unsigned int val;
212
213 spin_lock_irqsave(&syscon_swlock, flags);
214
215 val = __raw_readl(EP93XX_SYSCON_DEVCFG);
02239f0a 216 val &= ~clear_bits;
a0fb007b 217 val |= set_bits;
02239f0a
HS		 218 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
219 __raw_writel(val, EP93XX_SYSCON_DEVCFG);
220
221 spin_unlock_irqrestore(&syscon_swlock, flags);
222}
223EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
224
99e6a23a
MW		 225/**
226 * ep93xx_chip_revision() - returns the EP93xx chip revision
227 *
228 * See <mach/platform.h> for more information.
229 */
230unsigned int ep93xx_chip_revision(void)
231{
232 unsigned int v;
233
234 v = __raw_readl(EP93XX_SYSCON_SYSCFG);
235 v &= EP93XX_SYSCON_SYSCFG_REV_MASK;
236 v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT;
237 return v;
238}
02239f0a 239
1e4c8842
HS		 240/*************************************************************************
241 * EP93xx GPIO
242 *************************************************************************/
243static struct resource ep93xx_gpio_resource[] = {
244 {
245 .start = EP93XX_GPIO_PHYS_BASE,
246 .end = EP93XX_GPIO_PHYS_BASE + 0xcc - 1,
247 .flags = IORESOURCE_MEM,
248 },
249};
250
251static struct platform_device ep93xx_gpio_device = {
252 .name = "gpio-ep93xx",
253 .id = -1,
254 .num_resources = ARRAY_SIZE(ep93xx_gpio_resource),
255 .resource = ep93xx_gpio_resource,
256};
257
e7736d47
LB		 258/*************************************************************************
259 * EP93xx peripheral handling
260 *************************************************************************/
aee85fe8
LB		 261#define EP93XX_UART_MCR_OFFSET (0x0100)
262
263static void ep93xx_uart_set_mctrl(struct amba_device *dev,
264 void __iomem *base, unsigned int mctrl)
265{
266 unsigned int mcr;
267
268 mcr = 0;
186dcaa4 269 if (mctrl & TIOCM_RTS)
aee85fe8 270 mcr |= 2;
186dcaa4 271 if (mctrl & TIOCM_DTR)
aee85fe8
LB		 272 mcr |= 1;
273
274 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
275}
276
277static struct amba_pl010_data ep93xx_uart_data = {
278 .set_mctrl = ep93xx_uart_set_mctrl,
279};
280
281static struct amba_device uart1_device = {
282 .dev = {
1d559e29 283 .init_name = "apb:uart1",
aee85fe8
LB		 284 .platform_data = &ep93xx_uart_data,
285 },
286 .res = {
287 .start = EP93XX_UART1_PHYS_BASE,
288 .end = EP93XX_UART1_PHYS_BASE + 0x0fff,
289 .flags = IORESOURCE_MEM,
290 },
291 .irq = { IRQ_EP93XX_UART1, NO_IRQ },
292 .periphid = 0x00041010,
293};
294
295static struct amba_device uart2_device = {
296 .dev = {
1d559e29 297 .init_name = "apb:uart2",
aee85fe8
LB		 298 .platform_data = &ep93xx_uart_data,
299 },
300 .res = {
301 .start = EP93XX_UART2_PHYS_BASE,
302 .end = EP93XX_UART2_PHYS_BASE + 0x0fff,
303 .flags = IORESOURCE_MEM,
304 },
305 .irq = { IRQ_EP93XX_UART2, NO_IRQ },
306 .periphid = 0x00041010,
307};
308
309static struct amba_device uart3_device = {
310 .dev = {
1d559e29 311 .init_name = "apb:uart3",
aee85fe8
LB		 312 .platform_data = &ep93xx_uart_data,
313 },
314 .res = {
315 .start = EP93XX_UART3_PHYS_BASE,
316 .end = EP93XX_UART3_PHYS_BASE + 0x0fff,
317 .flags = IORESOURCE_MEM,
318 },
319 .irq = { IRQ_EP93XX_UART3, NO_IRQ },
320 .periphid = 0x00041010,
321};
322
41658132 323
38f7b009
HS		 324static struct resource ep93xx_rtc_resource[] = {
325 {
326 .start = EP93XX_RTC_PHYS_BASE,
327 .end = EP93XX_RTC_PHYS_BASE + 0x10c - 1,
328 .flags = IORESOURCE_MEM,
329 },
330};
331
41658132 332static struct platform_device ep93xx_rtc_device = {
38f7b009
HS		 333 .name = "ep93xx-rtc",
334 .id = -1,
335 .num_resources = ARRAY_SIZE(ep93xx_rtc_resource),
336 .resource = ep93xx_rtc_resource,
41658132
LB		 337};
338
339
1f64eb37
LB		 340static struct resource ep93xx_ohci_resources[] = {
341 [0] = {
342 .start = EP93XX_USB_PHYS_BASE,
343 .end = EP93XX_USB_PHYS_BASE + 0x0fff,
344 .flags = IORESOURCE_MEM,
345 },
346 [1] = {
347 .start = IRQ_EP93XX_USB,
348 .end = IRQ_EP93XX_USB,
349 .flags = IORESOURCE_IRQ,
350 },
351};
352
63890a0e 353
1f64eb37
LB		 354static struct platform_device ep93xx_ohci_device = {
355 .name = "ep93xx-ohci",
356 .id = -1,
357 .dev = {
63890a0e
MK		 358 .dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask,
359 .coherent_dma_mask = DMA_BIT_MASK(32),
1f64eb37
LB		 360 },
361 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
362 .resource = ep93xx_ohci_resources,
363};
364
b370e082 365
16bcf78f
HS		 366/*************************************************************************
367 * EP93xx physmap'ed flash
368 *************************************************************************/
369static struct physmap_flash_data ep93xx_flash_data;
370
371static struct resource ep93xx_flash_resource = {
372 .flags = IORESOURCE_MEM,
373};
374
375static struct platform_device ep93xx_flash = {
376 .name = "physmap-flash",
377 .id = 0,
378 .dev = {
379 .platform_data = &ep93xx_flash_data,
380 },
381 .num_resources = 1,
382 .resource = &ep93xx_flash_resource,
383};
384
385/**
386 * ep93xx_register_flash() - Register the external flash device.
387 * @width: bank width in octets
388 * @start: resource start address
389 * @size: resource size
390 */
391void __init ep93xx_register_flash(unsigned int width,
392 resource_size_t start, resource_size_t size)
393{
394 ep93xx_flash_data.width = width;
395
396 ep93xx_flash_resource.start = start;
397 ep93xx_flash_resource.end = start + size - 1;
398
399 platform_device_register(&ep93xx_flash);
400}
401
402
b370e082
HS		 403/*************************************************************************
404 * EP93xx ethernet peripheral handling
405 *************************************************************************/
a0a08fdc
HS		 406static struct ep93xx_eth_data ep93xx_eth_data;
407
408static struct resource ep93xx_eth_resource[] = {
409 {
410 .start = EP93XX_ETHERNET_PHYS_BASE,
411 .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
412 .flags = IORESOURCE_MEM,
413 }, {
414 .start = IRQ_EP93XX_ETHERNET,
415 .end = IRQ_EP93XX_ETHERNET,
416 .flags = IORESOURCE_IRQ,
417 }
418};
419
fa70cf47
MW		 420static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32);
421
a0a08fdc
HS		 422static struct platform_device ep93xx_eth_device = {
423 .name = "ep93xx-eth",
424 .id = -1,
425 .dev = {
fa70cf47
MW		 426 .platform_data = &ep93xx_eth_data,
427 .coherent_dma_mask = DMA_BIT_MASK(32),
428 .dma_mask = &ep93xx_eth_dma_mask,
a0a08fdc
HS		 429 },
430 .num_resources = ARRAY_SIZE(ep93xx_eth_resource),
431 .resource = ep93xx_eth_resource,
432};
433
b370e082
HS		 434/**
435 * ep93xx_register_eth - Register the built-in ethernet platform device.
436 * @data: platform specific ethernet configuration (__initdata)
437 * @copy_addr: flag indicating that the MAC address should be copied
438 * from the IndAd registers (as programmed by the bootloader)
439 */
a0a08fdc
HS		 440void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
441{
5b1c3c85
HS		 442 if (copy_addr)
443 memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
a0a08fdc
HS		 444
445 ep93xx_eth_data = *data;
446 platform_device_register(&ep93xx_eth_device);
447}
448
6531a991
HS		 449
450/*************************************************************************
451 * EP93xx i2c peripheral handling
452 *************************************************************************/
453static struct i2c_gpio_platform_data ep93xx_i2c_data;
d52a26a9
HS		 454
455static struct platform_device ep93xx_i2c_device = {
b370e082
HS		 456 .name = "i2c-gpio",
457 .id = 0,
458 .dev = {
459 .platform_data = &ep93xx_i2c_data,
460 },
d52a26a9
HS		 461};
462
b370e082
HS		 463/**
464 * ep93xx_register_i2c - Register the i2c platform device.
465 * @data: platform specific i2c-gpio configuration (__initdata)
466 * @devices: platform specific i2c bus device information (__initdata)
467 * @num: the number of devices on the i2c bus
468 */
6531a991
HS		 469void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
470 struct i2c_board_info *devices, int num)
d52a26a9 471{
6531a991
HS		 472 /*
473 * Set the EEPROM interface pin drive type control.
474 * Defines the driver type for the EECLK and EEDAT pins as either
475 * open drain, which will require an external pull-up, or a normal
476 * CMOS driver.
477 */
478 if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
64d6882d 479 pr_warning("sda != EEDAT, open drain has no effect\n");
6531a991 480 if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
64d6882d 481 pr_warning("scl != EECLK, open drain has no effect\n");
6531a991
HS		 482
483 __raw_writel((data->sda_is_open_drain << 1) |
484 (data->scl_is_open_drain << 0),
485 EP93XX_GPIO_EEDRIVE);
486
487 ep93xx_i2c_data = *data;
d52a26a9
HS		 488 i2c_register_board_info(0, devices, num);
489 platform_device_register(&ep93xx_i2c_device);
490}
491
4fec9978
MW		 492/*************************************************************************
493 * EP93xx SPI peripheral handling
494 *************************************************************************/
495static struct ep93xx_spi_info ep93xx_spi_master_data;
496
497static struct resource ep93xx_spi_resources[] = {
498 {
499 .start = EP93XX_SPI_PHYS_BASE,
500 .end = EP93XX_SPI_PHYS_BASE + 0x18 - 1,
501 .flags = IORESOURCE_MEM,
502 },
503 {
504 .start = IRQ_EP93XX_SSP,
505 .end = IRQ_EP93XX_SSP,
506 .flags = IORESOURCE_IRQ,
507 },
508};
509
626a96db
MW		 510static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
511
4fec9978
MW		 512static struct platform_device ep93xx_spi_device = {
513 .name = "ep93xx-spi",
514 .id = 0,
515 .dev = {
626a96db
MW		 516 .platform_data = &ep93xx_spi_master_data,
517 .coherent_dma_mask = DMA_BIT_MASK(32),
518 .dma_mask = &ep93xx_spi_dma_mask,
4fec9978
MW		 519 },
520 .num_resources = ARRAY_SIZE(ep93xx_spi_resources),
521 .resource = ep93xx_spi_resources,
522};
523
524/**
525 * ep93xx_register_spi() - registers spi platform device
526 * @info: ep93xx board specific spi master info (__initdata)
527 * @devices: SPI devices to register (__initdata)
528 * @num: number of SPI devices to register
529 *
530 * This function registers platform device for the EP93xx SPI controller and
531 * also makes sure that SPI pins are muxed so that I2S is not using those pins.
532 */
533void __init ep93xx_register_spi(struct ep93xx_spi_info *info,
534 struct spi_board_info *devices, int num)
535{
536 /*
537 * When SPI is used, we need to make sure that I2S is muxed off from
538 * SPI pins.
539 */
540 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP);
541
542 ep93xx_spi_master_data = *info;
543 spi_register_board_info(devices, num);
544 platform_device_register(&ep93xx_spi_device);
545}
3aa7a9a3
HS		 546
547/*************************************************************************
548 * EP93xx LEDs
549 *************************************************************************/
550static struct gpio_led ep93xx_led_pins[] = {
551 {
b370e082
HS		 552 .name = "platform:grled",
553 .gpio = EP93XX_GPIO_LINE_GRLED,
3aa7a9a3 554 }, {
b370e082
HS		 555 .name = "platform:rdled",
556 .gpio = EP93XX_GPIO_LINE_RDLED,
3aa7a9a3
HS		 557 },
558};
559
560static struct gpio_led_platform_data ep93xx_led_data = {
561 .num_leds = ARRAY_SIZE(ep93xx_led_pins),
562 .leds = ep93xx_led_pins,
563};
564
565static struct platform_device ep93xx_leds = {
566 .name = "leds-gpio",
567 .id = -1,
568 .dev = {
569 .platform_data = &ep93xx_led_data,
570 },
571};
572
573
ef12379f
HS		 574/*************************************************************************
575 * EP93xx pwm peripheral handling
576 *************************************************************************/
577static struct resource ep93xx_pwm0_resource[] = {
578 {
579 .start = EP93XX_PWM_PHYS_BASE,
580 .end = EP93XX_PWM_PHYS_BASE + 0x10 - 1,
581 .flags = IORESOURCE_MEM,
582 },
583};
584
585static struct platform_device ep93xx_pwm0_device = {
586 .name = "ep93xx-pwm",
587 .id = 0,
588 .num_resources = ARRAY_SIZE(ep93xx_pwm0_resource),
589 .resource = ep93xx_pwm0_resource,
590};
591
592static struct resource ep93xx_pwm1_resource[] = {
593 {
594 .start = EP93XX_PWM_PHYS_BASE + 0x20,
595 .end = EP93XX_PWM_PHYS_BASE + 0x30 - 1,
596 .flags = IORESOURCE_MEM,
597 },
598};
599
600static struct platform_device ep93xx_pwm1_device = {
601 .name = "ep93xx-pwm",
602 .id = 1,
603 .num_resources = ARRAY_SIZE(ep93xx_pwm1_resource),
604 .resource = ep93xx_pwm1_resource,
605};
606
607void __init ep93xx_register_pwm(int pwm0, int pwm1)
608{
609 if (pwm0)
610 platform_device_register(&ep93xx_pwm0_device);
611
612 /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
613 if (pwm1)
614 platform_device_register(&ep93xx_pwm1_device);
615}
616
617int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
618{
619 int err;
620
621 if (pdev->id == 0) {
622 err = 0;
623 } else if (pdev->id == 1) {
624 err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
625 dev_name(&pdev->dev));
626 if (err)
627 return err;
628 err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
629 if (err)
630 goto fail;
631
632 /* PWM 1 output on EGPIO[14] */
633 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
634 } else {
635 err = -ENODEV;
636 }
637
638 return err;
639
640fail:
641 gpio_free(EP93XX_GPIO_LINE_EGPIO14);
642 return err;
643}
644EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
645
646void ep93xx_pwm_release_gpio(struct platform_device *pdev)
647{
648 if (pdev->id == 1) {
649 gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
650 gpio_free(EP93XX_GPIO_LINE_EGPIO14);
651
652 /* EGPIO[14] used for GPIO */
653 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
654 }
655}
656EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
657
658
c6012189
RM		 659/*************************************************************************
660 * EP93xx video peripheral handling
661 *************************************************************************/
662static struct ep93xxfb_mach_info ep93xxfb_data;
663
664static struct resource ep93xx_fb_resource[] = {
665 {
666 .start = EP93XX_RASTER_PHYS_BASE,
667 .end = EP93XX_RASTER_PHYS_BASE + 0x800 - 1,
668 .flags = IORESOURCE_MEM,
669 },
670};
671
672static struct platform_device ep93xx_fb_device = {
673 .name = "ep93xx-fb",
674 .id = -1,
675 .dev = {
b370e082 676 .platform_data = &ep93xxfb_data,
c6012189
RM		 677 .coherent_dma_mask = DMA_BIT_MASK(32),
678 .dma_mask = &ep93xx_fb_device.dev.coherent_dma_mask,
679 },
680 .num_resources = ARRAY_SIZE(ep93xx_fb_resource),
681 .resource = ep93xx_fb_resource,
682};
683
6ea4b741
HS		 684static struct platform_device ep93xx_bl_device = {
685 .name = "ep93xx-bl",
686 .id = -1,
687};
688
b370e082
HS		 689/**
690 * ep93xx_register_fb - Register the framebuffer platform device.
691 * @data: platform specific framebuffer configuration (__initdata)
692 */
c6012189
RM		 693void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
694{
695 ep93xxfb_data = *data;
696 platform_device_register(&ep93xx_fb_device);
6ea4b741 697 platform_device_register(&ep93xx_bl_device);
c6012189
RM		 698}
699
12f56c68
HS		 700
701/*************************************************************************
702 * EP93xx matrix keypad peripheral handling
703 *************************************************************************/
b370e082
HS		 704static struct ep93xx_keypad_platform_data ep93xx_keypad_data;
705
12f56c68
HS		 706static struct resource ep93xx_keypad_resource[] = {
707 {
708 .start = EP93XX_KEY_MATRIX_PHYS_BASE,
709 .end = EP93XX_KEY_MATRIX_PHYS_BASE + 0x0c - 1,
710 .flags = IORESOURCE_MEM,
711 }, {
712 .start = IRQ_EP93XX_KEY,
713 .end = IRQ_EP93XX_KEY,
714 .flags = IORESOURCE_IRQ,
715 },
716};
717
718static struct platform_device ep93xx_keypad_device = {
b370e082
HS		 719 .name = "ep93xx-keypad",
720 .id = -1,
721 .dev = {
722 .platform_data = &ep93xx_keypad_data,
723 },
724 .num_resources = ARRAY_SIZE(ep93xx_keypad_resource),
725 .resource = ep93xx_keypad_resource,
12f56c68
HS		 726};
727
b370e082
HS		 728/**
729 * ep93xx_register_keypad - Register the keypad platform device.
730 * @data: platform specific keypad configuration (__initdata)
731 */
12f56c68
HS		 732void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data)
733{
b370e082 734 ep93xx_keypad_data = *data;
12f56c68
HS		 735 platform_device_register(&ep93xx_keypad_device);
736}
737
738int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)
739{
740 int err;
741 int i;
742
743 for (i = 0; i < 8; i++) {
744 err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev));
745 if (err)
746 goto fail_gpio_c;
747 err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev));
748 if (err)
749 goto fail_gpio_d;
750 }
751
752 /* Enable the keypad controller; GPIO ports C and D used for keypad */
753 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS |
754 EP93XX_SYSCON_DEVCFG_GONK);
755
756 return 0;
757
758fail_gpio_d:
759 gpio_free(EP93XX_GPIO_LINE_C(i));
760fail_gpio_c:
761 for ( ; i >= 0; --i) {
762 gpio_free(EP93XX_GPIO_LINE_C(i));
763 gpio_free(EP93XX_GPIO_LINE_D(i));
764 }
765 return err;
766}
767EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio);
768
769void ep93xx_keypad_release_gpio(struct platform_device *pdev)
770{
771 int i;
772
773 for (i = 0; i < 8; i++) {
774 gpio_free(EP93XX_GPIO_LINE_C(i));
775 gpio_free(EP93XX_GPIO_LINE_D(i));
776 }
777
778 /* Disable the keypad controller; GPIO ports C and D used for GPIO */
779 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
780 EP93XX_SYSCON_DEVCFG_GONK);
781}
782EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
783
ed67ea82
RM		 784/*************************************************************************
785 * EP93xx I2S audio peripheral handling
786 *************************************************************************/
787static struct resource ep93xx_i2s_resource[] = {
788 {
789 .start = EP93XX_I2S_PHYS_BASE,
790 .end = EP93XX_I2S_PHYS_BASE + 0x100 - 1,
791 .flags = IORESOURCE_MEM,
792 },
793};
794
795static struct platform_device ep93xx_i2s_device = {
796 .name = "ep93xx-i2s",
797 .id = -1,
798 .num_resources = ARRAY_SIZE(ep93xx_i2s_resource),
799 .resource = ep93xx_i2s_resource,
800};
801
f0fba2ad
LG		 802static struct platform_device ep93xx_pcm_device = {
803 .name = "ep93xx-pcm-audio",
804 .id = -1,
805};
806
ed67ea82
RM		 807void __init ep93xx_register_i2s(void)
808{
809 platform_device_register(&ep93xx_i2s_device);
f0fba2ad 810 platform_device_register(&ep93xx_pcm_device);
ed67ea82
RM		 811}
812
813#define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \
814 EP93XX_SYSCON_DEVCFG_I2SONAC97)
815
816#define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
817 EP93XX_SYSCON_I2SCLKDIV_SPOL)
818
819int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config)
820{
821 unsigned val;
822
823 /* Sanity check */
824 if (i2s_pins & ~EP93XX_SYSCON_DEVCFG_I2S_MASK)
825 return -EINVAL;
826 if (i2s_config & ~EP93XX_I2SCLKDIV_MASK)
827 return -EINVAL;
828
829 /* Must have only one of I2SONSSP/I2SONAC97 set */
830 if ((i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONSSP) ==
831 (i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONAC97))
832 return -EINVAL;
833
834 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
835 ep93xx_devcfg_set_bits(i2s_pins);
836
837 /*
838 * This is potentially racy with the clock api for i2s_mclk, sclk and
839 * lrclk. Since the i2s driver is the only user of those clocks we
840 * rely on it to prevent parallel use of this function and the
841 * clock api for the i2s clocks.
842 */
843 val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
844 val &= ~EP93XX_I2SCLKDIV_MASK;
845 val |= i2s_config;
846 ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
847
848 return 0;
849}
850EXPORT_SYMBOL(ep93xx_i2s_acquire);
851
852void ep93xx_i2s_release(void)
853{
854 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
855}
856EXPORT_SYMBOL(ep93xx_i2s_release);
12f56c68 857
534bc7fa
MW		 858/*************************************************************************
859 * EP93xx AC97 audio peripheral handling
860 *************************************************************************/
861static struct resource ep93xx_ac97_resources[] = {
862 {
863 .start = EP93XX_AAC_PHYS_BASE,
ec11594f 864 .end = EP93XX_AAC_PHYS_BASE + 0xac - 1,
534bc7fa
MW		 865 .flags = IORESOURCE_MEM,
866 },
867 {
868 .start = IRQ_EP93XX_AACINTR,
869 .end = IRQ_EP93XX_AACINTR,
870 .flags = IORESOURCE_IRQ,
871 },
872};
873
874static struct platform_device ep93xx_ac97_device = {
875 .name = "ep93xx-ac97",
876 .id = -1,
877 .num_resources = ARRAY_SIZE(ep93xx_ac97_resources),
878 .resource = ep93xx_ac97_resources,
879};
880
881void __init ep93xx_register_ac97(void)
882{
883 /*
884 * Make sure that the AC97 pins are not used by I2S.
885 */
886 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97);
887
888 platform_device_register(&ep93xx_ac97_device);
889 platform_device_register(&ep93xx_pcm_device);
890}
891
e7736d47
LB		 892void __init ep93xx_init_devices(void)
893{
02239f0a
HS		 894 /* Disallow access to MaverickCrunch initially */
895 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
aee85fe8 896
1e4c8842
HS		 897 /* Get the GPIO working early, other devices need it */
898 platform_device_register(&ep93xx_gpio_device);
b685004f 899
aee85fe8
LB		 900 amba_device_register(&uart1_device, &iomem_resource);
901 amba_device_register(&uart2_device, &iomem_resource);
902 amba_device_register(&uart3_device, &iomem_resource);
41658132
LB		 903
904 platform_device_register(&ep93xx_rtc_device);
1f64eb37 905 platform_device_register(&ep93xx_ohci_device);
3aa7a9a3 906 platform_device_register(&ep93xx_leds);
e7736d47 907}
Linux kernel - Deliverables
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