[deliverable/linux.git] / arch / arm / mach-ep93xx / include / mach / ep93xx-regs.h

/*
 * arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
 */

#ifndef __ASM_ARCH_EP93XX_REGS_H
#define __ASM_ARCH_EP93XX_REGS_H

/*
 * EP93xx Physical Memory Map:
 *
 * The ASDO pin is sampled at system reset to select a synchronous or
 * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
 * the synchronous boot mode is selected.  When ASDO is "0" (i.e
 * pulled-down) the asynchronous boot mode is selected.
 *
 * In synchronous boot mode nSDCE3 is decoded starting at physical address
 * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
 * decoded at 0xf0000000.
 *
 * There is known errata for the EP93xx dealing with External Memory
 * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
 * Guidelines" for more information.  This document can be found at:
 *
 *	http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
 */

#define EP93XX_CS0_PHYS_BASE_ASYNC	0x00000000	/* ASDO Pin = 0 */
#define EP93XX_SDCE3_PHYS_BASE_SYNC	0x00000000	/* ASDO Pin = 1 */
#define EP93XX_CS1_PHYS_BASE		0x10000000
#define EP93XX_CS2_PHYS_BASE		0x20000000
#define EP93XX_CS3_PHYS_BASE		0x30000000
#define EP93XX_PCMCIA_PHYS_BASE		0x40000000
#define EP93XX_CS6_PHYS_BASE		0x60000000
#define EP93XX_CS7_PHYS_BASE		0x70000000
#define EP93XX_SDCE0_PHYS_BASE		0xc0000000
#define EP93XX_SDCE1_PHYS_BASE		0xd0000000
#define EP93XX_SDCE2_PHYS_BASE		0xe0000000
#define EP93XX_SDCE3_PHYS_BASE_ASYNC	0xf0000000	/* ASDO Pin = 0 */
#define EP93XX_CS0_PHYS_BASE_SYNC	0xf0000000	/* ASDO Pin = 1 */

/*
 * EP93xx linux memory map:
 *
 * virt		phys		size
 * fe800000			5M		per-platform mappings
 * fed00000	80800000	2M		APB
 * fef00000	80000000	1M		AHB
 */

#define EP93XX_AHB_PHYS_BASE		0x80000000
#define EP93XX_AHB_VIRT_BASE		0xfef00000
#define EP93XX_AHB_SIZE			0x00100000

#define EP93XX_AHB_IOMEM(x)		IOMEM(EP93XX_AHB_VIRT_BASE + (x))

#define EP93XX_APB_PHYS_BASE		0x80800000
#define EP93XX_APB_VIRT_BASE		0xfed00000
#define EP93XX_APB_SIZE			0x00200000

#define EP93XX_APB_IOMEM(x)		IOMEM(EP93XX_APB_VIRT_BASE + (x))


/* AHB peripherals */
#define EP93XX_DMA_BASE			EP93XX_AHB_IOMEM(0x00000000)

#define EP93XX_ETHERNET_PHYS_BASE	(EP93XX_AHB_PHYS_BASE + 0x00010000)
#define EP93XX_ETHERNET_BASE		EP93XX_AHB_IOMEM(0x00010000)

#define EP93XX_USB_PHYS_BASE		(EP93XX_AHB_PHYS_BASE + 0x00020000)
#define EP93XX_USB_BASE			EP93XX_AHB_IOMEM(0x00020000)

#define EP93XX_RASTER_BASE		EP93XX_AHB_IOMEM(0x00030000)

#define EP93XX_GRAPHICS_ACCEL_BASE	EP93XX_AHB_IOMEM(0x00040000)

#define EP93XX_SDRAM_CONTROLLER_BASE	EP93XX_AHB_IOMEM(0x00060000)

#define EP93XX_PCMCIA_CONTROLLER_BASE	EP93XX_AHB_IOMEM(0x00080000)

#define EP93XX_BOOT_ROM_BASE		EP93XX_AHB_IOMEM(0x00090000)

#define EP93XX_IDE_BASE			EP93XX_AHB_IOMEM(0x000a0000)

#define EP93XX_VIC1_BASE		EP93XX_AHB_IOMEM(0x000b0000)

#define EP93XX_VIC2_BASE		EP93XX_AHB_IOMEM(0x000c0000)


/* APB peripherals */
#define EP93XX_TIMER_BASE		EP93XX_APB_IOMEM(0x00010000)
#define EP93XX_TIMER_REG(x)		(EP93XX_TIMER_BASE + (x))
#define EP93XX_TIMER1_LOAD		EP93XX_TIMER_REG(0x00)
#define EP93XX_TIMER1_VALUE		EP93XX_TIMER_REG(0x04)
#define EP93XX_TIMER1_CONTROL		EP93XX_TIMER_REG(0x08)
#define EP93XX_TIMER1_CLEAR		EP93XX_TIMER_REG(0x0c)
#define EP93XX_TIMER2_LOAD		EP93XX_TIMER_REG(0x20)
#define EP93XX_TIMER2_VALUE		EP93XX_TIMER_REG(0x24)
#define EP93XX_TIMER2_CONTROL		EP93XX_TIMER_REG(0x28)
#define EP93XX_TIMER2_CLEAR		EP93XX_TIMER_REG(0x2c)
#define EP93XX_TIMER4_VALUE_LOW		EP93XX_TIMER_REG(0x60)
#define EP93XX_TIMER4_VALUE_HIGH	EP93XX_TIMER_REG(0x64)
#define EP93XX_TIMER3_LOAD		EP93XX_TIMER_REG(0x80)
#define EP93XX_TIMER3_VALUE		EP93XX_TIMER_REG(0x84)
#define EP93XX_TIMER3_CONTROL		EP93XX_TIMER_REG(0x88)
#define EP93XX_TIMER3_CLEAR		EP93XX_TIMER_REG(0x8c)

#define EP93XX_I2S_BASE			EP93XX_APB_IOMEM(0x00020000)

#define EP93XX_SECURITY_BASE		EP93XX_APB_IOMEM(0x00030000)

#define EP93XX_GPIO_BASE		EP93XX_APB_IOMEM(0x00040000)
#define EP93XX_GPIO_REG(x)		(EP93XX_GPIO_BASE + (x))
#define EP93XX_GPIO_F_INT_TYPE1		EP93XX_GPIO_REG(0x4c)
#define EP93XX_GPIO_F_INT_TYPE2		EP93XX_GPIO_REG(0x50)
#define EP93XX_GPIO_F_INT_ACK		EP93XX_GPIO_REG(0x54)
#define EP93XX_GPIO_F_INT_ENABLE	EP93XX_GPIO_REG(0x58)
#define EP93XX_GPIO_F_INT_STATUS	EP93XX_GPIO_REG(0x5c)
#define EP93XX_GPIO_A_INT_TYPE1		EP93XX_GPIO_REG(0x90)
#define EP93XX_GPIO_A_INT_TYPE2		EP93XX_GPIO_REG(0x94)
#define EP93XX_GPIO_A_INT_ACK		EP93XX_GPIO_REG(0x98)
#define EP93XX_GPIO_A_INT_ENABLE	EP93XX_GPIO_REG(0x9c)
#define EP93XX_GPIO_A_INT_STATUS	EP93XX_GPIO_REG(0xa0)
#define EP93XX_GPIO_B_INT_TYPE1		EP93XX_GPIO_REG(0xac)
#define EP93XX_GPIO_B_INT_TYPE2		EP93XX_GPIO_REG(0xb0)
#define EP93XX_GPIO_B_INT_ACK		EP93XX_GPIO_REG(0xb4)
#define EP93XX_GPIO_B_INT_ENABLE	EP93XX_GPIO_REG(0xb8)
#define EP93XX_GPIO_B_INT_STATUS	EP93XX_GPIO_REG(0xbc)

#define EP93XX_AAC_BASE			EP93XX_APB_IOMEM(0x00080000)

#define EP93XX_SPI_BASE			EP93XX_APB_IOMEM(0x000a0000)

#define EP93XX_IRDA_BASE		EP93XX_APB_IOMEM(0x000b0000)

#define EP93XX_UART1_PHYS_BASE		(EP93XX_APB_PHYS_BASE + 0x000c0000)
#define EP93XX_UART1_BASE		EP93XX_APB_IOMEM(0x000c0000)

#define EP93XX_UART2_PHYS_BASE		(EP93XX_APB_PHYS_BASE + 0x000d0000)
#define EP93XX_UART2_BASE		EP93XX_APB_IOMEM(0x000d0000)

#define EP93XX_UART3_PHYS_BASE		(EP93XX_APB_PHYS_BASE + 0x000e0000)
#define EP93XX_UART3_BASE		EP93XX_APB_IOMEM(0x000e0000)

#define EP93XX_KEY_MATRIX_BASE		EP93XX_APB_IOMEM(0x000f0000)

#define EP93XX_ADC_BASE			EP93XX_APB_IOMEM(0x00100000)
#define EP93XX_TOUCHSCREEN_BASE		EP93XX_APB_IOMEM(0x00100000)

#define EP93XX_PWM_PHYS_BASE		(EP93XX_APB_PHYS_BASE + 0x00110000)
#define EP93XX_PWM_BASE			EP93XX_APB_IOMEM(0x00110000)

#define EP93XX_RTC_PHYS_BASE		(EP93XX_APB_PHYS_BASE + 0x00120000)
#define EP93XX_RTC_BASE			EP93XX_APB_IOMEM(0x00120000)

#define EP93XX_SYSCON_BASE		EP93XX_APB_IOMEM(0x00130000)
#define EP93XX_SYSCON_REG(x)		(EP93XX_SYSCON_BASE + (x))
#define EP93XX_SYSCON_POWER_STATE	EP93XX_SYSCON_REG(0x00)
#define EP93XX_SYSCON_PWRCNT		EP93XX_SYSCON_REG(0x04)
#define EP93XX_SYSCON_PWRCNT_FIR_EN	(1<<31)
#define EP93XX_SYSCON_PWRCNT_UARTBAUD	(1<<29)
#define EP93XX_SYSCON_PWRCNT_USH_EN	(1<<28)
#define EP93XX_SYSCON_PWRCNT_DMA_M2M1	(1<<27)
#define EP93XX_SYSCON_PWRCNT_DMA_M2M0	(1<<26)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P8	(1<<25)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P9	(1<<24)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P6	(1<<23)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P7	(1<<22)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P4	(1<<21)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P5	(1<<20)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P2	(1<<19)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P3	(1<<18)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P0	(1<<17)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P1	(1<<16)
#define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)
#define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)
#define EP93XX_SYSCON_CLOCK_SET1	EP93XX_SYSCON_REG(0x20)
#define EP93XX_SYSCON_CLOCK_SET2	EP93XX_SYSCON_REG(0x24)
#define EP93XX_SYSCON_DEVCFG		EP93XX_SYSCON_REG(0x80)
#define EP93XX_SYSCON_DEVCFG_SWRST	(1<<31)
#define EP93XX_SYSCON_DEVCFG_D1ONG	(1<<30)
#define EP93XX_SYSCON_DEVCFG_D0ONG	(1<<29)
#define EP93XX_SYSCON_DEVCFG_IONU2	(1<<28)
#define EP93XX_SYSCON_DEVCFG_GONK	(1<<27)
#define EP93XX_SYSCON_DEVCFG_TONG	(1<<26)
#define EP93XX_SYSCON_DEVCFG_MONG	(1<<25)
#define EP93XX_SYSCON_DEVCFG_U3EN	(1<<24)
#define EP93XX_SYSCON_DEVCFG_CPENA	(1<<23)
#define EP93XX_SYSCON_DEVCFG_A2ONG	(1<<22)
#define EP93XX_SYSCON_DEVCFG_A1ONG	(1<<21)
#define EP93XX_SYSCON_DEVCFG_U2EN	(1<<20)
#define EP93XX_SYSCON_DEVCFG_EXVC	(1<<19)
#define EP93XX_SYSCON_DEVCFG_U1EN	(1<<18)
#define EP93XX_SYSCON_DEVCFG_TIN	(1<<17)
#define EP93XX_SYSCON_DEVCFG_HC3IN	(1<<15)
#define EP93XX_SYSCON_DEVCFG_HC3EN	(1<<14)
#define EP93XX_SYSCON_DEVCFG_HC1IN	(1<<13)
#define EP93XX_SYSCON_DEVCFG_HC1EN	(1<<12)
#define EP93XX_SYSCON_DEVCFG_HONIDE	(1<<11)
#define EP93XX_SYSCON_DEVCFG_GONIDE	(1<<10)
#define EP93XX_SYSCON_DEVCFG_PONG	(1<<9)
#define EP93XX_SYSCON_DEVCFG_EONIDE	(1<<8)
#define EP93XX_SYSCON_DEVCFG_I2SONSSP	(1<<7)
#define EP93XX_SYSCON_DEVCFG_I2SONAC97	(1<<6)
#define EP93XX_SYSCON_DEVCFG_RASONP3	(1<<4)
#define EP93XX_SYSCON_DEVCFG_RAS	(1<<3)
#define EP93XX_SYSCON_DEVCFG_ADCPD	(1<<2)
#define EP93XX_SYSCON_DEVCFG_KEYS	(1<<1)
#define EP93XX_SYSCON_DEVCFG_SHENA	(1<<0)
#define EP93XX_SYSCON_KEYTCHCLKDIV	EP93XX_SYSCON_REG(0x90)
#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN	(1<<31)
#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	(1<<16)
#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN	(1<<15)
#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV	(1<<0)
#define EP93XX_SYSCON_SWLOCK		EP93XX_SYSCON_REG(0xc0)

#define EP93XX_WATCHDOG_BASE		EP93XX_APB_IOMEM(0x00140000)


#endif
Commit	Line	Data
e7736d47	1	/*
a09e64fb	2	* arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
e7736d47 LB	3	*/
	4
	5	#ifndef __ASM_ARCH_EP93XX_REGS_H
	6	#define __ASM_ARCH_EP93XX_REGS_H
	7
446b097a HS	8	/*
	9	* EP93xx Physical Memory Map:
	10	*
	11	* The ASDO pin is sampled at system reset to select a synchronous or
	12	* asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up)
	13	* the synchronous boot mode is selected. When ASDO is "0" (i.e
	14	* pulled-down) the asynchronous boot mode is selected.
	15	*
	16	* In synchronous boot mode nSDCE3 is decoded starting at physical address
	17	* 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
	18	* boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
	19	* decoded at 0xf0000000.
	20	*
	21	* There is known errata for the EP93xx dealing with External Memory
	22	* Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design
	23	* Guidelines" for more information. This document can be found at:
	24	*
	25	* http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
	26	*/
	27
	28	#define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
	29	#define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
	30	#define EP93XX_CS1_PHYS_BASE 0x10000000
	31	#define EP93XX_CS2_PHYS_BASE 0x20000000
	32	#define EP93XX_CS3_PHYS_BASE 0x30000000
	33	#define EP93XX_PCMCIA_PHYS_BASE 0x40000000
	34	#define EP93XX_CS6_PHYS_BASE 0x60000000
	35	#define EP93XX_CS7_PHYS_BASE 0x70000000
	36	#define EP93XX_SDCE0_PHYS_BASE 0xc0000000
	37	#define EP93XX_SDCE1_PHYS_BASE 0xd0000000
	38	#define EP93XX_SDCE2_PHYS_BASE 0xe0000000
	39	#define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */
	40	#define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */
	41
e7736d47 LB	42	/*
	43	* EP93xx linux memory map:
	44	*
	45	* virt phys size
	46	* fe800000 5M per-platform mappings
	47	* fed00000 80800000 2M APB
	48	* fef00000 80000000 1M AHB
	49	*/
	50
	51	#define EP93XX_AHB_PHYS_BASE 0x80000000
	52	#define EP93XX_AHB_VIRT_BASE 0xfef00000
	53	#define EP93XX_AHB_SIZE 0x00100000
	54
702b59e6 HS	55	#define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x))
702b59e6 HS	56
e7736d47 LB	57	#define EP93XX_APB_PHYS_BASE 0x80800000
	58	#define EP93XX_APB_VIRT_BASE 0xfed00000
	59	#define EP93XX_APB_SIZE 0x00200000
	60
702b59e6 HS	61	#define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x))
702b59e6 HS	62
e7736d47 LB	63
e7736d47 LB	64	/* AHB peripherals */
702b59e6	65	#define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000)
e7736d47	66
1d22e05d	67	#define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000)
702b59e6	68	#define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000)
e7736d47	69
e7736d47	70	#define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000)
702b59e6	71	#define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000)
e7736d47	72
702b59e6	73	#define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000)
e7736d47	74
702b59e6	75	#define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000)
e7736d47	76
702b59e6	77	#define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000)
e7736d47	78
702b59e6	79	#define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000)
e7736d47	80
702b59e6	81	#define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
e7736d47	82
702b59e6	83	#define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
e7736d47	84
702b59e6	85	#define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
e7736d47	86
702b59e6	87	#define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000)
e7736d47 LB	88
	89
	90	/* APB peripherals */
702b59e6	91	#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
e7736d47 LB	92	#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
	93	#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
	94	#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
	95	#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
	96	#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
	97	#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
	98	#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
	99	#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
	100	#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
	101	#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
	102	#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
	103	#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
	104	#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
	105	#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
	106	#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
	107
702b59e6	108	#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
e7736d47	109
702b59e6	110	#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
e7736d47	111
702b59e6	112	#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000)
a8e19667	113	#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
4932e397 LB	114	#define EP93XX_GPIO_F_INT_TYPE1 EP93XX_GPIO_REG(0x4c)
	115	#define EP93XX_GPIO_F_INT_TYPE2 EP93XX_GPIO_REG(0x50)
	116	#define EP93XX_GPIO_F_INT_ACK EP93XX_GPIO_REG(0x54)
	117	#define EP93XX_GPIO_F_INT_ENABLE EP93XX_GPIO_REG(0x58)
	118	#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c)
bd20ff57 LB	119	#define EP93XX_GPIO_A_INT_TYPE1 EP93XX_GPIO_REG(0x90)
	120	#define EP93XX_GPIO_A_INT_TYPE2 EP93XX_GPIO_REG(0x94)
	121	#define EP93XX_GPIO_A_INT_ACK EP93XX_GPIO_REG(0x98)
	122	#define EP93XX_GPIO_A_INT_ENABLE EP93XX_GPIO_REG(0x9c)
	123	#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0)
	124	#define EP93XX_GPIO_B_INT_TYPE1 EP93XX_GPIO_REG(0xac)
	125	#define EP93XX_GPIO_B_INT_TYPE2 EP93XX_GPIO_REG(0xb0)
	126	#define EP93XX_GPIO_B_INT_ACK EP93XX_GPIO_REG(0xb4)
	127	#define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8)
	128	#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc)
e7736d47	129
702b59e6	130	#define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
e7736d47	131
702b59e6	132	#define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000)
e7736d47	133
702b59e6	134	#define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000)
e7736d47	135
e7736d47	136	#define EP93XX_UART1_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000c0000)
702b59e6	137	#define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000)
e7736d47	138
e7736d47	139	#define EP93XX_UART2_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000d0000)
702b59e6	140	#define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000)
e7736d47	141
e7736d47	142	#define EP93XX_UART3_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000e0000)
702b59e6	143	#define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000)
e7736d47	144
702b59e6	145	#define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
e7736d47	146
702b59e6 HS	147	#define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
702b59e6 HS	148	#define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
e7736d47	149
ef12379f	150	#define EP93XX_PWM_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x00110000)
702b59e6	151	#define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000)
e7736d47	152
38f7b009	153	#define EP93XX_RTC_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x00120000)
702b59e6	154	#define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000)
e7736d47	155
702b59e6	156	#define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000)
e7736d47 LB	157	#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
e7736d47 LB	158	#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
40702432 HS	159	#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
	160	#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
	161	#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
	162	#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
	163	#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
	164	#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
	165	#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
	166	#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
	167	#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
	168	#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
	169	#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
	170	#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
	171	#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
	172	#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
	173	#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
	174	#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
e7736d47 LB	175	#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
e7736d47 LB	176	#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
1d81eedb LB	177	#define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20)
1d81eedb LB	178	#define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24)
02239f0a HS	179	#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
	180	#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
	181	#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
	182	#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
	183	#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
	184	#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
	185	#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
	186	#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
	187	#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
	188	#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
	189	#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
	190	#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
	191	#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
	192	#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
	193	#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
	194	#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
	195	#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
	196	#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
	197	#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
	198	#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
	199	#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
	200	#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
	201	#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
	202	#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
	203	#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
	204	#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
	205	#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
	206	#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
	207	#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
	208	#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
	209	#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
5d43f11b HS	210	#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
	211	#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
	212	#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
	213	#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
	214	#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
e7736d47 LB	215	#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
e7736d47 LB	216
702b59e6	217	#define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
e7736d47 LB	218
	219
	220	#endif