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ARM: delete struct sys_timer
[deliverable/linux.git] / arch / arm / mach-exynos / common.c
CommitLineData
cc511b8d
KK		 1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
7affca35 16#include <linux/device.h>
cc511b8d
KK		 17#include <linux/gpio.h>
18#include <linux/sched.h>
19#include <linux/serial_core.h>
237c78be 20#include <linux/of.h>
5b7897db 21#include <linux/of_fdt.h>
237c78be 22#include <linux/of_irq.h>
1e60bc0b
TA		 23#include <linux/export.h>
24#include <linux/irqdomain.h>
e873a47c 25#include <linux/of_address.h>
cc511b8d
KK		 26
27#include <asm/proc-fns.h>
40ba95fd 28#include <asm/exception.h>
cc511b8d
KK		 29#include <asm/hardware/cache-l2x0.h>
30#include <asm/hardware/gic.h>
31#include <asm/mach/map.h>
32#include <asm/mach/irq.h>
b756a50f 33#include <asm/cacheflush.h>
cc511b8d
KK		 34
35#include <mach/regs-irq.h>
36#include <mach/regs-pmu.h>
37#include <mach/regs-gpio.h>
b756a50f 38#include <mach/pmu.h>
cc511b8d
KK		 39
40#include <plat/cpu.h>
41#include <plat/clock.h>
42#include <plat/devs.h>
43#include <plat/pm.h>
cc511b8d
KK		 44#include <plat/sdhci.h>
45#include <plat/gpio-cfg.h>
46#include <plat/adc-core.h>
47#include <plat/fb-core.h>
48#include <plat/fimc-core.h>
49#include <plat/iic-core.h>
50#include <plat/tv-core.h>
308b3afb 51#include <plat/spi-core.h>
cc511b8d
KK		 52#include <plat/regs-serial.h>
53
54#include "common.h"
6cdeddcc
ADK		 55#define L2_AUX_VAL 0x7C470001
56#define L2_AUX_MASK 0xC200ffff
cc511b8d 57
cc511b8d
KK		 58static const char name_exynos4210[] = "EXYNOS4210";
59static const char name_exynos4212[] = "EXYNOS4212";
60static const char name_exynos4412[] = "EXYNOS4412";
94c7ca71 61static const char name_exynos5250[] = "EXYNOS5250";
2edb36c4 62static const char name_exynos5440[] = "EXYNOS5440";
cc511b8d 63
906c789c 64static void exynos4_map_io(void);
94c7ca71 65static void exynos5_map_io(void);
2edb36c4 66static void exynos5440_map_io(void);
906c789c 67static void exynos4_init_clocks(int xtal);
94c7ca71 68static void exynos5_init_clocks(int xtal);
55b6ef7a 69static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
906c789c 70static int exynos_init(void);
cc511b8d
KK		 71
72static struct cpu_table cpu_ids[] __initdata = {
73 {
74 .idcode = EXYNOS4210_CPU_ID,
75 .idmask = EXYNOS4_CPU_MASK,
76 .map_io = exynos4_map_io,
77 .init_clocks = exynos4_init_clocks,
55b6ef7a 78 .init_uarts = exynos4_init_uarts,
cc511b8d
KK		 79 .init = exynos_init,
80 .name = name_exynos4210,
81 }, {
82 .idcode = EXYNOS4212_CPU_ID,
83 .idmask = EXYNOS4_CPU_MASK,
84 .map_io = exynos4_map_io,
85 .init_clocks = exynos4_init_clocks,
55b6ef7a 86 .init_uarts = exynos4_init_uarts,
cc511b8d
KK		 87 .init = exynos_init,
88 .name = name_exynos4212,
89 }, {
90 .idcode = EXYNOS4412_CPU_ID,
91 .idmask = EXYNOS4_CPU_MASK,
92 .map_io = exynos4_map_io,
93 .init_clocks = exynos4_init_clocks,
55b6ef7a 94 .init_uarts = exynos4_init_uarts,
cc511b8d
KK		 95 .init = exynos_init,
96 .name = name_exynos4412,
94c7ca71
KK		 97 }, {
98 .idcode = EXYNOS5250_SOC_ID,
99 .idmask = EXYNOS5_SOC_MASK,
100 .map_io = exynos5_map_io,
101 .init_clocks = exynos5_init_clocks,
94c7ca71
KK		 102 .init = exynos_init,
103 .name = name_exynos5250,
2edb36c4
KK		 104 }, {
105 .idcode = EXYNOS5440_SOC_ID,
106 .idmask = EXYNOS5_SOC_MASK,
107 .map_io = exynos5440_map_io,
108 .init = exynos_init,
109 .name = name_exynos5440,
cc511b8d
KK		 110 },
111};
112
113/* Initial IO mappings */
114
115static struct map_desc exynos_iodesc[] __initdata = {
116 {
117 .virtual = (unsigned long)S5P_VA_CHIPID,
94c7ca71 118 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
cc511b8d
KK		 119 .length = SZ_4K,
120 .type = MT_DEVICE,
94c7ca71
KK		 121 },
122};
123
5b7897db 124#ifdef CONFIG_ARCH_EXYNOS5
2edb36c4
KK		 125static struct map_desc exynos5440_iodesc[] __initdata = {
126 {
127 .virtual = (unsigned long)S5P_VA_CHIPID,
128 .pfn = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
129 .length = SZ_4K,
130 .type = MT_DEVICE,
131 },
132};
5b7897db 133#endif
2edb36c4 134
94c7ca71
KK		 135static struct map_desc exynos4_iodesc[] __initdata = {
136 {
cc511b8d
KK		 137 .virtual = (unsigned long)S3C_VA_SYS,
138 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
139 .length = SZ_64K,
140 .type = MT_DEVICE,
141 }, {
142 .virtual = (unsigned long)S3C_VA_TIMER,
143 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
144 .length = SZ_16K,
145 .type = MT_DEVICE,
146 }, {
147 .virtual = (unsigned long)S3C_VA_WATCHDOG,
148 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
149 .length = SZ_4K,
150 .type = MT_DEVICE,
151 }, {
152 .virtual = (unsigned long)S5P_VA_SROMC,
153 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
154 .length = SZ_4K,
155 .type = MT_DEVICE,
156 }, {
157 .virtual = (unsigned long)S5P_VA_SYSTIMER,
158 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
159 .length = SZ_4K,
160 .type = MT_DEVICE,
161 }, {
162 .virtual = (unsigned long)S5P_VA_PMU,
163 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
164 .length = SZ_64K,
165 .type = MT_DEVICE,
166 }, {
167 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
168 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
169 .length = SZ_4K,
170 .type = MT_DEVICE,
171 }, {
172 .virtual = (unsigned long)S5P_VA_GIC_CPU,
173 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
174 .length = SZ_64K,
175 .type = MT_DEVICE,
176 }, {
177 .virtual = (unsigned long)S5P_VA_GIC_DIST,
178 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
179 .length = SZ_64K,
180 .type = MT_DEVICE,
181 }, {
182 .virtual = (unsigned long)S3C_VA_UART,
183 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
184 .length = SZ_512K,
185 .type = MT_DEVICE,
94c7ca71 186 }, {
cc511b8d
KK		 187 .virtual = (unsigned long)S5P_VA_CMU,
188 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
189 .length = SZ_128K,
190 .type = MT_DEVICE,
191 }, {
192 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
193 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
194 .length = SZ_8K,
195 .type = MT_DEVICE,
196 }, {
197 .virtual = (unsigned long)S5P_VA_L2CC,
198 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
199 .length = SZ_4K,
200 .type = MT_DEVICE,
cc511b8d
KK		 201 }, {
202 .virtual = (unsigned long)S5P_VA_DMC0,
203 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
2bde0b08
MH		 204 .length = SZ_64K,
205 .type = MT_DEVICE,
206 }, {
207 .virtual = (unsigned long)S5P_VA_DMC1,
208 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
209 .length = SZ_64K,
cc511b8d 210 .type = MT_DEVICE,
cc511b8d
KK		 211 }, {
212 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
213 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
214 .length = SZ_4K,
215 .type = MT_DEVICE,
216 },
217};
218
219static struct map_desc exynos4_iodesc0[] __initdata = {
220 {
221 .virtual = (unsigned long)S5P_VA_SYSRAM,
222 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
223 .length = SZ_4K,
224 .type = MT_DEVICE,
225 },
226};
227
228static struct map_desc exynos4_iodesc1[] __initdata = {
229 {
230 .virtual = (unsigned long)S5P_VA_SYSRAM,
231 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
232 .length = SZ_4K,
233 .type = MT_DEVICE,
234 },
235};
236
94c7ca71
KK		 237static struct map_desc exynos5_iodesc[] __initdata = {
238 {
239 .virtual = (unsigned long)S3C_VA_SYS,
240 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
241 .length = SZ_64K,
242 .type = MT_DEVICE,
243 }, {
244 .virtual = (unsigned long)S3C_VA_TIMER,
245 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
246 .length = SZ_16K,
247 .type = MT_DEVICE,
248 }, {
249 .virtual = (unsigned long)S3C_VA_WATCHDOG,
250 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
251 .length = SZ_4K,
252 .type = MT_DEVICE,
253 }, {
254 .virtual = (unsigned long)S5P_VA_SROMC,
255 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
256 .length = SZ_4K,
257 .type = MT_DEVICE,
258 }, {
259 .virtual = (unsigned long)S5P_VA_SYSTIMER,
260 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
261 .length = SZ_4K,
262 .type = MT_DEVICE,
263 }, {
264 .virtual = (unsigned long)S5P_VA_SYSRAM,
265 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
266 .length = SZ_4K,
267 .type = MT_DEVICE,
268 }, {
269 .virtual = (unsigned long)S5P_VA_CMU,
270 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
271 .length = 144 * SZ_1K,
272 .type = MT_DEVICE,
273 }, {
274 .virtual = (unsigned long)S5P_VA_PMU,
275 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
276 .length = SZ_64K,
277 .type = MT_DEVICE,
94c7ca71
KK		 278 }, {
279 .virtual = (unsigned long)S3C_VA_UART,
280 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
281 .length = SZ_512K,
282 .type = MT_DEVICE,
94c7ca71
KK		 283 },
284};
285
2edb36c4
KK		 286static struct map_desc exynos5440_iodesc0[] __initdata = {
287 {
288 .virtual = (unsigned long)S3C_VA_UART,
289 .pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
290 .length = SZ_512K,
291 .type = MT_DEVICE,
292 },
293};
294
9eb48595 295void exynos4_restart(char mode, const char *cmd)
cc511b8d
KK		 296{
297 __raw_writel(0x1, S5P_SWRESET);
298}
299
94c7ca71
KK		 300void exynos5_restart(char mode, const char *cmd)
301{
2edb36c4
KK		 302 u32 val;
303 void __iomem *addr;
304
305 if (of_machine_is_compatible("samsung,exynos5250")) {
306 val = 0x1;
307 addr = EXYNOS_SWRESET;
308 } else if (of_machine_is_compatible("samsung,exynos5440")) {
309 val = (0x10 << 20) | (0x1 << 16);
310 addr = EXYNOS5440_SWRESET;
311 } else {
312 pr_err("%s: cannot support non-DT\n", __func__);
313 return;
314 }
315
316 __raw_writel(val, addr);
94c7ca71
KK		 317}
318
bb13fabc
SG		 319void __init exynos_init_late(void)
320{
2edb36c4
KK		 321 if (of_machine_is_compatible("samsung,exynos5440"))
322 /* to be supported later */
323 return;
324
bb13fabc
SG		 325 exynos_pm_late_initcall();
326}
327
cc511b8d
KK		 328/*
329 * exynos_map_io
330 *
331 * register the standard cpu IO areas
332 */
333
334void __init exynos_init_io(struct map_desc *mach_desc, int size)
335{
5b7897db
DA		 336 struct map_desc *iodesc = exynos_iodesc;
337 int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
338#if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
339 unsigned long root = of_get_flat_dt_root();
340
cc511b8d 341 /* initialize the io descriptors we need for initialization */
5b7897db
DA		 342 if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
343 iodesc = exynos5440_iodesc;
344 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
345 }
346#endif
347
348 iotable_init(iodesc, iodesc_sz);
2edb36c4 349
cc511b8d
KK		 350 if (mach_desc)
351 iotable_init(mach_desc, size);
352
353 /* detect cpu id and rev. */
354 s5p_init_cpu(S5P_VA_CHIPID);
355
356 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
357}
358
906c789c 359static void __init exynos4_map_io(void)
cc511b8d
KK		 360{
361 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
362
363 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
364 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
365 else
366 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
367
368 /* initialize device information early */
369 exynos4_default_sdhci0();
370 exynos4_default_sdhci1();
371 exynos4_default_sdhci2();
372 exynos4_default_sdhci3();
373
374 s3c_adc_setname("samsung-adc-v3");
375
376 s3c_fimc_setname(0, "exynos4-fimc");
377 s3c_fimc_setname(1, "exynos4-fimc");
378 s3c_fimc_setname(2, "exynos4-fimc");
379 s3c_fimc_setname(3, "exynos4-fimc");
380
8482c81c
TA		 381 s3c_sdhci_setname(0, "exynos4-sdhci");
382 s3c_sdhci_setname(1, "exynos4-sdhci");
383 s3c_sdhci_setname(2, "exynos4-sdhci");
384 s3c_sdhci_setname(3, "exynos4-sdhci");
385
cc511b8d
KK		 386 /* The I2C bus controllers are directly compatible with s3c2440 */
387 s3c_i2c0_setname("s3c2440-i2c");
388 s3c_i2c1_setname("s3c2440-i2c");
389 s3c_i2c2_setname("s3c2440-i2c");
390
391 s5p_fb_setname(0, "exynos4-fb");
392 s5p_hdmi_setname("exynos4-hdmi");
308b3afb
HS		 393
394 s3c64xx_spi_setname("exynos4210-spi");
cc511b8d
KK		 395}
396
94c7ca71
KK		 397static void __init exynos5_map_io(void)
398{
399 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
94c7ca71
KK		 400}
401
906c789c 402static void __init exynos4_init_clocks(int xtal)
cc511b8d
KK		 403{
404 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
405
406 s3c24xx_register_baseclocks(xtal);
407 s5p_register_clocks(xtal);
408
409 if (soc_is_exynos4210())
410 exynos4210_register_clocks();
411 else if (soc_is_exynos4212() || soc_is_exynos4412())
412 exynos4212_register_clocks();
413
414 exynos4_register_clocks();
415 exynos4_setup_clocks();
416}
417
2edb36c4
KK		 418static void __init exynos5440_map_io(void)
419{
420 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
421}
422
94c7ca71
KK		 423static void __init exynos5_init_clocks(int xtal)
424{
425 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
426
427 s3c24xx_register_baseclocks(xtal);
428 s5p_register_clocks(xtal);
429
430 exynos5_register_clocks();
431 exynos5_setup_clocks();
432}
433
cc511b8d
KK		 434#define COMBINER_ENABLE_SET 0x0
435#define COMBINER_ENABLE_CLEAR 0x4
436#define COMBINER_INT_STATUS 0xC
437
438static DEFINE_SPINLOCK(irq_controller_lock);
439
440struct combiner_chip_data {
441 unsigned int irq_offset;
442 unsigned int irq_mask;
443 void __iomem *base;
444};
445
1e60bc0b 446static struct irq_domain *combiner_irq_domain;
cc511b8d
KK		 447static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
448
449static inline void __iomem *combiner_base(struct irq_data *data)
450{
451 struct combiner_chip_data *combiner_data =
452 irq_data_get_irq_chip_data(data);
453
454 return combiner_data->base;
455}
456
457static void combiner_mask_irq(struct irq_data *data)
458{
1e60bc0b 459 u32 mask = 1 << (data->hwirq % 32);
cc511b8d
KK		 460
461 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
462}
463
464static void combiner_unmask_irq(struct irq_data *data)
465{
1e60bc0b 466 u32 mask = 1 << (data->hwirq % 32);
cc511b8d
KK		 467
468 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
469}
470
471static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
472{
473 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
474 struct irq_chip *chip = irq_get_chip(irq);
475 unsigned int cascade_irq, combiner_irq;
476 unsigned long status;
477
478 chained_irq_enter(chip, desc);
479
480 spin_lock(&irq_controller_lock);
481 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
482 spin_unlock(&irq_controller_lock);
483 status &= chip_data->irq_mask;
484
485 if (status == 0)
486 goto out;
487
488 combiner_irq = __ffs(status);
489
490 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
491 if (unlikely(cascade_irq >= NR_IRQS))
492 do_bad_IRQ(cascade_irq, desc);
493 else
494 generic_handle_irq(cascade_irq);
495
496 out:
497 chained_irq_exit(chip, desc);
498}
499
500static struct irq_chip combiner_chip = {
501 .name = "COMBINER",
502 .irq_mask = combiner_mask_irq,
503 .irq_unmask = combiner_unmask_irq,
504};
505
506static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
507{
bb19a751
KK		 508 unsigned int max_nr;
509
510 if (soc_is_exynos5250())
511 max_nr = EXYNOS5_MAX_COMBINER_NR;
512 else
513 max_nr = EXYNOS4_MAX_COMBINER_NR;
514
515 if (combiner_nr >= max_nr)
cc511b8d
KK		 516 BUG();
517 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
518 BUG();
519 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
520}
521
1e60bc0b
TA		 522static void __init combiner_init_one(unsigned int combiner_nr,
523 void __iomem *base)
cc511b8d 524{
cc511b8d 525 combiner_data[combiner_nr].base = base;
1e60bc0b
TA		 526 combiner_data[combiner_nr].irq_offset = irq_find_mapping(
527 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
cc511b8d
KK		 528 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
529
530 /* Disable all interrupts */
cc511b8d
KK		 531 __raw_writel(combiner_data[combiner_nr].irq_mask,
532 base + COMBINER_ENABLE_CLEAR);
1e60bc0b 533}
cc511b8d 534
e873a47c
TA		 535#ifdef CONFIG_OF
536static int combiner_irq_domain_xlate(struct irq_domain *d,
537 struct device_node *controller,
538 const u32 *intspec, unsigned int intsize,
539 unsigned long *out_hwirq,
540 unsigned int *out_type)
541{
542 if (d->of_node != controller)
543 return -EINVAL;
544
545 if (intsize < 2)
546 return -EINVAL;
547
548 *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
549 *out_type = 0;
550
551 return 0;
552}
553#else
554static int combiner_irq_domain_xlate(struct irq_domain *d,
555 struct device_node *controller,
556 const u32 *intspec, unsigned int intsize,
557 unsigned long *out_hwirq,
558 unsigned int *out_type)
559{
560 return -EINVAL;
561}
562#endif
563
1e60bc0b
TA		 564static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
565 irq_hw_number_t hw)
566{
567 irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
568 irq_set_chip_data(irq, &combiner_data[hw >> 3]);
569 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
570
571 return 0;
572}
cc511b8d 573
1e60bc0b 574static struct irq_domain_ops combiner_irq_domain_ops = {
e873a47c 575 .xlate = combiner_irq_domain_xlate,
1e60bc0b
TA		 576 .map = combiner_irq_domain_map,
577};
578
2a2b0e20
SK		 579static void __init combiner_init(void __iomem *combiner_base,
580 struct device_node *np)
1e60bc0b 581{
e873a47c 582 int i, irq, irq_base;
1e60bc0b
TA		 583 unsigned int max_nr, nr_irq;
584
e873a47c
TA		 585 if (np) {
586 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
587 pr_warning("%s: number of combiners not specified, "
588 "setting default as %d.\n",
589 __func__, EXYNOS4_MAX_COMBINER_NR);
590 max_nr = EXYNOS4_MAX_COMBINER_NR;
591 }
592 } else {
593 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
594 EXYNOS4_MAX_COMBINER_NR;
595 }
1e60bc0b
TA		 596 nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
597
598 irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
599 if (IS_ERR_VALUE(irq_base)) {
600 irq_base = COMBINER_IRQ(0, 0);
601 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
602 }
603
604 combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
605 &combiner_irq_domain_ops, &combiner_data);
606 if (WARN_ON(!combiner_irq_domain)) {
607 pr_warning("%s: irq domain init failed\n", __func__);
608 return;
609 }
610
611 for (i = 0; i < max_nr; i++) {
612 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
820f3dd7
AB		 613 irq = IRQ_SPI(i);
614#ifdef CONFIG_OF
615 if (np)
616 irq = irq_of_parse_and_map(np, i);
617#endif
e873a47c 618 combiner_cascade_irq(i, irq);
cc511b8d
KK		 619 }
620}
621
237c78be 622#ifdef CONFIG_OF
96046ea3
SK		 623static int __init combiner_of_init(struct device_node *np,
624 struct device_node *parent)
e873a47c
TA		 625{
626 void __iomem *combiner_base;
627
628 combiner_base = of_iomap(np, 0);
629 if (!combiner_base) {
630 pr_err("%s: failed to map combiner registers\n", __func__);
631 return -ENXIO;
632 }
633
634 combiner_init(combiner_base, np);
635
636 return 0;
637}
638
2edb36c4 639static const struct of_device_id exynos_dt_irq_match[] = {
237c78be 640 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
2edb36c4 641 { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
e873a47c
TA		 642 { .compatible = "samsung,exynos4210-combiner",
643 .data = combiner_of_init, },
237c78be
AB		 644 {},
645};
646#endif
cc511b8d
KK		 647
648void __init exynos4_init_irq(void)
649{
40ba95fd 650 unsigned int gic_bank_offset;
cc511b8d
KK		 651
652 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
653
237c78be 654 if (!of_have_populated_dt())
75294957 655 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
237c78be
AB		 656#ifdef CONFIG_OF
657 else
2edb36c4 658 of_irq_init(exynos_dt_irq_match);
237c78be 659#endif
cc511b8d 660
e873a47c
TA		 661 if (!of_have_populated_dt())
662 combiner_init(S5P_VA_COMBINER_BASE, NULL);
cc511b8d
KK		 663
664 /*
665 * The parameters of s5p_init_irq() are for VIC init.
666 * Theses parameters should be NULL and 0 because EXYNOS4
667 * uses GIC instead of VIC.
668 */
669 s5p_init_irq(NULL, 0);
670}
671
94c7ca71
KK		 672void __init exynos5_init_irq(void)
673{
6fff5a11 674#ifdef CONFIG_OF
2edb36c4 675 of_irq_init(exynos_dt_irq_match);
6fff5a11 676#endif
cc511b8d
KK		 677 /*
678 * The parameters of s5p_init_irq() are for VIC init.
679 * Theses parameters should be NULL and 0 because EXYNOS4
680 * uses GIC instead of VIC.
681 */
12fee194
KK		 682 if (!of_machine_is_compatible("samsung,exynos5440"))
683 s5p_init_irq(NULL, 0);
3445513c
IS		 684
685 gic_arch_extn.irq_set_wake = s3c_irq_wake;
cc511b8d
KK		 686}
687
9ee6af9c
TA		 688struct bus_type exynos_subsys = {
689 .name = "exynos-core",
690 .dev_name = "exynos-core",
94c7ca71
KK		 691};
692
7affca35 693static struct device exynos4_dev = {
9ee6af9c 694 .bus = &exynos_subsys,
94c7ca71
KK		 695};
696
697static int __init exynos_core_init(void)
cc511b8d 698{
9ee6af9c 699 return subsys_system_register(&exynos_subsys, NULL);
cc511b8d 700}
94c7ca71 701core_initcall(exynos_core_init);
cc511b8d
KK		 702
703#ifdef CONFIG_CACHE_L2X0
704static int __init exynos4_l2x0_cache_init(void)
705{
e1b1994e
IH		 706 int ret;
707
2edb36c4 708 if (soc_is_exynos5250() || soc_is_exynos5440())
94c7ca71
KK		 709 return 0;
710
6cdeddcc
ADK		 711 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
712 if (!ret) {
713 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
714 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
715 return 0;
716 }
cc511b8d 717
b756a50f
ADK		 718 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
719 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
720 /* TAG, Data Latency Control: 2 cycles */
721 l2x0_saved_regs.tag_latency = 0x110;
cc511b8d 722
b756a50f
ADK		 723 if (soc_is_exynos4212() || soc_is_exynos4412())
724 l2x0_saved_regs.data_latency = 0x120;
725 else
726 l2x0_saved_regs.data_latency = 0x110;
727
728 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
729 l2x0_saved_regs.pwr_ctrl =
730 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
cc511b8d 731
b756a50f 732 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
cc511b8d 733
b756a50f
ADK		 734 __raw_writel(l2x0_saved_regs.tag_latency,
735 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
736 __raw_writel(l2x0_saved_regs.data_latency,
737 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
cc511b8d 738
b756a50f
ADK		 739 /* L2X0 Prefetch Control */
740 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
741 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
742
743 /* L2X0 Power Control */
744 __raw_writel(l2x0_saved_regs.pwr_ctrl,
745 S5P_VA_L2CC + L2X0_POWER_CTRL);
746
747 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
748 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
749 }
cc511b8d 750
6cdeddcc 751 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
cc511b8d
KK		 752 return 0;
753}
cc511b8d
KK		 754early_initcall(exynos4_l2x0_cache_init);
755#endif
756
906c789c 757static int __init exynos_init(void)
cc511b8d
KK		 758{
759 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
94c7ca71 760
9ee6af9c 761 return device_register(&exynos4_dev);
cc511b8d
KK		 762}
763
cc511b8d
KK		 764/* uart registration process */
765
55b6ef7a 766static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
cc511b8d
KK		 767{
768 struct s3c2410_uartcfg *tcfg = cfg;
769 u32 ucnt;
770
237c78be
AB		 771 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
772 tcfg->has_fracval = 1;
cc511b8d 773
55b6ef7a 774 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
cc511b8d
KK		 775}
776
330c90a5
EK		 777static void __iomem *exynos_eint_base;
778
cc511b8d
KK		 779static DEFINE_SPINLOCK(eint_lock);
780
781static unsigned int eint0_15_data[16];
782
330c90a5 783static inline int exynos4_irq_to_gpio(unsigned int irq)
cc511b8d 784{
330c90a5
EK		 785 if (irq < IRQ_EINT(0))
786 return -EINVAL;
cc511b8d 787
330c90a5
EK		 788 irq -= IRQ_EINT(0);
789 if (irq < 8)
790 return EXYNOS4_GPX0(irq);
791
792 irq -= 8;
793 if (irq < 8)
794 return EXYNOS4_GPX1(irq);
795
796 irq -= 8;
797 if (irq < 8)
798 return EXYNOS4_GPX2(irq);
799
800 irq -= 8;
801 if (irq < 8)
802 return EXYNOS4_GPX3(irq);
803
804 return -EINVAL;
805}
806
807static inline int exynos5_irq_to_gpio(unsigned int irq)
808{
809 if (irq < IRQ_EINT(0))
810 return -EINVAL;
811
812 irq -= IRQ_EINT(0);
813 if (irq < 8)
814 return EXYNOS5_GPX0(irq);
815
816 irq -= 8;
817 if (irq < 8)
818 return EXYNOS5_GPX1(irq);
819
820 irq -= 8;
821 if (irq < 8)
822 return EXYNOS5_GPX2(irq);
cc511b8d 823
330c90a5
EK		 824 irq -= 8;
825 if (irq < 8)
826 return EXYNOS5_GPX3(irq);
827
828 return -EINVAL;
cc511b8d
KK		 829}
830
bb19a751
KK		 831static unsigned int exynos4_eint0_15_src_int[16] = {
832 EXYNOS4_IRQ_EINT0,
833 EXYNOS4_IRQ_EINT1,
834 EXYNOS4_IRQ_EINT2,
835 EXYNOS4_IRQ_EINT3,
836 EXYNOS4_IRQ_EINT4,
837 EXYNOS4_IRQ_EINT5,
838 EXYNOS4_IRQ_EINT6,
839 EXYNOS4_IRQ_EINT7,
840 EXYNOS4_IRQ_EINT8,
841 EXYNOS4_IRQ_EINT9,
842 EXYNOS4_IRQ_EINT10,
843 EXYNOS4_IRQ_EINT11,
844 EXYNOS4_IRQ_EINT12,
845 EXYNOS4_IRQ_EINT13,
846 EXYNOS4_IRQ_EINT14,
847 EXYNOS4_IRQ_EINT15,
848};
cc511b8d 849
bb19a751
KK		 850static unsigned int exynos5_eint0_15_src_int[16] = {
851 EXYNOS5_IRQ_EINT0,
852 EXYNOS5_IRQ_EINT1,
853 EXYNOS5_IRQ_EINT2,
854 EXYNOS5_IRQ_EINT3,
855 EXYNOS5_IRQ_EINT4,
856 EXYNOS5_IRQ_EINT5,
857 EXYNOS5_IRQ_EINT6,
858 EXYNOS5_IRQ_EINT7,
859 EXYNOS5_IRQ_EINT8,
860 EXYNOS5_IRQ_EINT9,
861 EXYNOS5_IRQ_EINT10,
862 EXYNOS5_IRQ_EINT11,
863 EXYNOS5_IRQ_EINT12,
864 EXYNOS5_IRQ_EINT13,
865 EXYNOS5_IRQ_EINT14,
866 EXYNOS5_IRQ_EINT15,
867};
330c90a5 868static inline void exynos_irq_eint_mask(struct irq_data *data)
cc511b8d
KK		 869{
870 u32 mask;
871
872 spin_lock(&eint_lock);
330c90a5
EK		 873 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
874 mask |= EINT_OFFSET_BIT(data->irq);
875 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
cc511b8d
KK		 876 spin_unlock(&eint_lock);
877}
878
330c90a5 879static void exynos_irq_eint_unmask(struct irq_data *data)
cc511b8d
KK		 880{
881 u32 mask;
882
883 spin_lock(&eint_lock);
330c90a5
EK		 884 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
885 mask &= ~(EINT_OFFSET_BIT(data->irq));
886 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
cc511b8d
KK		 887 spin_unlock(&eint_lock);
888}
889
330c90a5 890static inline void exynos_irq_eint_ack(struct irq_data *data)
cc511b8d 891{
330c90a5
EK		 892 __raw_writel(EINT_OFFSET_BIT(data->irq),
893 EINT_PEND(exynos_eint_base, data->irq));
cc511b8d
KK		 894}
895
330c90a5 896static void exynos_irq_eint_maskack(struct irq_data *data)
cc511b8d 897{
330c90a5
EK		 898 exynos_irq_eint_mask(data);
899 exynos_irq_eint_ack(data);
cc511b8d
KK		 900}
901
330c90a5 902static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
cc511b8d
KK		 903{
904 int offs = EINT_OFFSET(data->irq);
905 int shift;
906 u32 ctrl, mask;
907 u32 newvalue = 0;
908
909 switch (type) {
910 case IRQ_TYPE_EDGE_RISING:
911 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
912 break;
913
914 case IRQ_TYPE_EDGE_FALLING:
915 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
916 break;
917
918 case IRQ_TYPE_EDGE_BOTH:
919 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
920 break;
921
922 case IRQ_TYPE_LEVEL_LOW:
923 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
924 break;
925
926 case IRQ_TYPE_LEVEL_HIGH:
927 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
928 break;
929
930 default:
931 printk(KERN_ERR "No such irq type %d", type);
932 return -EINVAL;
933 }
934
935 shift = (offs & 0x7) * 4;
936 mask = 0x7 << shift;
937
938 spin_lock(&eint_lock);
330c90a5 939 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
cc511b8d
KK		 940 ctrl &= ~mask;
941 ctrl |= newvalue << shift;
330c90a5 942 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
cc511b8d
KK		 943 spin_unlock(&eint_lock);
944
330c90a5
EK		 945 if (soc_is_exynos5250())
946 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
947 else
948 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
cc511b8d
KK		 949
950 return 0;
951}
952
330c90a5
EK		 953static struct irq_chip exynos_irq_eint = {
954 .name = "exynos-eint",
955 .irq_mask = exynos_irq_eint_mask,
956 .irq_unmask = exynos_irq_eint_unmask,
957 .irq_mask_ack = exynos_irq_eint_maskack,
958 .irq_ack = exynos_irq_eint_ack,
959 .irq_set_type = exynos_irq_eint_set_type,
cc511b8d
KK		 960#ifdef CONFIG_PM
961 .irq_set_wake = s3c_irqext_wake,
962#endif
963};
964
965/*
966 * exynos4_irq_demux_eint
967 *
968 * This function demuxes the IRQ from from EINTs 16 to 31.
969 * It is designed to be inlined into the specific handler
970 * s5p_irq_demux_eintX_Y.
971 *
972 * Each EINT pend/mask registers handle eight of them.
973 */
330c90a5 974static inline void exynos_irq_demux_eint(unsigned int start)
cc511b8d
KK		 975{
976 unsigned int irq;
977
330c90a5
EK		 978 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
979 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
cc511b8d
KK		 980
981 status &= ~mask;
982 status &= 0xff;
983
984 while (status) {
985 irq = fls(status) - 1;
986 generic_handle_irq(irq + start);
987 status &= ~(1 << irq);
988 }
989}
990
330c90a5 991static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
cc511b8d
KK		 992{
993 struct irq_chip *chip = irq_get_chip(irq);
994 chained_irq_enter(chip, desc);
330c90a5
EK		 995 exynos_irq_demux_eint(IRQ_EINT(16));
996 exynos_irq_demux_eint(IRQ_EINT(24));
cc511b8d
KK		 997 chained_irq_exit(chip, desc);
998}
999
bb19a751 1000static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
cc511b8d
KK		 1001{
1002 u32 *irq_data = irq_get_handler_data(irq);
1003 struct irq_chip *chip = irq_get_chip(irq);
1004
1005 chained_irq_enter(chip, desc);
cc511b8d 1006 generic_handle_irq(*irq_data);
cc511b8d
KK		 1007 chained_irq_exit(chip, desc);
1008}
1009
330c90a5 1010static int __init exynos_init_irq_eint(void)
cc511b8d
KK		 1011{
1012 int irq;
1013
fef05c29
TA		 1014#ifdef CONFIG_PINCTRL_SAMSUNG
1015 /*
1016 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
1017 * functionality along with support for external gpio and wakeup
1018 * interrupts. If the samsung pinctrl driver is enabled and includes
1019 * the wakeup interrupt support, then the setting up external wakeup
1020 * interrupts here can be skipped. This check here is temporary to
1021 * allow exynos4 platforms that do not use Samsung pinctrl driver to
1022 * co-exist with platforms that do. When all of the Samsung Exynos4
1023 * platforms switch over to using the pinctrl driver, the wakeup
1024 * interrupt support code here can be completely removed.
1025 */
ab7b51ff
TF		 1026 static const struct of_device_id exynos_pinctrl_ids[] = {
1027 { .compatible = "samsung,pinctrl-exynos4210", },
1028 { .compatible = "samsung,pinctrl-exynos4x12", },
1029 };
fef05c29 1030 struct device_node *pctrl_np, *wkup_np;
fef05c29
TA		 1031 const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
1032
ab7b51ff 1033 for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
fef05c29
TA		 1034 if (of_device_is_available(pctrl_np)) {
1035 wkup_np = of_find_compatible_node(pctrl_np, NULL,
1036 wkup_compat);
1037 if (wkup_np)
1038 return -ENODEV;
1039 }
1040 }
1041#endif
2edb36c4
KK		 1042 if (soc_is_exynos5440())
1043 return 0;
fef05c29 1044
94c7ca71 1045 if (soc_is_exynos5250())
330c90a5
EK		 1046 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
1047 else
1048 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
1049
1050 if (exynos_eint_base == NULL) {
1051 pr_err("unable to ioremap for EINT base address\n");
1052 return -ENOMEM;
1053 }
94c7ca71 1054
cc511b8d 1055 for (irq = 0 ; irq <= 31 ; irq++) {
330c90a5 1056 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
cc511b8d
KK		 1057 handle_level_irq);
1058 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
1059 }
1060
330c90a5 1061 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
cc511b8d
KK		 1062
1063 for (irq = 0 ; irq <= 15 ; irq++) {
1064 eint0_15_data[irq] = IRQ_EINT(irq);
1065
bb19a751
KK		 1066 if (soc_is_exynos5250()) {
1067 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
1068 &eint0_15_data[irq]);
1069 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
1070 exynos_irq_eint0_15);
1071 } else {
1072 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
1073 &eint0_15_data[irq]);
1074 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
1075 exynos_irq_eint0_15);
1076 }
cc511b8d
KK		 1077 }
1078
1079 return 0;
1080}
330c90a5 1081arch_initcall(exynos_init_irq_eint);
Linux kernel - Deliverables
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