[deliverable/linux.git] / arch / arm / mach-exynos / firmware.c

/*
 * Copyright (C) 2012 Samsung Electronics.
 * Kyungmin Park <kyungmin.park@samsung.com>
 * Tomasz Figa <t.figa@samsung.com>
 *
 * This program is free software,you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include <asm/firmware.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/suspend.h>

#include <mach/map.h>

#include "common.h"
#include "smc.h"

#define EXYNOS_SLEEP_MAGIC	0x00000bad
#define EXYNOS_AFTR_MAGIC	0xfcba0d10
#define EXYNOS_BOOT_ADDR	0x8
#define EXYNOS_BOOT_FLAG	0xc

static void exynos_save_cp15(void)
{
	/* Save Power control and Diagnostic registers */
	asm ("mrc p15, 0, %0, c15, c0, 0\n"
	     "mrc p15, 0, %1, c15, c0, 1\n"
	     : "=r" (cp15_save_power), "=r" (cp15_save_diag)
	     : : "cc");
}

static int exynos_do_idle(unsigned long mode)
{
	switch (mode) {
	case FW_DO_IDLE_AFTR:
		if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
			exynos_save_cp15();
		__raw_writel(virt_to_phys(exynos_cpu_resume_ns),
			     sysram_ns_base_addr + 0x24);
		__raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
		exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
		break;
	case FW_DO_IDLE_SLEEP:
		exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
	}
	return 0;
}

static int exynos_cpu_boot(int cpu)
{
	/*
	 * Exynos3250 doesn't need to send smc command for secondary CPU boot
	 * because Exynos3250 removes WFE in secure mode.
	 */
	if (soc_is_exynos3250())
		return 0;

	/*
	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
	 * But, Exynos4212 has only one secondary CPU so second parameter
	 * isn't used for informing secure firmware about CPU id.
	 */
	if (soc_is_exynos4212())
		cpu = 0;

	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
	return 0;
}

static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
{
	void __iomem *boot_reg;

	if (!sysram_ns_base_addr)
		return -ENODEV;

	boot_reg = sysram_ns_base_addr + 0x1c;

	/*
	 * Almost all Exynos-series of SoCs that run in secure mode don't need
	 * additional offset for every CPU, with Exynos4412 being the only
	 * exception.
	 */
	if (soc_is_exynos4412())
		boot_reg += 4 * cpu;

	__raw_writel(boot_addr, boot_reg);
	return 0;
}

static int exynos_cpu_suspend(unsigned long arg)
{
	flush_cache_all();
	outer_flush_all();

	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);

	pr_info("Failed to suspend the system\n");
	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	return 1;
}

static int exynos_suspend(void)
{
	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
		exynos_save_cp15();

	writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	writel(virt_to_phys(exynos_cpu_resume_ns),
		sysram_ns_base_addr + EXYNOS_BOOT_ADDR);

	return cpu_suspend(0, exynos_cpu_suspend);
}

static int exynos_resume(void)
{
	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);

	return 0;
}

static const struct firmware_ops exynos_firmware_ops = {
	.do_idle		= IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL,
	.set_cpu_boot_addr	= exynos_set_cpu_boot_addr,
	.cpu_boot		= exynos_cpu_boot,
	.suspend		= IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL,
	.resume			= IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL,
};

static void exynos_l2_write_sec(unsigned long val, unsigned reg)
{
	static int l2cache_enabled;

	switch (reg) {
	case L2X0_CTRL:
		if (val & L2X0_CTRL_EN) {
			/*
			 * Before the cache can be enabled, due to firmware
			 * design, SMC_CMD_L2X0INVALL must be called.
			 */
			if (!l2cache_enabled) {
				exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
				l2cache_enabled = 1;
			}
		} else {
			l2cache_enabled = 0;
		}
		exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
		break;

	case L2X0_DEBUG_CTRL:
		exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
		break;

	default:
		WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg);
	}
}

static void exynos_l2_configure(const struct l2x0_regs *regs)
{
	exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
		   regs->prefetch_ctrl);
	exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
}

void __init exynos_firmware_init(void)
{
	struct device_node *nd;
	const __be32 *addr;

	nd = of_find_compatible_node(NULL, NULL,
					"samsung,secure-firmware");
	if (!nd)
		return;

	addr = of_get_address(nd, 0, NULL, NULL);
	if (!addr) {
		pr_err("%s: No address specified.\n", __func__);
		return;
	}

	pr_info("Running under secure firmware.\n");

	register_firmware_ops(&exynos_firmware_ops);

	/*
	 * Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
	 * running under secure firmware, require certain registers of L2
	 * cache controller to be written in secure mode. Here .write_sec
	 * callback is provided to perform necessary SMC calls.
	 */
	if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
	    read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
		outer_cache.write_sec = exynos_l2_write_sec;
		outer_cache.configure = exynos_l2_configure;
	}
}
Commit	Line	Data
bca28f8f TF	1	/*
	2	* Copyright (C) 2012 Samsung Electronics.
	3	* Kyungmin Park <kyungmin.park@samsung.com>
	4	* Tomasz Figa <t.figa@samsung.com>
	5	*
	6	* This program is free software,you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/io.h>
	13	#include <linux/init.h>
	14	#include <linux/of.h>
	15	#include <linux/of_address.h>
	16
2b9d9c32 TF	17	#include <asm/cacheflush.h>
2b9d9c32 TF	18	#include <asm/cputype.h>
bca28f8f	19	#include <asm/firmware.h>
5445b640	20	#include <asm/hardware/cache-l2x0.h>
2b9d9c32	21	#include <asm/suspend.h>
bca28f8f TF	22
	23	#include <mach/map.h>
	24
b3205dea	25	#include "common.h"
bca28f8f TF	26	#include "smc.h"
bca28f8f TF	27
2b9d9c32	28	#define EXYNOS_SLEEP_MAGIC 0x00000bad
a135e201	29	#define EXYNOS_AFTR_MAGIC 0xfcba0d10
2b9d9c32 TF	30	#define EXYNOS_BOOT_ADDR 0x8
	31	#define EXYNOS_BOOT_FLAG 0xc
	32
a135e201 BZ	33	static void exynos_save_cp15(void)
	34	{
	35	/* Save Power control and Diagnostic registers */
	36	asm ("mrc p15, 0, %0, c15, c0, 0\n"
	37	"mrc p15, 0, %1, c15, c0, 1\n"
	38	: "=r" (cp15_save_power), "=r" (cp15_save_diag)
	39	: : "cc");
	40	}
	41
0b7778a8	42	static int exynos_do_idle(unsigned long mode)
bca28f8f	43	{
0b7778a8 BZ	44	switch (mode) {
0b7778a8 BZ	45	case FW_DO_IDLE_AFTR:
a135e201 BZ	46	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
	47	exynos_save_cp15();
	48	__raw_writel(virt_to_phys(exynos_cpu_resume_ns),
	49	sysram_ns_base_addr + 0x24);
	50	__raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
0b7778a8 BZ	51	exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
	52	break;
	53	case FW_DO_IDLE_SLEEP:
	54	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
	55	}
bca28f8f TF	56	return 0;
	57	}
	58
	59	static int exynos_cpu_boot(int cpu)
	60	{
6457158a CC	61	/*
	62	* Exynos3250 doesn't need to send smc command for secondary CPU boot
	63	* because Exynos3250 removes WFE in secure mode.
	64	*/
	65	if (soc_is_exynos3250())
	66	return 0;
	67
989ff3fd KP	68	/*
	69	* The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
	70	* But, Exynos4212 has only one secondary CPU so second parameter
	71	* isn't used for informing secure firmware about CPU id.
	72	*/
	73	if (soc_is_exynos4212())
	74	cpu = 0;
	75
bca28f8f TF	76	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
	77	return 0;
	78	}
	79
	80	static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
	81	{
b3205dea SK	82	void __iomem *boot_reg;
	83
	84	if (!sysram_ns_base_addr)
	85	return -ENODEV;
	86
fe388fac	87	boot_reg = sysram_ns_base_addr + 0x1c;
989ff3fd	88
35e75645 SK	89	/*
	90	* Almost all Exynos-series of SoCs that run in secure mode don't need
	91	* additional offset for every CPU, with Exynos4412 being the only
	92	* exception.
	93	*/
	94	if (soc_is_exynos4412())
	95	boot_reg += 4 * cpu;
bca28f8f TF	96
	97	__raw_writel(boot_addr, boot_reg);
	98	return 0;
	99	}
	100
2b9d9c32 TF	101	static int exynos_cpu_suspend(unsigned long arg)
	102	{
	103	flush_cache_all();
	104	outer_flush_all();
	105
	106	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
	107
	108	pr_info("Failed to suspend the system\n");
	109	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	110	return 1;
	111	}
	112
	113	static int exynos_suspend(void)
	114	{
a135e201 BZ	115	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
a135e201 BZ	116	exynos_save_cp15();
2b9d9c32 TF	117
	118	writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	119	writel(virt_to_phys(exynos_cpu_resume_ns),
	120	sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
	121
	122	return cpu_suspend(0, exynos_cpu_suspend);
	123	}
	124
	125	static int exynos_resume(void)
	126	{
	127	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	128
	129	return 0;
	130	}
	131
bca28f8f	132	static const struct firmware_ops exynos_firmware_ops = {
03c1b760	133	.do_idle = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL,
bca28f8f TF	134	.set_cpu_boot_addr = exynos_set_cpu_boot_addr,
bca28f8f TF	135	.cpu_boot = exynos_cpu_boot,
03c1b760 AB	136	.suspend = IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL,
03c1b760 AB	137	.resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL,
bca28f8f TF	138	};
bca28f8f TF	139
5445b640 TF	140	static void exynos_l2_write_sec(unsigned long val, unsigned reg)
	141	{
	142	static int l2cache_enabled;
	143
	144	switch (reg) {
	145	case L2X0_CTRL:
	146	if (val & L2X0_CTRL_EN) {
	147	/*
	148	* Before the cache can be enabled, due to firmware
	149	* design, SMC_CMD_L2X0INVALL must be called.
	150	*/
	151	if (!l2cache_enabled) {
	152	exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
	153	l2cache_enabled = 1;
	154	}
	155	} else {
	156	l2cache_enabled = 0;
	157	}
	158	exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
	159	break;
	160
	161	case L2X0_DEBUG_CTRL:
	162	exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
	163	break;
	164
	165	default:
	166	WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg);
	167	}
	168	}
	169
	170	static void exynos_l2_configure(const struct l2x0_regs *regs)
	171	{
	172	exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
	173	regs->prefetch_ctrl);
	174	exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
	175	}
	176
bca28f8f TF	177	void __init exynos_firmware_init(void)
bca28f8f TF	178	{
4ee1cc79 TF	179	struct device_node *nd;
4ee1cc79 TF	180	const __be32 *addr;
bca28f8f	181
4ee1cc79 TF	182	nd = of_find_compatible_node(NULL, NULL,
	183	"samsung,secure-firmware");
	184	if (!nd)
	185	return;
bca28f8f	186
4ee1cc79 TF	187	addr = of_get_address(nd, 0, NULL, NULL);
	188	if (!addr) {
	189	pr_err("%s: No address specified.\n", __func__);
	190	return;
bca28f8f TF	191	}
	192
	193	pr_info("Running under secure firmware.\n");
	194
	195	register_firmware_ops(&exynos_firmware_ops);
5445b640 TF	196
	197	/*
	198	* Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
	199	* running under secure firmware, require certain registers of L2
	200	* cache controller to be written in secure mode. Here .write_sec
	201	* callback is provided to perform necessary SMC calls.
	202	*/
	203	if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
	204	read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
	205	outer_cache.write_sec = exynos_l2_write_sec;
	206	outer_cache.configure = exynos_l2_configure;
	207	}
bca28f8f	208	}