[deliverable/linux.git] / arch / arm / mach-exynos / firmware.c

/*
 * Copyright (C) 2012 Samsung Electronics.
 * Kyungmin Park <kyungmin.park@samsung.com>
 * Tomasz Figa <t.figa@samsung.com>
 *
 * This program is free software,you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include <asm/firmware.h>
#include <asm/suspend.h>

#include <mach/map.h>

#include "common.h"
#include "smc.h"

#define EXYNOS_SLEEP_MAGIC	0x00000bad
#define EXYNOS_BOOT_ADDR	0x8
#define EXYNOS_BOOT_FLAG	0xc

static int exynos_do_idle(void)
{
	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
	return 0;
}

static int exynos_cpu_boot(int cpu)
{
	/*
	 * Exynos3250 doesn't need to send smc command for secondary CPU boot
	 * because Exynos3250 removes WFE in secure mode.
	 */
	if (soc_is_exynos3250())
		return 0;

	/*
	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
	 * But, Exynos4212 has only one secondary CPU so second parameter
	 * isn't used for informing secure firmware about CPU id.
	 */
	if (soc_is_exynos4212())
		cpu = 0;

	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
	return 0;
}

static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
{
	void __iomem *boot_reg;

	if (!sysram_ns_base_addr)
		return -ENODEV;

	boot_reg = sysram_ns_base_addr + 0x1c;

	/*
	 * Almost all Exynos-series of SoCs that run in secure mode don't need
	 * additional offset for every CPU, with Exynos4412 being the only
	 * exception.
	 */
	if (soc_is_exynos4412())
		boot_reg += 4 * cpu;

	__raw_writel(boot_addr, boot_reg);
	return 0;
}

static int exynos_cpu_suspend(unsigned long arg)
{
	flush_cache_all();
	outer_flush_all();

	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);

	pr_info("Failed to suspend the system\n");
	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	return 1;
}

static int exynos_suspend(void)
{
	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
		/* Save Power control and Diagnostic registers */
		asm ("mrc p15, 0, %0, c15, c0, 0\n"
			"mrc p15, 0, %1, c15, c0, 1\n"
			: "=r" (cp15_save_power), "=r" (cp15_save_diag)
			: : "cc");
	}

	writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	writel(virt_to_phys(exynos_cpu_resume_ns),
		sysram_ns_base_addr + EXYNOS_BOOT_ADDR);

	return cpu_suspend(0, exynos_cpu_suspend);
}

static int exynos_resume(void)
{
	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);

	return 0;
}

static const struct firmware_ops exynos_firmware_ops = {
	.do_idle		= exynos_do_idle,
	.set_cpu_boot_addr	= exynos_set_cpu_boot_addr,
	.cpu_boot		= exynos_cpu_boot,
	.suspend		= exynos_suspend,
	.resume			= exynos_resume,
};

void __init exynos_firmware_init(void)
{
	struct device_node *nd;
	const __be32 *addr;

	nd = of_find_compatible_node(NULL, NULL,
					"samsung,secure-firmware");
	if (!nd)
		return;

	addr = of_get_address(nd, 0, NULL, NULL);
	if (!addr) {
		pr_err("%s: No address specified.\n", __func__);
		return;
	}

	pr_info("Running under secure firmware.\n");

	register_firmware_ops(&exynos_firmware_ops);
}
Commit	Line	Data
bca28f8f TF	1	/*
	2	* Copyright (C) 2012 Samsung Electronics.
	3	* Kyungmin Park <kyungmin.park@samsung.com>
	4	* Tomasz Figa <t.figa@samsung.com>
	5	*
	6	* This program is free software,you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/io.h>
	13	#include <linux/init.h>
	14	#include <linux/of.h>
	15	#include <linux/of_address.h>
	16
2b9d9c32 TF	17	#include <asm/cacheflush.h>
2b9d9c32 TF	18	#include <asm/cputype.h>
bca28f8f	19	#include <asm/firmware.h>
2b9d9c32	20	#include <asm/suspend.h>
bca28f8f TF	21
	22	#include <mach/map.h>
	23
b3205dea	24	#include "common.h"
bca28f8f TF	25	#include "smc.h"
bca28f8f TF	26
2b9d9c32 TF	27	#define EXYNOS_SLEEP_MAGIC 0x00000bad
	28	#define EXYNOS_BOOT_ADDR 0x8
	29	#define EXYNOS_BOOT_FLAG 0xc
	30
bca28f8f TF	31	static int exynos_do_idle(void)
	32	{
	33	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
	34	return 0;
	35	}
	36
	37	static int exynos_cpu_boot(int cpu)
	38	{
6457158a CC	39	/*
	40	* Exynos3250 doesn't need to send smc command for secondary CPU boot
	41	* because Exynos3250 removes WFE in secure mode.
	42	*/
	43	if (soc_is_exynos3250())
	44	return 0;
	45
989ff3fd KP	46	/*
	47	* The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
	48	* But, Exynos4212 has only one secondary CPU so second parameter
	49	* isn't used for informing secure firmware about CPU id.
	50	*/
	51	if (soc_is_exynos4212())
	52	cpu = 0;
	53
bca28f8f TF	54	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
	55	return 0;
	56	}
	57
	58	static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
	59	{
b3205dea SK	60	void __iomem *boot_reg;
	61
	62	if (!sysram_ns_base_addr)
	63	return -ENODEV;
	64
fe388fac	65	boot_reg = sysram_ns_base_addr + 0x1c;
989ff3fd	66
35e75645 SK	67	/*
	68	* Almost all Exynos-series of SoCs that run in secure mode don't need
	69	* additional offset for every CPU, with Exynos4412 being the only
	70	* exception.
	71	*/
	72	if (soc_is_exynos4412())
	73	boot_reg += 4 * cpu;
bca28f8f TF	74
	75	__raw_writel(boot_addr, boot_reg);
	76	return 0;
	77	}
	78
2b9d9c32 TF	79	static int exynos_cpu_suspend(unsigned long arg)
	80	{
	81	flush_cache_all();
	82	outer_flush_all();
	83
	84	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
	85
	86	pr_info("Failed to suspend the system\n");
	87	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	88	return 1;
	89	}
	90
	91	static int exynos_suspend(void)
	92	{
	93	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
	94	/* Save Power control and Diagnostic registers */
	95	asm ("mrc p15, 0, %0, c15, c0, 0\n"
	96	"mrc p15, 0, %1, c15, c0, 1\n"
	97	: "=r" (cp15_save_power), "=r" (cp15_save_diag)
	98	: : "cc");
	99	}
	100
	101	writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	102	writel(virt_to_phys(exynos_cpu_resume_ns),
	103	sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
	104
	105	return cpu_suspend(0, exynos_cpu_suspend);
	106	}
	107
	108	static int exynos_resume(void)
	109	{
	110	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	111
	112	return 0;
	113	}
	114
bca28f8f TF	115	static const struct firmware_ops exynos_firmware_ops = {
	116	.do_idle = exynos_do_idle,
	117	.set_cpu_boot_addr = exynos_set_cpu_boot_addr,
	118	.cpu_boot = exynos_cpu_boot,
2b9d9c32 TF	119	.suspend = exynos_suspend,
2b9d9c32 TF	120	.resume = exynos_resume,
bca28f8f TF	121	};
	122
	123	void __init exynos_firmware_init(void)
	124	{
4ee1cc79 TF	125	struct device_node *nd;
4ee1cc79 TF	126	const __be32 *addr;
bca28f8f	127
4ee1cc79 TF	128	nd = of_find_compatible_node(NULL, NULL,
	129	"samsung,secure-firmware");
	130	if (!nd)
	131	return;
bca28f8f	132
4ee1cc79 TF	133	addr = of_get_address(nd, 0, NULL, NULL);
	134	if (!addr) {
	135	pr_err("%s: No address specified.\n", __func__);
	136	return;
bca28f8f TF	137	}
	138
	139	pr_info("Running under secure firmware.\n");
	140
	141	register_firmware_ops(&exynos_firmware_ops);
	142	}