Commit | Line | Data |
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7d30e8b3 | 1 | /* linux/arch/arm/mach-exynos4/platsmp.c |
2b12b5c4 | 2 | * |
7d30e8b3 KK |
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
2b12b5c4 CY |
5 | * |
6 | * Cloned from linux/arch/arm/mach-vexpress/platsmp.c | |
7 | * | |
8 | * Copyright (C) 2002 ARM Ltd. | |
9 | * All Rights Reserved | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/jiffies.h> | |
21 | #include <linux/smp.h> | |
22 | #include <linux/io.h> | |
b3205dea | 23 | #include <linux/of_address.h> |
2b12b5c4 CY |
24 | |
25 | #include <asm/cacheflush.h> | |
eb50439b | 26 | #include <asm/smp_plat.h> |
2b12b5c4 | 27 | #include <asm/smp_scu.h> |
beddf63f | 28 | #include <asm/firmware.h> |
2b12b5c4 | 29 | |
06853ae4 | 30 | #include "common.h" |
65c9a853 | 31 | #include "regs-pmu.h" |
06853ae4 | 32 | |
7d30e8b3 | 33 | extern void exynos4_secondary_startup(void); |
2b12b5c4 | 34 | |
1f054f52 TF |
35 | static inline void __iomem *cpu_boot_reg_base(void) |
36 | { | |
37 | if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) | |
38 | return S5P_INFORM5; | |
b3205dea | 39 | return sysram_base_addr; |
1f054f52 TF |
40 | } |
41 | ||
42 | static inline void __iomem *cpu_boot_reg(int cpu) | |
43 | { | |
44 | void __iomem *boot_reg; | |
45 | ||
46 | boot_reg = cpu_boot_reg_base(); | |
b3205dea SK |
47 | if (!boot_reg) |
48 | return ERR_PTR(-ENODEV); | |
1f054f52 TF |
49 | if (soc_is_exynos4412()) |
50 | boot_reg += 4*cpu; | |
86c6f148 | 51 | else if (soc_is_exynos5420() || soc_is_exynos5800()) |
1580be3d | 52 | boot_reg += 4; |
1f054f52 TF |
53 | return boot_reg; |
54 | } | |
911c29b0 | 55 | |
3705ff6d RK |
56 | /* |
57 | * Write pen_release in a way that is guaranteed to be visible to all | |
58 | * observers, irrespective of whether they're taking part in coherency | |
59 | * or not. This is necessary for the hotplug code to work reliably. | |
60 | */ | |
61 | static void write_pen_release(int val) | |
62 | { | |
63 | pen_release = val; | |
64 | smp_wmb(); | |
f45913fd | 65 | sync_cache_w(&pen_release); |
3705ff6d RK |
66 | } |
67 | ||
2b12b5c4 CY |
68 | static void __iomem *scu_base_addr(void) |
69 | { | |
70 | return (void __iomem *)(S5P_VA_SCU); | |
71 | } | |
72 | ||
73 | static DEFINE_SPINLOCK(boot_lock); | |
74 | ||
8bd26e3a | 75 | static void exynos_secondary_init(unsigned int cpu) |
2b12b5c4 | 76 | { |
2b12b5c4 CY |
77 | /* |
78 | * let the primary processor know we're out of the | |
79 | * pen, then head off into the C entry point | |
80 | */ | |
3705ff6d | 81 | write_pen_release(-1); |
2b12b5c4 CY |
82 | |
83 | /* | |
84 | * Synchronise with the boot thread. | |
85 | */ | |
86 | spin_lock(&boot_lock); | |
87 | spin_unlock(&boot_lock); | |
88 | } | |
89 | ||
8bd26e3a | 90 | static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) |
2b12b5c4 CY |
91 | { |
92 | unsigned long timeout; | |
9637f30e TF |
93 | u32 mpidr = cpu_logical_map(cpu); |
94 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
b3205dea | 95 | int ret = -ENOSYS; |
2b12b5c4 CY |
96 | |
97 | /* | |
98 | * Set synchronisation state between this boot processor | |
99 | * and the secondary one | |
100 | */ | |
101 | spin_lock(&boot_lock); | |
102 | ||
103 | /* | |
104 | * The secondary processor is waiting to be released from | |
105 | * the holding pen - release it, then wait for it to flag | |
106 | * that it has been released by resetting pen_release. | |
107 | * | |
9637f30e | 108 | * Note that "pen_release" is the hardware CPU core ID, whereas |
2b12b5c4 CY |
109 | * "cpu" is Linux's internal ID. |
110 | */ | |
9637f30e | 111 | write_pen_release(core_id); |
2b12b5c4 | 112 | |
9637f30e TF |
113 | if (!exynos_cpu_power_state(core_id)) { |
114 | exynos_cpu_power_up(core_id); | |
911c29b0 JM |
115 | timeout = 10; |
116 | ||
117 | /* wait max 10 ms until cpu1 is on */ | |
9637f30e TF |
118 | while (exynos_cpu_power_state(core_id) |
119 | != S5P_CORE_LOCAL_PWR_EN) { | |
911c29b0 JM |
120 | if (timeout-- == 0) |
121 | break; | |
122 | ||
123 | mdelay(1); | |
124 | } | |
125 | ||
126 | if (timeout == 0) { | |
127 | printk(KERN_ERR "cpu1 power enable failed"); | |
128 | spin_unlock(&boot_lock); | |
129 | return -ETIMEDOUT; | |
130 | } | |
131 | } | |
2b12b5c4 CY |
132 | /* |
133 | * Send the secondary CPU a soft interrupt, thereby causing | |
134 | * the boot monitor to read the system wide flags register, | |
135 | * and branch to the address found there. | |
136 | */ | |
2b12b5c4 CY |
137 | |
138 | timeout = jiffies + (1 * HZ); | |
139 | while (time_before(jiffies, timeout)) { | |
beddf63f TF |
140 | unsigned long boot_addr; |
141 | ||
2b12b5c4 | 142 | smp_rmb(); |
911c29b0 | 143 | |
beddf63f TF |
144 | boot_addr = virt_to_phys(exynos4_secondary_startup); |
145 | ||
146 | /* | |
147 | * Try to set boot address using firmware first | |
148 | * and fall back to boot register if it fails. | |
149 | */ | |
9637f30e | 150 | ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr); |
b3205dea SK |
151 | if (ret && ret != -ENOSYS) |
152 | goto fail; | |
153 | if (ret == -ENOSYS) { | |
9637f30e | 154 | void __iomem *boot_reg = cpu_boot_reg(core_id); |
b3205dea SK |
155 | |
156 | if (IS_ERR(boot_reg)) { | |
157 | ret = PTR_ERR(boot_reg); | |
158 | goto fail; | |
159 | } | |
9637f30e | 160 | __raw_writel(boot_addr, cpu_boot_reg(core_id)); |
b3205dea | 161 | } |
beddf63f | 162 | |
9637f30e | 163 | call_firmware_op(cpu_boot, core_id); |
beddf63f | 164 | |
b1cffebf | 165 | arch_send_wakeup_ipi_mask(cpumask_of(cpu)); |
911c29b0 | 166 | |
2b12b5c4 CY |
167 | if (pen_release == -1) |
168 | break; | |
169 | ||
170 | udelay(10); | |
171 | } | |
172 | ||
173 | /* | |
174 | * now the secondary core is starting up let it run its | |
175 | * calibrations, then wait for it to finish | |
176 | */ | |
b3205dea | 177 | fail: |
2b12b5c4 CY |
178 | spin_unlock(&boot_lock); |
179 | ||
b3205dea | 180 | return pen_release != -1 ? ret : 0; |
2b12b5c4 CY |
181 | } |
182 | ||
183 | /* | |
184 | * Initialise the CPU possible map early - this describes the CPUs | |
185 | * which may be present or become present in the system. | |
186 | */ | |
187 | ||
06853ae4 | 188 | static void __init exynos_smp_init_cpus(void) |
2b12b5c4 CY |
189 | { |
190 | void __iomem *scu_base = scu_base_addr(); | |
191 | unsigned int i, ncores; | |
192 | ||
1897d2f3 | 193 | if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) |
e9bba615 | 194 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
1897d2f3 CK |
195 | else |
196 | /* | |
197 | * CPU Nodes are passed thru DT and set_cpu_possible | |
198 | * is set by "arm_dt_init_cpu_maps". | |
199 | */ | |
200 | return; | |
2b12b5c4 CY |
201 | |
202 | /* sanity check */ | |
a06f916b RK |
203 | if (ncores > nr_cpu_ids) { |
204 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | |
205 | ncores, nr_cpu_ids); | |
206 | ncores = nr_cpu_ids; | |
2b12b5c4 CY |
207 | } |
208 | ||
209 | for (i = 0; i < ncores; i++) | |
210 | set_cpu_possible(i, true); | |
211 | } | |
212 | ||
06853ae4 | 213 | static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) |
2b12b5c4 | 214 | { |
1f054f52 TF |
215 | int i; |
216 | ||
1754c42e OJ |
217 | exynos_sysram_init(); |
218 | ||
b5f3c75a | 219 | if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) |
e9bba615 | 220 | scu_enable(scu_base_addr()); |
05c74a6c | 221 | |
2b12b5c4 | 222 | /* |
05c74a6c RK |
223 | * Write the address of secondary startup into the |
224 | * system-wide flags register. The boot monitor waits | |
225 | * until it receives a soft interrupt, and then the | |
226 | * secondary CPU branches to this address. | |
beddf63f TF |
227 | * |
228 | * Try using firmware operation first and fall back to | |
229 | * boot register if it fails. | |
2b12b5c4 | 230 | */ |
beddf63f | 231 | for (i = 1; i < max_cpus; ++i) { |
beddf63f | 232 | unsigned long boot_addr; |
9637f30e TF |
233 | u32 mpidr; |
234 | u32 core_id; | |
b3205dea | 235 | int ret; |
beddf63f | 236 | |
9637f30e TF |
237 | mpidr = cpu_logical_map(i); |
238 | core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
beddf63f TF |
239 | boot_addr = virt_to_phys(exynos4_secondary_startup); |
240 | ||
9637f30e | 241 | ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr); |
b3205dea SK |
242 | if (ret && ret != -ENOSYS) |
243 | break; | |
244 | if (ret == -ENOSYS) { | |
9637f30e | 245 | void __iomem *boot_reg = cpu_boot_reg(core_id); |
b3205dea SK |
246 | |
247 | if (IS_ERR(boot_reg)) | |
248 | break; | |
9637f30e | 249 | __raw_writel(boot_addr, cpu_boot_reg(core_id)); |
b3205dea | 250 | } |
beddf63f | 251 | } |
2b12b5c4 | 252 | } |
06853ae4 MZ |
253 | |
254 | struct smp_operations exynos_smp_ops __initdata = { | |
255 | .smp_init_cpus = exynos_smp_init_cpus, | |
256 | .smp_prepare_cpus = exynos_smp_prepare_cpus, | |
257 | .smp_secondary_init = exynos_secondary_init, | |
258 | .smp_boot_secondary = exynos_boot_secondary, | |
259 | #ifdef CONFIG_HOTPLUG_CPU | |
260 | .cpu_die = exynos_cpu_die, | |
261 | #endif | |
262 | }; |