Commit | Line | Data |
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b3ed3a17 | 1 | /* linux/arch/arm/mach-exynos4/clock.c |
c8bef140 | 2 | * |
b3ed3a17 KK |
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
c8bef140 | 5 | * |
b3ed3a17 | 6 | * EXYNOS4 - Clock support |
c8bef140 CY |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/io.h> | |
16 | ||
17 | #include <plat/cpu-freq.h> | |
18 | #include <plat/clock.h> | |
19 | #include <plat/cpu.h> | |
20 | #include <plat/pll.h> | |
21 | #include <plat/s5p-clock.h> | |
22 | #include <plat/clock-clksrc.h> | |
23 | ||
24 | #include <mach/map.h> | |
25 | #include <mach/regs-clock.h> | |
b0b6ff0b | 26 | #include <mach/sysmmu.h> |
c8bef140 CY |
27 | |
28 | static struct clk clk_sclk_hdmi27m = { | |
29 | .name = "sclk_hdmi27m", | |
c8bef140 CY |
30 | .rate = 27000000, |
31 | }; | |
32 | ||
b99380e1 JL |
33 | static struct clk clk_sclk_hdmiphy = { |
34 | .name = "sclk_hdmiphy", | |
b99380e1 JL |
35 | }; |
36 | ||
37 | static struct clk clk_sclk_usbphy0 = { | |
38 | .name = "sclk_usbphy0", | |
b99380e1 JL |
39 | .rate = 27000000, |
40 | }; | |
41 | ||
42 | static struct clk clk_sclk_usbphy1 = { | |
43 | .name = "sclk_usbphy1", | |
b99380e1 JL |
44 | }; |
45 | ||
b3ed3a17 | 46 | static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) |
37e01729 JL |
47 | { |
48 | return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable); | |
49 | } | |
50 | ||
b3ed3a17 | 51 | static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable) |
33f469d2 JL |
52 | { |
53 | return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable); | |
54 | } | |
55 | ||
b3ed3a17 | 56 | static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) |
33f469d2 JL |
57 | { |
58 | return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable); | |
59 | } | |
60 | ||
b3ed3a17 | 61 | static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) |
33f469d2 JL |
62 | { |
63 | return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); | |
64 | } | |
65 | ||
b3ed3a17 | 66 | static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) |
340ea1ef JL |
67 | { |
68 | return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable); | |
69 | } | |
70 | ||
b3ed3a17 | 71 | static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) |
3297c2e6 JL |
72 | { |
73 | return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); | |
74 | } | |
75 | ||
b3ed3a17 | 76 | static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) |
33f469d2 JL |
77 | { |
78 | return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable); | |
79 | } | |
80 | ||
b0b6ff0b KC |
81 | static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable) |
82 | { | |
83 | return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable); | |
84 | } | |
85 | ||
b3ed3a17 | 86 | static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable) |
82260bf3 JL |
87 | { |
88 | return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable); | |
89 | } | |
90 | ||
b0b6ff0b KC |
91 | static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable) |
92 | { | |
93 | return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable); | |
94 | } | |
95 | ||
b3ed3a17 | 96 | static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable) |
82260bf3 JL |
97 | { |
98 | return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable); | |
99 | } | |
100 | ||
b3ed3a17 | 101 | static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable) |
82260bf3 JL |
102 | { |
103 | return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable); | |
104 | } | |
105 | ||
b3ed3a17 | 106 | static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) |
82260bf3 JL |
107 | { |
108 | return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable); | |
109 | } | |
110 | ||
b3ed3a17 | 111 | static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) |
340ea1ef JL |
112 | { |
113 | return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable); | |
114 | } | |
115 | ||
b3ed3a17 | 116 | static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable) |
5a847b4a JL |
117 | { |
118 | return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); | |
119 | } | |
120 | ||
b3ed3a17 | 121 | static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) |
82260bf3 JL |
122 | { |
123 | return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable); | |
124 | } | |
125 | ||
c8bef140 CY |
126 | /* Core list of CMU_CPU side */ |
127 | ||
128 | static struct clksrc_clk clk_mout_apll = { | |
129 | .clk = { | |
130 | .name = "mout_apll", | |
c8bef140 CY |
131 | }, |
132 | .sources = &clk_src_apll, | |
133 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, | |
3ff31020 JL |
134 | }; |
135 | ||
136 | static struct clksrc_clk clk_sclk_apll = { | |
137 | .clk = { | |
138 | .name = "sclk_apll", | |
3ff31020 JL |
139 | .parent = &clk_mout_apll.clk, |
140 | }, | |
c8bef140 CY |
141 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, |
142 | }; | |
143 | ||
144 | static struct clksrc_clk clk_mout_epll = { | |
145 | .clk = { | |
146 | .name = "mout_epll", | |
c8bef140 CY |
147 | }, |
148 | .sources = &clk_src_epll, | |
149 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, | |
150 | }; | |
151 | ||
152 | static struct clksrc_clk clk_mout_mpll = { | |
153 | .clk = { | |
154 | .name = "mout_mpll", | |
c8bef140 CY |
155 | }, |
156 | .sources = &clk_src_mpll, | |
157 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, | |
158 | }; | |
159 | ||
160 | static struct clk *clkset_moutcore_list[] = { | |
8f3b9cff | 161 | [0] = &clk_mout_apll.clk, |
c8bef140 CY |
162 | [1] = &clk_mout_mpll.clk, |
163 | }; | |
164 | ||
165 | static struct clksrc_sources clkset_moutcore = { | |
166 | .sources = clkset_moutcore_list, | |
167 | .nr_sources = ARRAY_SIZE(clkset_moutcore_list), | |
168 | }; | |
169 | ||
170 | static struct clksrc_clk clk_moutcore = { | |
171 | .clk = { | |
172 | .name = "moutcore", | |
c8bef140 CY |
173 | }, |
174 | .sources = &clkset_moutcore, | |
175 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, | |
176 | }; | |
177 | ||
178 | static struct clksrc_clk clk_coreclk = { | |
179 | .clk = { | |
180 | .name = "core_clk", | |
c8bef140 CY |
181 | .parent = &clk_moutcore.clk, |
182 | }, | |
183 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, | |
184 | }; | |
185 | ||
186 | static struct clksrc_clk clk_armclk = { | |
187 | .clk = { | |
188 | .name = "armclk", | |
c8bef140 CY |
189 | .parent = &clk_coreclk.clk, |
190 | }, | |
191 | }; | |
192 | ||
193 | static struct clksrc_clk clk_aclk_corem0 = { | |
194 | .clk = { | |
195 | .name = "aclk_corem0", | |
c8bef140 CY |
196 | .parent = &clk_coreclk.clk, |
197 | }, | |
198 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, | |
199 | }; | |
200 | ||
201 | static struct clksrc_clk clk_aclk_cores = { | |
202 | .clk = { | |
203 | .name = "aclk_cores", | |
c8bef140 CY |
204 | .parent = &clk_coreclk.clk, |
205 | }, | |
206 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, | |
207 | }; | |
208 | ||
209 | static struct clksrc_clk clk_aclk_corem1 = { | |
210 | .clk = { | |
211 | .name = "aclk_corem1", | |
c8bef140 CY |
212 | .parent = &clk_coreclk.clk, |
213 | }, | |
214 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, | |
215 | }; | |
216 | ||
217 | static struct clksrc_clk clk_periphclk = { | |
218 | .clk = { | |
219 | .name = "periphclk", | |
c8bef140 CY |
220 | .parent = &clk_coreclk.clk, |
221 | }, | |
222 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, | |
223 | }; | |
224 | ||
c8bef140 CY |
225 | /* Core list of CMU_CORE side */ |
226 | ||
227 | static struct clk *clkset_corebus_list[] = { | |
228 | [0] = &clk_mout_mpll.clk, | |
3ff31020 | 229 | [1] = &clk_sclk_apll.clk, |
c8bef140 CY |
230 | }; |
231 | ||
232 | static struct clksrc_sources clkset_mout_corebus = { | |
233 | .sources = clkset_corebus_list, | |
234 | .nr_sources = ARRAY_SIZE(clkset_corebus_list), | |
235 | }; | |
236 | ||
237 | static struct clksrc_clk clk_mout_corebus = { | |
238 | .clk = { | |
239 | .name = "mout_corebus", | |
c8bef140 CY |
240 | }, |
241 | .sources = &clkset_mout_corebus, | |
7af36b97 | 242 | .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, |
c8bef140 CY |
243 | }; |
244 | ||
245 | static struct clksrc_clk clk_sclk_dmc = { | |
246 | .clk = { | |
247 | .name = "sclk_dmc", | |
c8bef140 CY |
248 | .parent = &clk_mout_corebus.clk, |
249 | }, | |
7af36b97 | 250 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, |
c8bef140 CY |
251 | }; |
252 | ||
253 | static struct clksrc_clk clk_aclk_cored = { | |
254 | .clk = { | |
255 | .name = "aclk_cored", | |
c8bef140 CY |
256 | .parent = &clk_sclk_dmc.clk, |
257 | }, | |
7af36b97 | 258 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, |
c8bef140 CY |
259 | }; |
260 | ||
261 | static struct clksrc_clk clk_aclk_corep = { | |
262 | .clk = { | |
263 | .name = "aclk_corep", | |
c8bef140 CY |
264 | .parent = &clk_aclk_cored.clk, |
265 | }, | |
7af36b97 | 266 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, |
c8bef140 CY |
267 | }; |
268 | ||
269 | static struct clksrc_clk clk_aclk_acp = { | |
270 | .clk = { | |
271 | .name = "aclk_acp", | |
c8bef140 CY |
272 | .parent = &clk_mout_corebus.clk, |
273 | }, | |
7af36b97 | 274 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, |
c8bef140 CY |
275 | }; |
276 | ||
277 | static struct clksrc_clk clk_pclk_acp = { | |
278 | .clk = { | |
279 | .name = "pclk_acp", | |
c8bef140 CY |
280 | .parent = &clk_aclk_acp.clk, |
281 | }, | |
7af36b97 | 282 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, |
c8bef140 CY |
283 | }; |
284 | ||
285 | /* Core list of CMU_TOP side */ | |
286 | ||
287 | static struct clk *clkset_aclk_top_list[] = { | |
288 | [0] = &clk_mout_mpll.clk, | |
3ff31020 | 289 | [1] = &clk_sclk_apll.clk, |
c8bef140 CY |
290 | }; |
291 | ||
9e23552f | 292 | static struct clksrc_sources clkset_aclk = { |
c8bef140 CY |
293 | .sources = clkset_aclk_top_list, |
294 | .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), | |
295 | }; | |
296 | ||
297 | static struct clksrc_clk clk_aclk_200 = { | |
298 | .clk = { | |
299 | .name = "aclk_200", | |
c8bef140 | 300 | }, |
9e23552f | 301 | .sources = &clkset_aclk, |
c8bef140 CY |
302 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, |
303 | .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 }, | |
304 | }; | |
305 | ||
c8bef140 CY |
306 | static struct clksrc_clk clk_aclk_100 = { |
307 | .clk = { | |
308 | .name = "aclk_100", | |
c8bef140 | 309 | }, |
9e23552f | 310 | .sources = &clkset_aclk, |
c8bef140 CY |
311 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, |
312 | .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 }, | |
313 | }; | |
314 | ||
c8bef140 CY |
315 | static struct clksrc_clk clk_aclk_160 = { |
316 | .clk = { | |
317 | .name = "aclk_160", | |
c8bef140 | 318 | }, |
9e23552f | 319 | .sources = &clkset_aclk, |
c8bef140 CY |
320 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, |
321 | .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 }, | |
322 | }; | |
323 | ||
c8bef140 CY |
324 | static struct clksrc_clk clk_aclk_133 = { |
325 | .clk = { | |
326 | .name = "aclk_133", | |
c8bef140 | 327 | }, |
9e23552f | 328 | .sources = &clkset_aclk, |
c8bef140 CY |
329 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, |
330 | .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 }, | |
331 | }; | |
332 | ||
333 | static struct clk *clkset_vpllsrc_list[] = { | |
334 | [0] = &clk_fin_vpll, | |
335 | [1] = &clk_sclk_hdmi27m, | |
336 | }; | |
337 | ||
338 | static struct clksrc_sources clkset_vpllsrc = { | |
339 | .sources = clkset_vpllsrc_list, | |
340 | .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list), | |
341 | }; | |
342 | ||
343 | static struct clksrc_clk clk_vpllsrc = { | |
344 | .clk = { | |
345 | .name = "vpll_src", | |
b3ed3a17 | 346 | .enable = exynos4_clksrc_mask_top_ctrl, |
37e01729 | 347 | .ctrlbit = (1 << 0), |
c8bef140 CY |
348 | }, |
349 | .sources = &clkset_vpllsrc, | |
350 | .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 }, | |
351 | }; | |
352 | ||
353 | static struct clk *clkset_sclk_vpll_list[] = { | |
354 | [0] = &clk_vpllsrc.clk, | |
355 | [1] = &clk_fout_vpll, | |
356 | }; | |
357 | ||
358 | static struct clksrc_sources clkset_sclk_vpll = { | |
359 | .sources = clkset_sclk_vpll_list, | |
360 | .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), | |
361 | }; | |
362 | ||
363 | static struct clksrc_clk clk_sclk_vpll = { | |
364 | .clk = { | |
365 | .name = "sclk_vpll", | |
c8bef140 CY |
366 | }, |
367 | .sources = &clkset_sclk_vpll, | |
368 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, | |
369 | }; | |
370 | ||
957c461e | 371 | static struct clk init_clocks_off[] = { |
c8bef140 CY |
372 | { |
373 | .name = "timers", | |
c8bef140 | 374 | .parent = &clk_aclk_100.clk, |
b3ed3a17 | 375 | .enable = exynos4_clk_ip_peril_ctrl, |
c8bef140 | 376 | .ctrlbit = (1<<24), |
82260bf3 JL |
377 | }, { |
378 | .name = "csis", | |
badc4f2d | 379 | .devname = "s5p-mipi-csis.0", |
b3ed3a17 | 380 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
381 | .ctrlbit = (1 << 4), |
382 | }, { | |
383 | .name = "csis", | |
badc4f2d | 384 | .devname = "s5p-mipi-csis.1", |
b3ed3a17 | 385 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
386 | .ctrlbit = (1 << 5), |
387 | }, { | |
388 | .name = "fimc", | |
badc4f2d | 389 | .devname = "exynos4-fimc.0", |
b3ed3a17 | 390 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
391 | .ctrlbit = (1 << 0), |
392 | }, { | |
393 | .name = "fimc", | |
badc4f2d | 394 | .devname = "exynos4-fimc.1", |
b3ed3a17 | 395 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
396 | .ctrlbit = (1 << 1), |
397 | }, { | |
398 | .name = "fimc", | |
badc4f2d | 399 | .devname = "exynos4-fimc.2", |
b3ed3a17 | 400 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
401 | .ctrlbit = (1 << 2), |
402 | }, { | |
403 | .name = "fimc", | |
badc4f2d | 404 | .devname = "exynos4-fimc.3", |
b3ed3a17 | 405 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
406 | .ctrlbit = (1 << 3), |
407 | }, { | |
408 | .name = "fimd", | |
268a7ef2 | 409 | .devname = "exynos4-fb.0", |
b3ed3a17 | 410 | .enable = exynos4_clk_ip_lcd0_ctrl, |
82260bf3 JL |
411 | .ctrlbit = (1 << 0), |
412 | }, { | |
413 | .name = "fimd", | |
268a7ef2 | 414 | .devname = "exynos4-fb.1", |
b3ed3a17 | 415 | .enable = exynos4_clk_ip_lcd1_ctrl, |
82260bf3 | 416 | .ctrlbit = (1 << 0), |
40360217 AK |
417 | }, { |
418 | .name = "sataphy", | |
40360217 AK |
419 | .parent = &clk_aclk_133.clk, |
420 | .enable = exynos4_clk_ip_fsys_ctrl, | |
421 | .ctrlbit = (1 << 3), | |
340ea1ef JL |
422 | }, { |
423 | .name = "hsmmc", | |
badc4f2d | 424 | .devname = "s3c-sdhci.0", |
340ea1ef | 425 | .parent = &clk_aclk_133.clk, |
b3ed3a17 | 426 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
427 | .ctrlbit = (1 << 5), |
428 | }, { | |
429 | .name = "hsmmc", | |
badc4f2d | 430 | .devname = "s3c-sdhci.1", |
340ea1ef | 431 | .parent = &clk_aclk_133.clk, |
b3ed3a17 | 432 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
433 | .ctrlbit = (1 << 6), |
434 | }, { | |
435 | .name = "hsmmc", | |
badc4f2d | 436 | .devname = "s3c-sdhci.2", |
340ea1ef | 437 | .parent = &clk_aclk_133.clk, |
b3ed3a17 | 438 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
439 | .ctrlbit = (1 << 7), |
440 | }, { | |
441 | .name = "hsmmc", | |
badc4f2d | 442 | .devname = "s3c-sdhci.3", |
340ea1ef | 443 | .parent = &clk_aclk_133.clk, |
b3ed3a17 | 444 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
445 | .ctrlbit = (1 << 8), |
446 | }, { | |
badc4f2d | 447 | .name = "dwmmc", |
340ea1ef | 448 | .parent = &clk_aclk_133.clk, |
b3ed3a17 | 449 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef | 450 | .ctrlbit = (1 << 9), |
82260bf3 JL |
451 | }, { |
452 | .name = "sata", | |
40360217 | 453 | .parent = &clk_aclk_133.clk, |
b3ed3a17 | 454 | .enable = exynos4_clk_ip_fsys_ctrl, |
82260bf3 | 455 | .ctrlbit = (1 << 10), |
3055c6da JB |
456 | }, { |
457 | .name = "pdma", | |
badc4f2d | 458 | .devname = "s3c-pl330.0", |
b3ed3a17 | 459 | .enable = exynos4_clk_ip_fsys_ctrl, |
3055c6da JB |
460 | .ctrlbit = (1 << 0), |
461 | }, { | |
462 | .name = "pdma", | |
badc4f2d | 463 | .devname = "s3c-pl330.1", |
b3ed3a17 | 464 | .enable = exynos4_clk_ip_fsys_ctrl, |
3055c6da | 465 | .ctrlbit = (1 << 1), |
82260bf3 JL |
466 | }, { |
467 | .name = "adc", | |
b3ed3a17 | 468 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 | 469 | .ctrlbit = (1 << 15), |
f9d7bcbc NKC |
470 | }, { |
471 | .name = "keypad", | |
f9d7bcbc NKC |
472 | .enable = exynos4_clk_ip_perir_ctrl, |
473 | .ctrlbit = (1 << 16), | |
cdff6e6f CY |
474 | }, { |
475 | .name = "rtc", | |
b3ed3a17 | 476 | .enable = exynos4_clk_ip_perir_ctrl, |
cdff6e6f | 477 | .ctrlbit = (1 << 15), |
82260bf3 JL |
478 | }, { |
479 | .name = "watchdog", | |
f5fb4a20 | 480 | .parent = &clk_aclk_100.clk, |
b3ed3a17 | 481 | .enable = exynos4_clk_ip_perir_ctrl, |
82260bf3 JL |
482 | .ctrlbit = (1 << 14), |
483 | }, { | |
484 | .name = "usbhost", | |
b3ed3a17 | 485 | .enable = exynos4_clk_ip_fsys_ctrl , |
82260bf3 JL |
486 | .ctrlbit = (1 << 12), |
487 | }, { | |
488 | .name = "otg", | |
b3ed3a17 | 489 | .enable = exynos4_clk_ip_fsys_ctrl, |
82260bf3 JL |
490 | .ctrlbit = (1 << 13), |
491 | }, { | |
492 | .name = "spi", | |
badc4f2d | 493 | .devname = "s3c64xx-spi.0", |
b3ed3a17 | 494 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
495 | .ctrlbit = (1 << 16), |
496 | }, { | |
497 | .name = "spi", | |
badc4f2d | 498 | .devname = "s3c64xx-spi.1", |
b3ed3a17 | 499 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
500 | .ctrlbit = (1 << 17), |
501 | }, { | |
502 | .name = "spi", | |
badc4f2d | 503 | .devname = "s3c64xx-spi.2", |
b3ed3a17 | 504 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 | 505 | .ctrlbit = (1 << 18), |
2d27043f JB |
506 | }, { |
507 | .name = "iis", | |
badc4f2d | 508 | .devname = "samsung-i2s.0", |
b3ed3a17 | 509 | .enable = exynos4_clk_ip_peril_ctrl, |
2d27043f JB |
510 | .ctrlbit = (1 << 19), |
511 | }, { | |
512 | .name = "iis", | |
badc4f2d | 513 | .devname = "samsung-i2s.1", |
b3ed3a17 | 514 | .enable = exynos4_clk_ip_peril_ctrl, |
2d27043f JB |
515 | .ctrlbit = (1 << 20), |
516 | }, { | |
517 | .name = "iis", | |
badc4f2d | 518 | .devname = "samsung-i2s.2", |
b3ed3a17 | 519 | .enable = exynos4_clk_ip_peril_ctrl, |
2d27043f | 520 | .ctrlbit = (1 << 21), |
aa227557 JB |
521 | }, { |
522 | .name = "ac97", | |
af8a9f63 | 523 | .devname = "samsung-ac97", |
b3ed3a17 | 524 | .enable = exynos4_clk_ip_peril_ctrl, |
aa227557 | 525 | .ctrlbit = (1 << 27), |
82260bf3 JL |
526 | }, { |
527 | .name = "fimg2d", | |
b3ed3a17 | 528 | .enable = exynos4_clk_ip_image_ctrl, |
82260bf3 | 529 | .ctrlbit = (1 << 0), |
0f75a96b KD |
530 | }, { |
531 | .name = "mfc", | |
532 | .devname = "s5p-mfc", | |
533 | .enable = exynos4_clk_ip_mfc_ctrl, | |
534 | .ctrlbit = (1 << 0), | |
82260bf3 JL |
535 | }, { |
536 | .name = "i2c", | |
badc4f2d | 537 | .devname = "s3c2440-i2c.0", |
82260bf3 | 538 | .parent = &clk_aclk_100.clk, |
b3ed3a17 | 539 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
540 | .ctrlbit = (1 << 6), |
541 | }, { | |
542 | .name = "i2c", | |
badc4f2d | 543 | .devname = "s3c2440-i2c.1", |
82260bf3 | 544 | .parent = &clk_aclk_100.clk, |
b3ed3a17 | 545 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
546 | .ctrlbit = (1 << 7), |
547 | }, { | |
548 | .name = "i2c", | |
badc4f2d | 549 | .devname = "s3c2440-i2c.2", |
82260bf3 | 550 | .parent = &clk_aclk_100.clk, |
b3ed3a17 | 551 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
552 | .ctrlbit = (1 << 8), |
553 | }, { | |
554 | .name = "i2c", | |
badc4f2d | 555 | .devname = "s3c2440-i2c.3", |
82260bf3 | 556 | .parent = &clk_aclk_100.clk, |
b3ed3a17 | 557 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
558 | .ctrlbit = (1 << 9), |
559 | }, { | |
560 | .name = "i2c", | |
badc4f2d | 561 | .devname = "s3c2440-i2c.4", |
82260bf3 | 562 | .parent = &clk_aclk_100.clk, |
b3ed3a17 | 563 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
564 | .ctrlbit = (1 << 10), |
565 | }, { | |
566 | .name = "i2c", | |
badc4f2d | 567 | .devname = "s3c2440-i2c.5", |
82260bf3 | 568 | .parent = &clk_aclk_100.clk, |
b3ed3a17 | 569 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
570 | .ctrlbit = (1 << 11), |
571 | }, { | |
572 | .name = "i2c", | |
badc4f2d | 573 | .devname = "s3c2440-i2c.6", |
82260bf3 | 574 | .parent = &clk_aclk_100.clk, |
b3ed3a17 | 575 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
576 | .ctrlbit = (1 << 12), |
577 | }, { | |
578 | .name = "i2c", | |
badc4f2d | 579 | .devname = "s3c2440-i2c.7", |
82260bf3 | 580 | .parent = &clk_aclk_100.clk, |
b3ed3a17 | 581 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 | 582 | .ctrlbit = (1 << 13), |
b0b6ff0b KC |
583 | }, { |
584 | .name = "SYSMMU_MDMA", | |
b0b6ff0b KC |
585 | .enable = exynos4_clk_ip_image_ctrl, |
586 | .ctrlbit = (1 << 5), | |
587 | }, { | |
588 | .name = "SYSMMU_FIMC0", | |
b0b6ff0b KC |
589 | .enable = exynos4_clk_ip_cam_ctrl, |
590 | .ctrlbit = (1 << 7), | |
591 | }, { | |
592 | .name = "SYSMMU_FIMC1", | |
b0b6ff0b KC |
593 | .enable = exynos4_clk_ip_cam_ctrl, |
594 | .ctrlbit = (1 << 8), | |
595 | }, { | |
596 | .name = "SYSMMU_FIMC2", | |
b0b6ff0b KC |
597 | .enable = exynos4_clk_ip_cam_ctrl, |
598 | .ctrlbit = (1 << 9), | |
599 | }, { | |
600 | .name = "SYSMMU_FIMC3", | |
b0b6ff0b KC |
601 | .enable = exynos4_clk_ip_cam_ctrl, |
602 | .ctrlbit = (1 << 10), | |
603 | }, { | |
604 | .name = "SYSMMU_JPEG", | |
b0b6ff0b KC |
605 | .enable = exynos4_clk_ip_cam_ctrl, |
606 | .ctrlbit = (1 << 11), | |
607 | }, { | |
608 | .name = "SYSMMU_FIMD0", | |
b0b6ff0b KC |
609 | .enable = exynos4_clk_ip_lcd0_ctrl, |
610 | .ctrlbit = (1 << 4), | |
611 | }, { | |
612 | .name = "SYSMMU_FIMD1", | |
b0b6ff0b KC |
613 | .enable = exynos4_clk_ip_lcd1_ctrl, |
614 | .ctrlbit = (1 << 4), | |
615 | }, { | |
616 | .name = "SYSMMU_PCIe", | |
b0b6ff0b KC |
617 | .enable = exynos4_clk_ip_fsys_ctrl, |
618 | .ctrlbit = (1 << 18), | |
619 | }, { | |
620 | .name = "SYSMMU_G2D", | |
b0b6ff0b KC |
621 | .enable = exynos4_clk_ip_image_ctrl, |
622 | .ctrlbit = (1 << 3), | |
623 | }, { | |
624 | .name = "SYSMMU_ROTATOR", | |
b0b6ff0b KC |
625 | .enable = exynos4_clk_ip_image_ctrl, |
626 | .ctrlbit = (1 << 4), | |
627 | }, { | |
628 | .name = "SYSMMU_TV", | |
b0b6ff0b KC |
629 | .enable = exynos4_clk_ip_tv_ctrl, |
630 | .ctrlbit = (1 << 4), | |
631 | }, { | |
632 | .name = "SYSMMU_MFC_L", | |
b0b6ff0b KC |
633 | .enable = exynos4_clk_ip_mfc_ctrl, |
634 | .ctrlbit = (1 << 1), | |
635 | }, { | |
636 | .name = "SYSMMU_MFC_R", | |
b0b6ff0b KC |
637 | .enable = exynos4_clk_ip_mfc_ctrl, |
638 | .ctrlbit = (1 << 2), | |
639 | } | |
c8bef140 CY |
640 | }; |
641 | ||
642 | static struct clk init_clocks[] = { | |
5a847b4a JL |
643 | { |
644 | .name = "uart", | |
badc4f2d | 645 | .devname = "s5pv210-uart.0", |
b3ed3a17 | 646 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
647 | .ctrlbit = (1 << 0), |
648 | }, { | |
649 | .name = "uart", | |
badc4f2d | 650 | .devname = "s5pv210-uart.1", |
b3ed3a17 | 651 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
652 | .ctrlbit = (1 << 1), |
653 | }, { | |
654 | .name = "uart", | |
badc4f2d | 655 | .devname = "s5pv210-uart.2", |
b3ed3a17 | 656 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
657 | .ctrlbit = (1 << 2), |
658 | }, { | |
659 | .name = "uart", | |
badc4f2d | 660 | .devname = "s5pv210-uart.3", |
b3ed3a17 | 661 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
662 | .ctrlbit = (1 << 3), |
663 | }, { | |
664 | .name = "uart", | |
badc4f2d | 665 | .devname = "s5pv210-uart.4", |
b3ed3a17 | 666 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
667 | .ctrlbit = (1 << 4), |
668 | }, { | |
669 | .name = "uart", | |
badc4f2d | 670 | .devname = "s5pv210-uart.5", |
b3ed3a17 | 671 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
672 | .ctrlbit = (1 << 5), |
673 | } | |
c8bef140 CY |
674 | }; |
675 | ||
676 | static struct clk *clkset_group_list[] = { | |
677 | [0] = &clk_ext_xtal_mux, | |
678 | [1] = &clk_xusbxti, | |
679 | [2] = &clk_sclk_hdmi27m, | |
b99380e1 JL |
680 | [3] = &clk_sclk_usbphy0, |
681 | [4] = &clk_sclk_usbphy1, | |
682 | [5] = &clk_sclk_hdmiphy, | |
c8bef140 CY |
683 | [6] = &clk_mout_mpll.clk, |
684 | [7] = &clk_mout_epll.clk, | |
685 | [8] = &clk_sclk_vpll.clk, | |
686 | }; | |
687 | ||
688 | static struct clksrc_sources clkset_group = { | |
689 | .sources = clkset_group_list, | |
690 | .nr_sources = ARRAY_SIZE(clkset_group_list), | |
691 | }; | |
692 | ||
06cba8d5 JL |
693 | static struct clk *clkset_mout_g2d0_list[] = { |
694 | [0] = &clk_mout_mpll.clk, | |
695 | [1] = &clk_sclk_apll.clk, | |
696 | }; | |
697 | ||
698 | static struct clksrc_sources clkset_mout_g2d0 = { | |
699 | .sources = clkset_mout_g2d0_list, | |
700 | .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list), | |
701 | }; | |
702 | ||
703 | static struct clksrc_clk clk_mout_g2d0 = { | |
704 | .clk = { | |
705 | .name = "mout_g2d0", | |
06cba8d5 JL |
706 | }, |
707 | .sources = &clkset_mout_g2d0, | |
708 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, | |
709 | }; | |
710 | ||
711 | static struct clk *clkset_mout_g2d1_list[] = { | |
712 | [0] = &clk_mout_epll.clk, | |
713 | [1] = &clk_sclk_vpll.clk, | |
714 | }; | |
715 | ||
716 | static struct clksrc_sources clkset_mout_g2d1 = { | |
717 | .sources = clkset_mout_g2d1_list, | |
718 | .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list), | |
719 | }; | |
720 | ||
721 | static struct clksrc_clk clk_mout_g2d1 = { | |
722 | .clk = { | |
723 | .name = "mout_g2d1", | |
06cba8d5 JL |
724 | }, |
725 | .sources = &clkset_mout_g2d1, | |
726 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, | |
727 | }; | |
728 | ||
729 | static struct clk *clkset_mout_g2d_list[] = { | |
730 | [0] = &clk_mout_g2d0.clk, | |
731 | [1] = &clk_mout_g2d1.clk, | |
732 | }; | |
733 | ||
734 | static struct clksrc_sources clkset_mout_g2d = { | |
735 | .sources = clkset_mout_g2d_list, | |
736 | .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list), | |
737 | }; | |
738 | ||
0f75a96b KD |
739 | static struct clk *clkset_mout_mfc0_list[] = { |
740 | [0] = &clk_mout_mpll.clk, | |
741 | [1] = &clk_sclk_apll.clk, | |
742 | }; | |
743 | ||
744 | static struct clksrc_sources clkset_mout_mfc0 = { | |
745 | .sources = clkset_mout_mfc0_list, | |
746 | .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list), | |
747 | }; | |
748 | ||
749 | static struct clksrc_clk clk_mout_mfc0 = { | |
750 | .clk = { | |
751 | .name = "mout_mfc0", | |
752 | }, | |
753 | .sources = &clkset_mout_mfc0, | |
754 | .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 }, | |
755 | }; | |
756 | ||
757 | static struct clk *clkset_mout_mfc1_list[] = { | |
758 | [0] = &clk_mout_epll.clk, | |
759 | [1] = &clk_sclk_vpll.clk, | |
760 | }; | |
761 | ||
762 | static struct clksrc_sources clkset_mout_mfc1 = { | |
763 | .sources = clkset_mout_mfc1_list, | |
764 | .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list), | |
765 | }; | |
766 | ||
767 | static struct clksrc_clk clk_mout_mfc1 = { | |
768 | .clk = { | |
769 | .name = "mout_mfc1", | |
770 | }, | |
771 | .sources = &clkset_mout_mfc1, | |
772 | .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 }, | |
773 | }; | |
774 | ||
775 | static struct clk *clkset_mout_mfc_list[] = { | |
776 | [0] = &clk_mout_mfc0.clk, | |
777 | [1] = &clk_mout_mfc1.clk, | |
778 | }; | |
779 | ||
780 | static struct clksrc_sources clkset_mout_mfc = { | |
781 | .sources = clkset_mout_mfc_list, | |
782 | .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list), | |
783 | }; | |
784 | ||
340ea1ef JL |
785 | static struct clksrc_clk clk_dout_mmc0 = { |
786 | .clk = { | |
787 | .name = "dout_mmc0", | |
340ea1ef JL |
788 | }, |
789 | .sources = &clkset_group, | |
790 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, | |
791 | .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 }, | |
792 | }; | |
793 | ||
794 | static struct clksrc_clk clk_dout_mmc1 = { | |
795 | .clk = { | |
796 | .name = "dout_mmc1", | |
340ea1ef JL |
797 | }, |
798 | .sources = &clkset_group, | |
799 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, | |
800 | .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 }, | |
801 | }; | |
802 | ||
803 | static struct clksrc_clk clk_dout_mmc2 = { | |
804 | .clk = { | |
805 | .name = "dout_mmc2", | |
340ea1ef JL |
806 | }, |
807 | .sources = &clkset_group, | |
808 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, | |
809 | .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 }, | |
810 | }; | |
811 | ||
812 | static struct clksrc_clk clk_dout_mmc3 = { | |
813 | .clk = { | |
814 | .name = "dout_mmc3", | |
340ea1ef JL |
815 | }, |
816 | .sources = &clkset_group, | |
817 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, | |
818 | .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 }, | |
819 | }; | |
820 | ||
821 | static struct clksrc_clk clk_dout_mmc4 = { | |
822 | .clk = { | |
823 | .name = "dout_mmc4", | |
340ea1ef JL |
824 | }, |
825 | .sources = &clkset_group, | |
826 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, | |
827 | .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 }, | |
828 | }; | |
829 | ||
c8bef140 CY |
830 | static struct clksrc_clk clksrcs[] = { |
831 | { | |
832 | .clk = { | |
833 | .name = "uclk1", | |
badc4f2d | 834 | .devname = "s5pv210-uart.0", |
b3ed3a17 | 835 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
5a847b4a | 836 | .ctrlbit = (1 << 0), |
c8bef140 CY |
837 | }, |
838 | .sources = &clkset_group, | |
839 | .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 }, | |
840 | .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 }, | |
841 | }, { | |
842 | .clk = { | |
843 | .name = "uclk1", | |
badc4f2d | 844 | .devname = "s5pv210-uart.1", |
b3ed3a17 | 845 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
3297c2e6 | 846 | .ctrlbit = (1 << 4), |
c8bef140 CY |
847 | }, |
848 | .sources = &clkset_group, | |
849 | .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 }, | |
850 | .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 }, | |
851 | }, { | |
852 | .clk = { | |
853 | .name = "uclk1", | |
badc4f2d | 854 | .devname = "s5pv210-uart.2", |
b3ed3a17 | 855 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
3297c2e6 | 856 | .ctrlbit = (1 << 8), |
c8bef140 CY |
857 | }, |
858 | .sources = &clkset_group, | |
859 | .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 }, | |
860 | .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 }, | |
861 | }, { | |
862 | .clk = { | |
863 | .name = "uclk1", | |
badc4f2d | 864 | .devname = "s5pv210-uart.3", |
b3ed3a17 | 865 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
3297c2e6 | 866 | .ctrlbit = (1 << 12), |
c8bef140 CY |
867 | }, |
868 | .sources = &clkset_group, | |
869 | .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 }, | |
870 | .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, | |
871 | }, { | |
872 | .clk = { | |
873 | .name = "sclk_pwm", | |
b3ed3a17 | 874 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
c8bef140 CY |
875 | .ctrlbit = (1 << 24), |
876 | }, | |
877 | .sources = &clkset_group, | |
878 | .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 }, | |
879 | .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 }, | |
33f469d2 JL |
880 | }, { |
881 | .clk = { | |
882 | .name = "sclk_csis", | |
badc4f2d | 883 | .devname = "s5p-mipi-csis.0", |
b3ed3a17 | 884 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
885 | .ctrlbit = (1 << 24), |
886 | }, | |
887 | .sources = &clkset_group, | |
888 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 }, | |
889 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 }, | |
890 | }, { | |
891 | .clk = { | |
892 | .name = "sclk_csis", | |
badc4f2d | 893 | .devname = "s5p-mipi-csis.1", |
b3ed3a17 | 894 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
895 | .ctrlbit = (1 << 28), |
896 | }, | |
897 | .sources = &clkset_group, | |
898 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 }, | |
899 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 }, | |
900 | }, { | |
901 | .clk = { | |
00aaad22 | 902 | .name = "sclk_cam0", |
b3ed3a17 | 903 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
904 | .ctrlbit = (1 << 16), |
905 | }, | |
906 | .sources = &clkset_group, | |
907 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 }, | |
908 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 }, | |
909 | }, { | |
910 | .clk = { | |
00aaad22 | 911 | .name = "sclk_cam1", |
b3ed3a17 | 912 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
913 | .ctrlbit = (1 << 20), |
914 | }, | |
915 | .sources = &clkset_group, | |
916 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 }, | |
917 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 }, | |
918 | }, { | |
919 | .clk = { | |
920 | .name = "sclk_fimc", | |
badc4f2d | 921 | .devname = "exynos4-fimc.0", |
b3ed3a17 | 922 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
923 | .ctrlbit = (1 << 0), |
924 | }, | |
925 | .sources = &clkset_group, | |
926 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 }, | |
927 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 }, | |
928 | }, { | |
929 | .clk = { | |
930 | .name = "sclk_fimc", | |
badc4f2d | 931 | .devname = "exynos4-fimc.1", |
b3ed3a17 | 932 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
933 | .ctrlbit = (1 << 4), |
934 | }, | |
935 | .sources = &clkset_group, | |
936 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 }, | |
937 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 }, | |
938 | }, { | |
939 | .clk = { | |
940 | .name = "sclk_fimc", | |
badc4f2d | 941 | .devname = "exynos4-fimc.2", |
b3ed3a17 | 942 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
943 | .ctrlbit = (1 << 8), |
944 | }, | |
945 | .sources = &clkset_group, | |
946 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 }, | |
947 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 }, | |
948 | }, { | |
949 | .clk = { | |
950 | .name = "sclk_fimc", | |
badc4f2d | 951 | .devname = "exynos4-fimc.3", |
b3ed3a17 | 952 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
953 | .ctrlbit = (1 << 12), |
954 | }, | |
955 | .sources = &clkset_group, | |
956 | .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 }, | |
957 | .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 }, | |
958 | }, { | |
959 | .clk = { | |
960 | .name = "sclk_fimd", | |
268a7ef2 | 961 | .devname = "exynos4-fb.0", |
b3ed3a17 | 962 | .enable = exynos4_clksrc_mask_lcd0_ctrl, |
33f469d2 JL |
963 | .ctrlbit = (1 << 0), |
964 | }, | |
965 | .sources = &clkset_group, | |
966 | .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 }, | |
967 | .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 }, | |
968 | }, { | |
969 | .clk = { | |
970 | .name = "sclk_fimd", | |
268a7ef2 | 971 | .devname = "exynos4-fb.1", |
b3ed3a17 | 972 | .enable = exynos4_clksrc_mask_lcd1_ctrl, |
33f469d2 JL |
973 | .ctrlbit = (1 << 0), |
974 | }, | |
975 | .sources = &clkset_group, | |
976 | .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 }, | |
977 | .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 }, | |
978 | }, { | |
979 | .clk = { | |
980 | .name = "sclk_sata", | |
b3ed3a17 | 981 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
33f469d2 JL |
982 | .ctrlbit = (1 << 24), |
983 | }, | |
984 | .sources = &clkset_mout_corebus, | |
985 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 }, | |
986 | .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 }, | |
987 | }, { | |
988 | .clk = { | |
989 | .name = "sclk_spi", | |
badc4f2d | 990 | .devname = "s3c64xx-spi.0", |
b3ed3a17 | 991 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
33f469d2 JL |
992 | .ctrlbit = (1 << 16), |
993 | }, | |
994 | .sources = &clkset_group, | |
995 | .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 }, | |
996 | .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 }, | |
997 | }, { | |
998 | .clk = { | |
999 | .name = "sclk_spi", | |
badc4f2d | 1000 | .devname = "s3c64xx-spi.1", |
b3ed3a17 | 1001 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
33f469d2 JL |
1002 | .ctrlbit = (1 << 20), |
1003 | }, | |
1004 | .sources = &clkset_group, | |
1005 | .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 }, | |
1006 | .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 }, | |
1007 | }, { | |
1008 | .clk = { | |
1009 | .name = "sclk_spi", | |
badc4f2d | 1010 | .devname = "s3c64xx-spi.2", |
b3ed3a17 | 1011 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
33f469d2 JL |
1012 | .ctrlbit = (1 << 24), |
1013 | }, | |
1014 | .sources = &clkset_group, | |
1015 | .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 }, | |
1016 | .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 }, | |
1017 | }, { | |
1018 | .clk = { | |
1019 | .name = "sclk_fimg2d", | |
33f469d2 JL |
1020 | }, |
1021 | .sources = &clkset_mout_g2d, | |
1022 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, | |
1023 | .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 }, | |
0f75a96b KD |
1024 | }, { |
1025 | .clk = { | |
1026 | .name = "sclk_mfc", | |
1027 | .devname = "s5p-mfc", | |
1028 | }, | |
1029 | .sources = &clkset_mout_mfc, | |
1030 | .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 }, | |
1031 | .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, | |
340ea1ef JL |
1032 | }, { |
1033 | .clk = { | |
1034 | .name = "sclk_mmc", | |
badc4f2d | 1035 | .devname = "s3c-sdhci.0", |
340ea1ef | 1036 | .parent = &clk_dout_mmc0.clk, |
b3ed3a17 | 1037 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
340ea1ef JL |
1038 | .ctrlbit = (1 << 0), |
1039 | }, | |
1040 | .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, | |
1041 | }, { | |
1042 | .clk = { | |
1043 | .name = "sclk_mmc", | |
badc4f2d | 1044 | .devname = "s3c-sdhci.1", |
340ea1ef | 1045 | .parent = &clk_dout_mmc1.clk, |
b3ed3a17 | 1046 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
340ea1ef JL |
1047 | .ctrlbit = (1 << 4), |
1048 | }, | |
1049 | .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, | |
1050 | }, { | |
1051 | .clk = { | |
1052 | .name = "sclk_mmc", | |
badc4f2d | 1053 | .devname = "s3c-sdhci.2", |
340ea1ef | 1054 | .parent = &clk_dout_mmc2.clk, |
b3ed3a17 | 1055 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
340ea1ef JL |
1056 | .ctrlbit = (1 << 8), |
1057 | }, | |
1058 | .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, | |
1059 | }, { | |
1060 | .clk = { | |
1061 | .name = "sclk_mmc", | |
badc4f2d | 1062 | .devname = "s3c-sdhci.3", |
340ea1ef | 1063 | .parent = &clk_dout_mmc3.clk, |
b3ed3a17 | 1064 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
340ea1ef JL |
1065 | .ctrlbit = (1 << 12), |
1066 | }, | |
1067 | .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, | |
1068 | }, { | |
1069 | .clk = { | |
badc4f2d | 1070 | .name = "sclk_dwmmc", |
340ea1ef | 1071 | .parent = &clk_dout_mmc4.clk, |
b3ed3a17 | 1072 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
340ea1ef JL |
1073 | .ctrlbit = (1 << 16), |
1074 | }, | |
1075 | .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 }, | |
1076 | } | |
c8bef140 CY |
1077 | }; |
1078 | ||
1079 | /* Clock initialization code */ | |
1080 | static struct clksrc_clk *sysclks[] = { | |
1081 | &clk_mout_apll, | |
3ff31020 | 1082 | &clk_sclk_apll, |
c8bef140 CY |
1083 | &clk_mout_epll, |
1084 | &clk_mout_mpll, | |
1085 | &clk_moutcore, | |
1086 | &clk_coreclk, | |
1087 | &clk_armclk, | |
1088 | &clk_aclk_corem0, | |
1089 | &clk_aclk_cores, | |
1090 | &clk_aclk_corem1, | |
1091 | &clk_periphclk, | |
c8bef140 CY |
1092 | &clk_mout_corebus, |
1093 | &clk_sclk_dmc, | |
1094 | &clk_aclk_cored, | |
1095 | &clk_aclk_corep, | |
1096 | &clk_aclk_acp, | |
1097 | &clk_pclk_acp, | |
1098 | &clk_vpllsrc, | |
1099 | &clk_sclk_vpll, | |
1100 | &clk_aclk_200, | |
1101 | &clk_aclk_100, | |
1102 | &clk_aclk_160, | |
1103 | &clk_aclk_133, | |
340ea1ef JL |
1104 | &clk_dout_mmc0, |
1105 | &clk_dout_mmc1, | |
1106 | &clk_dout_mmc2, | |
1107 | &clk_dout_mmc3, | |
1108 | &clk_dout_mmc4, | |
0f75a96b KD |
1109 | &clk_mout_mfc0, |
1110 | &clk_mout_mfc1, | |
c8bef140 CY |
1111 | }; |
1112 | ||
877d1b57 JL |
1113 | static int xtal_rate; |
1114 | ||
b3ed3a17 | 1115 | static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) |
877d1b57 JL |
1116 | { |
1117 | return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); | |
1118 | } | |
1119 | ||
b3ed3a17 KK |
1120 | static struct clk_ops exynos4_fout_apll_ops = { |
1121 | .get_rate = exynos4_fout_apll_get_rate, | |
877d1b57 JL |
1122 | }; |
1123 | ||
b3ed3a17 | 1124 | void __init_or_cpufreq exynos4_setup_clocks(void) |
c8bef140 CY |
1125 | { |
1126 | struct clk *xtal_clk; | |
1127 | unsigned long apll; | |
1128 | unsigned long mpll; | |
1129 | unsigned long epll; | |
1130 | unsigned long vpll; | |
1131 | unsigned long vpllsrc; | |
1132 | unsigned long xtal; | |
1133 | unsigned long armclk; | |
c8bef140 | 1134 | unsigned long sclk_dmc; |
228ef987 JL |
1135 | unsigned long aclk_200; |
1136 | unsigned long aclk_100; | |
1137 | unsigned long aclk_160; | |
1138 | unsigned long aclk_133; | |
c8bef140 CY |
1139 | unsigned int ptr; |
1140 | ||
1141 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | |
1142 | ||
1143 | xtal_clk = clk_get(NULL, "xtal"); | |
1144 | BUG_ON(IS_ERR(xtal_clk)); | |
1145 | ||
1146 | xtal = clk_get_rate(xtal_clk); | |
877d1b57 JL |
1147 | |
1148 | xtal_rate = xtal; | |
1149 | ||
c8bef140 CY |
1150 | clk_put(xtal_clk); |
1151 | ||
1152 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | |
1153 | ||
1154 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508); | |
1155 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508); | |
1156 | epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), | |
4d235f79 | 1157 | __raw_readl(S5P_EPLL_CON1), pll_4600); |
c8bef140 CY |
1158 | |
1159 | vpllsrc = clk_get_rate(&clk_vpllsrc.clk); | |
1160 | vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), | |
6861a197 | 1161 | __raw_readl(S5P_VPLL_CON1), pll_4650c); |
c8bef140 | 1162 | |
b3ed3a17 | 1163 | clk_fout_apll.ops = &exynos4_fout_apll_ops; |
c8bef140 CY |
1164 | clk_fout_mpll.rate = mpll; |
1165 | clk_fout_epll.rate = epll; | |
1166 | clk_fout_vpll.rate = vpll; | |
1167 | ||
b3ed3a17 | 1168 | printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", |
c8bef140 CY |
1169 | apll, mpll, epll, vpll); |
1170 | ||
1171 | armclk = clk_get_rate(&clk_armclk.clk); | |
c8bef140 | 1172 | sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk); |
a6aa7a55 | 1173 | |
228ef987 JL |
1174 | aclk_200 = clk_get_rate(&clk_aclk_200.clk); |
1175 | aclk_100 = clk_get_rate(&clk_aclk_100.clk); | |
1176 | aclk_160 = clk_get_rate(&clk_aclk_160.clk); | |
1177 | aclk_133 = clk_get_rate(&clk_aclk_133.clk); | |
1178 | ||
b3ed3a17 | 1179 | printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" |
228ef987 JL |
1180 | "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", |
1181 | armclk, sclk_dmc, aclk_200, | |
1182 | aclk_100, aclk_160, aclk_133); | |
c8bef140 CY |
1183 | |
1184 | clk_f.rate = armclk; | |
1185 | clk_h.rate = sclk_dmc; | |
228ef987 | 1186 | clk_p.rate = aclk_100; |
c8bef140 CY |
1187 | |
1188 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | |
1189 | s3c_set_clksrc(&clksrcs[ptr], true); | |
1190 | } | |
1191 | ||
1192 | static struct clk *clks[] __initdata = { | |
1193 | /* Nothing here yet */ | |
1194 | }; | |
1195 | ||
b3ed3a17 | 1196 | void __init exynos4_register_clocks(void) |
c8bef140 | 1197 | { |
c8bef140 CY |
1198 | int ptr; |
1199 | ||
957c461e | 1200 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
c8bef140 CY |
1201 | |
1202 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) | |
1203 | s3c_register_clksrc(sysclks[ptr], 1); | |
1204 | ||
1205 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | |
1206 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | |
1207 | ||
957c461e KK |
1208 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
1209 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | |
c8bef140 CY |
1210 | |
1211 | s3c_pwmclk_init(); | |
1212 | } |