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699efdd2 JK |
1 | /* linux/arch/arm/mach-exynos4/mach-origen.c |
2 | * | |
3 | * Copyright (c) 2011 Insignal Co., Ltd. | |
4 | * http://www.insignal.co.kr/ | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/serial_core.h> | |
12 | #include <linux/gpio.h> | |
13 | #include <linux/mmc/host.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/input.h> | |
9edff0f7 | 17 | #include <linux/pwm_backlight.h> |
c86cfdd0 | 18 | #include <linux/gpio_keys.h> |
699efdd2 JK |
19 | |
20 | #include <asm/mach/arch.h> | |
21 | #include <asm/mach-types.h> | |
22 | ||
23 | #include <plat/regs-serial.h> | |
24 | #include <plat/exynos4.h> | |
25 | #include <plat/cpu.h> | |
26 | #include <plat/devs.h> | |
27 | #include <plat/sdhci.h> | |
28 | #include <plat/iic.h> | |
24f9e1f3 SK |
29 | #include <plat/ehci.h> |
30 | #include <plat/clock.h> | |
9edff0f7 GM |
31 | #include <plat/gpio-cfg.h> |
32 | #include <plat/backlight.h> | |
699efdd2 JK |
33 | |
34 | #include <mach/map.h> | |
35 | ||
36 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | |
37 | #define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | |
38 | S3C2410_UCON_RXILEVEL | \ | |
39 | S3C2410_UCON_TXIRQMODE | \ | |
40 | S3C2410_UCON_RXIRQMODE | \ | |
41 | S3C2410_UCON_RXFIFO_TOI | \ | |
42 | S3C2443_UCON_RXERR_IRQEN) | |
43 | ||
44 | #define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8 | |
45 | ||
46 | #define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | |
47 | S5PV210_UFCON_TXTRIG4 | \ | |
48 | S5PV210_UFCON_RXTRIG4) | |
49 | ||
50 | static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = { | |
51 | [0] = { | |
52 | .hwport = 0, | |
53 | .flags = 0, | |
54 | .ucon = ORIGEN_UCON_DEFAULT, | |
55 | .ulcon = ORIGEN_ULCON_DEFAULT, | |
56 | .ufcon = ORIGEN_UFCON_DEFAULT, | |
57 | }, | |
58 | [1] = { | |
59 | .hwport = 1, | |
60 | .flags = 0, | |
61 | .ucon = ORIGEN_UCON_DEFAULT, | |
62 | .ulcon = ORIGEN_ULCON_DEFAULT, | |
63 | .ufcon = ORIGEN_UFCON_DEFAULT, | |
64 | }, | |
65 | [2] = { | |
66 | .hwport = 2, | |
67 | .flags = 0, | |
68 | .ucon = ORIGEN_UCON_DEFAULT, | |
69 | .ulcon = ORIGEN_ULCON_DEFAULT, | |
70 | .ufcon = ORIGEN_UFCON_DEFAULT, | |
71 | }, | |
72 | [3] = { | |
73 | .hwport = 3, | |
74 | .flags = 0, | |
75 | .ucon = ORIGEN_UCON_DEFAULT, | |
76 | .ulcon = ORIGEN_ULCON_DEFAULT, | |
77 | .ufcon = ORIGEN_UFCON_DEFAULT, | |
78 | }, | |
79 | }; | |
80 | ||
cf1dad9d TB |
81 | static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = { |
82 | .cd_type = S3C_SDHCI_CD_INTERNAL, | |
83 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, | |
84 | }; | |
85 | ||
699efdd2 | 86 | static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = { |
92e41efd | 87 | .cd_type = S3C_SDHCI_CD_INTERNAL, |
699efdd2 JK |
88 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, |
89 | }; | |
90 | ||
24f9e1f3 SK |
91 | /* USB EHCI */ |
92 | static struct s5p_ehci_platdata origen_ehci_pdata; | |
93 | ||
94 | static void __init origen_ehci_init(void) | |
95 | { | |
96 | struct s5p_ehci_platdata *pdata = &origen_ehci_pdata; | |
97 | ||
98 | s5p_ehci_set_platdata(pdata); | |
99 | } | |
100 | ||
c86cfdd0 SK |
101 | static struct gpio_keys_button origen_gpio_keys_table[] = { |
102 | { | |
103 | .code = KEY_MENU, | |
104 | .gpio = EXYNOS4_GPX1(5), | |
105 | .desc = "gpio-keys: KEY_MENU", | |
106 | .type = EV_KEY, | |
107 | .active_low = 1, | |
108 | .wakeup = 1, | |
109 | .debounce_interval = 1, | |
110 | }, { | |
111 | .code = KEY_HOME, | |
112 | .gpio = EXYNOS4_GPX1(6), | |
113 | .desc = "gpio-keys: KEY_HOME", | |
114 | .type = EV_KEY, | |
115 | .active_low = 1, | |
116 | .wakeup = 1, | |
117 | .debounce_interval = 1, | |
118 | }, { | |
119 | .code = KEY_BACK, | |
120 | .gpio = EXYNOS4_GPX1(7), | |
121 | .desc = "gpio-keys: KEY_BACK", | |
122 | .type = EV_KEY, | |
123 | .active_low = 1, | |
124 | .wakeup = 1, | |
125 | .debounce_interval = 1, | |
126 | }, { | |
127 | .code = KEY_UP, | |
128 | .gpio = EXYNOS4_GPX2(0), | |
129 | .desc = "gpio-keys: KEY_UP", | |
130 | .type = EV_KEY, | |
131 | .active_low = 1, | |
132 | .wakeup = 1, | |
133 | .debounce_interval = 1, | |
134 | }, { | |
135 | .code = KEY_DOWN, | |
136 | .gpio = EXYNOS4_GPX2(1), | |
137 | .desc = "gpio-keys: KEY_DOWN", | |
138 | .type = EV_KEY, | |
139 | .active_low = 1, | |
140 | .wakeup = 1, | |
141 | .debounce_interval = 1, | |
142 | }, | |
143 | }; | |
144 | ||
145 | static struct gpio_keys_platform_data origen_gpio_keys_data = { | |
146 | .buttons = origen_gpio_keys_table, | |
147 | .nbuttons = ARRAY_SIZE(origen_gpio_keys_table), | |
148 | }; | |
149 | ||
150 | static struct platform_device origen_device_gpiokeys = { | |
151 | .name = "gpio-keys", | |
152 | .dev = { | |
153 | .platform_data = &origen_gpio_keys_data, | |
154 | }, | |
155 | }; | |
156 | ||
699efdd2 JK |
157 | static struct platform_device *origen_devices[] __initdata = { |
158 | &s3c_device_hsmmc2, | |
cf1dad9d | 159 | &s3c_device_hsmmc0, |
699efdd2 JK |
160 | &s3c_device_rtc, |
161 | &s3c_device_wdt, | |
24f9e1f3 | 162 | &s5p_device_ehci, |
6f8eb324 SK |
163 | &s5p_device_fimc0, |
164 | &s5p_device_fimc1, | |
165 | &s5p_device_fimc2, | |
166 | &s5p_device_fimc3, | |
c86cfdd0 | 167 | &origen_device_gpiokeys, |
699efdd2 JK |
168 | }; |
169 | ||
9edff0f7 GM |
170 | /* LCD Backlight data */ |
171 | static struct samsung_bl_gpio_info origen_bl_gpio_info = { | |
172 | .no = EXYNOS4_GPD0(0), | |
173 | .func = S3C_GPIO_SFN(2), | |
174 | }; | |
175 | ||
176 | static struct platform_pwm_backlight_data origen_bl_data = { | |
177 | .pwm_id = 0, | |
178 | .pwm_period_ns = 1000, | |
179 | }; | |
180 | ||
699efdd2 JK |
181 | static void __init origen_map_io(void) |
182 | { | |
183 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); | |
184 | s3c24xx_init_clocks(24000000); | |
185 | s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); | |
186 | } | |
187 | ||
188 | static void __init origen_machine_init(void) | |
189 | { | |
cf1dad9d TB |
190 | /* |
191 | * Since sdhci instance 2 can contain a bootable media, | |
192 | * sdhci instance 0 is registered after instance 2. | |
193 | */ | |
699efdd2 | 194 | s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata); |
cf1dad9d | 195 | s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata); |
24f9e1f3 SK |
196 | |
197 | origen_ehci_init(); | |
198 | clk_xusbxti.rate = 24000000; | |
199 | ||
699efdd2 | 200 | platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices)); |
9edff0f7 GM |
201 | |
202 | samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data); | |
699efdd2 JK |
203 | } |
204 | ||
205 | MACHINE_START(ORIGEN, "ORIGEN") | |
206 | /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */ | |
207 | .boot_params = S5P_PA_SDRAM + 0x100, | |
208 | .init_irq = exynos4_init_irq, | |
209 | .map_io = origen_map_io, | |
210 | .init_machine = origen_machine_init, | |
211 | .timer = &exynos4_timer, | |
212 | MACHINE_END |