Commit | Line | Data |
---|---|---|
e038ed50 | 1 | #include <linux/clk.h> |
c349adde | 2 | #include <linux/clk-provider.h> |
e038ed50 SH |
3 | #include <linux/clkdev.h> |
4 | #include <linux/err.h> | |
e038ed50 | 5 | #include <linux/of.h> |
c349adde | 6 | #include <linux/of_address.h> |
e8e3faa0 | 7 | #include <dt-bindings/clock/imx27-clock.h> |
0c831317 SG |
8 | #include <soc/imx/revision.h> |
9 | #include <asm/irq.h> | |
e038ed50 | 10 | |
e038ed50 | 11 | #include "clk.h" |
0c831317 SG |
12 | |
13 | #define MX27_CCM_BASE_ADDR 0x10027000 | |
14 | #define MX27_GPT1_BASE_ADDR 0x10003000 | |
15 | #define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26) | |
e038ed50 | 16 | |
c349adde | 17 | static void __iomem *ccm __initdata; |
e038ed50 SH |
18 | |
19 | /* Register offsets */ | |
c349adde AS |
20 | #define CCM_CSCR (ccm + 0x00) |
21 | #define CCM_MPCTL0 (ccm + 0x04) | |
22 | #define CCM_MPCTL1 (ccm + 0x08) | |
23 | #define CCM_SPCTL0 (ccm + 0x0c) | |
24 | #define CCM_SPCTL1 (ccm + 0x10) | |
c349adde AS |
25 | #define CCM_PCDR0 (ccm + 0x18) |
26 | #define CCM_PCDR1 (ccm + 0x1c) | |
27 | #define CCM_PCCR0 (ccm + 0x20) | |
28 | #define CCM_PCCR1 (ccm + 0x24) | |
29 | #define CCM_CCSR (ccm + 0x28) | |
e038ed50 SH |
30 | |
31 | static const char *vpu_sel_clks[] = { "spll", "mpll_main2", }; | |
32 | static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", }; | |
4ea9e857 | 33 | static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", }; |
b4de5317 | 34 | static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", }; |
e038ed50 | 35 | static const char *clko_sel_clks[] = { |
b4de5317 AS |
36 | "ckil", "fpm", "ckih_gate", "ckih_gate", |
37 | "ckih_gate", "mpll", "spll", "cpu_div", | |
e038ed50 SH |
38 | "ahb", "ipg", "per1_div", "per2_div", |
39 | "per3_div", "per4_div", "ssi1_div", "ssi2_div", | |
40 | "nfc_div", "mshc_div", "vpu_div", "60m", | |
41 | "32k", "usb_div", "dptc", | |
42 | }; | |
43 | ||
b7eed207 | 44 | static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; |
e038ed50 | 45 | |
e8e3faa0 | 46 | static struct clk *clk[IMX27_CLK_MAX]; |
c20736f1 | 47 | static struct clk_onecell_data clk_data; |
e038ed50 | 48 | |
bb9c3398 | 49 | static void __init _mx27_clocks_init(unsigned long fref) |
e038ed50 | 50 | { |
c349adde AS |
51 | BUG_ON(!ccm); |
52 | ||
e8e3faa0 AS |
53 | clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); |
54 | clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); | |
55 | clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); | |
56 | clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); | |
b4de5317 AS |
57 | clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); |
58 | clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); | |
e8e3faa0 AS |
59 | clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks)); |
60 | clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks)); | |
3bec5f81 SG |
61 | clk[IMX27_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "mpll", "mpll_sel", CCM_MPCTL0); |
62 | clk[IMX27_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "spll", "ckih_gate", CCM_SPCTL0); | |
e8e3faa0 AS |
63 | clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); |
64 | clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); | |
e038ed50 SH |
65 | |
66 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { | |
e8e3faa0 AS |
67 | clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); |
68 | clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); | |
e038ed50 | 69 | } else { |
e8e3faa0 AS |
70 | clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); |
71 | clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); | |
e038ed50 SH |
72 | } |
73 | ||
e8e3faa0 AS |
74 | clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); |
75 | clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); | |
76 | clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6); | |
77 | clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6); | |
78 | clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6); | |
79 | clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); | |
80 | clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); | |
81 | clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); | |
82 | clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3); | |
83 | clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); | |
84 | clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); | |
85 | ||
e038ed50 | 86 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) |
e8e3faa0 | 87 | clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2); |
e038ed50 | 88 | else |
e8e3faa0 AS |
89 | clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3); |
90 | ||
91 | clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3); | |
92 | clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); | |
93 | clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); | |
94 | clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); | |
95 | clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); | |
96 | clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0); | |
97 | clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0); | |
98 | clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1); | |
99 | clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2); | |
100 | clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3); | |
101 | clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4); | |
102 | clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5); | |
103 | clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6); | |
104 | clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7); | |
105 | clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8); | |
106 | clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9); | |
107 | clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11); | |
108 | clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12); | |
109 | clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13); | |
110 | clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14); | |
111 | clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15); | |
112 | clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16); | |
113 | clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17); | |
114 | clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18); | |
115 | clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19); | |
116 | clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20); | |
117 | clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21); | |
118 | clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22); | |
119 | clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23); | |
120 | clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24); | |
121 | clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25); | |
122 | clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26); | |
123 | clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27); | |
124 | clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28); | |
125 | clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29); | |
126 | clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30); | |
127 | clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31); | |
128 | clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2); | |
129 | clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3); | |
130 | clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4); | |
131 | clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5); | |
132 | clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6); | |
133 | clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7); | |
134 | clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8); | |
135 | clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9); | |
136 | clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10); | |
137 | clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); | |
138 | clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); | |
139 | clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); | |
140 | clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14); | |
141 | clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15); | |
142 | clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16); | |
143 | clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17); | |
144 | clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18); | |
145 | clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19); | |
146 | clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20); | |
147 | clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21); | |
148 | clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22); | |
149 | clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23); | |
150 | clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24); | |
151 | clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25); | |
152 | clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26); | |
153 | clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27); | |
154 | clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28); | |
155 | clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29); | |
156 | clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30); | |
157 | clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31); | |
e038ed50 | 158 | |
229be9c1 | 159 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
e038ed50 | 160 | |
e8e3faa0 | 161 | clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0"); |
bb9c3398 | 162 | |
e8e3faa0 | 163 | clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); |
bb9c3398 AS |
164 | |
165 | imx_print_silicon_rev("i.MX27", mx27_revision()); | |
166 | } | |
167 | ||
168 | int __init mx27_clocks_init(unsigned long fref) | |
169 | { | |
c349adde AS |
170 | ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K); |
171 | ||
bb9c3398 | 172 | _mx27_clocks_init(fref); |
c20736f1 | 173 | |
e8e3faa0 AS |
174 | clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); |
175 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0"); | |
176 | clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); | |
177 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1"); | |
178 | clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); | |
179 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2"); | |
180 | clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); | |
181 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3"); | |
182 | clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4"); | |
183 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4"); | |
184 | clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5"); | |
185 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5"); | |
186 | clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); | |
187 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0"); | |
188 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0"); | |
189 | clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0"); | |
190 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1"); | |
191 | clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1"); | |
192 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2"); | |
193 | clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2"); | |
194 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0"); | |
195 | clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0"); | |
196 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1"); | |
197 | clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1"); | |
198 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2"); | |
199 | clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2"); | |
200 | clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0"); | |
201 | clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); | |
202 | clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0"); | |
203 | clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0"); | |
204 | clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0"); | |
205 | clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27"); | |
206 | clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27"); | |
207 | clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27"); | |
208 | clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0"); | |
209 | clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0"); | |
210 | clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0"); | |
211 | clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1"); | |
212 | clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1"); | |
213 | clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1"); | |
214 | clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2"); | |
215 | clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2"); | |
216 | clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2"); | |
217 | clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0"); | |
218 | clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1"); | |
219 | clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0"); | |
220 | clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0"); | |
221 | clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0"); | |
222 | clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma"); | |
223 | clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma"); | |
224 | clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0"); | |
225 | clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0"); | |
226 | clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0"); | |
227 | clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0"); | |
228 | clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1"); | |
229 | clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0"); | |
230 | clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad"); | |
231 | clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0"); | |
232 | clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0"); | |
233 | clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0"); | |
234 | clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0"); | |
e038ed50 | 235 | |
6c529c49 | 236 | mxc_timer_init(MX27_GPT1_BASE_ADDR, MX27_INT_GPT1); |
e038ed50 | 237 | |
e038ed50 SH |
238 | return 0; |
239 | } | |
240 | ||
c349adde | 241 | static void __init mx27_clocks_init_dt(struct device_node *np) |
e038ed50 | 242 | { |
c349adde | 243 | struct device_node *refnp; |
e038ed50 SH |
244 | u32 fref = 26000000; /* default */ |
245 | ||
c349adde AS |
246 | for_each_compatible_node(refnp, NULL, "fixed-clock") { |
247 | if (!of_device_is_compatible(refnp, "fsl,imx-osc26m")) | |
e038ed50 SH |
248 | continue; |
249 | ||
c349adde | 250 | if (!of_property_read_u32(refnp, "clock-frequency", &fref)) |
e038ed50 SH |
251 | break; |
252 | } | |
253 | ||
c349adde | 254 | ccm = of_iomap(np, 0); |
bb9c3398 | 255 | |
c349adde | 256 | _mx27_clocks_init(fref); |
bb9c3398 AS |
257 | |
258 | clk_data.clks = clk; | |
259 | clk_data.clk_num = ARRAY_SIZE(clk); | |
260 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
e038ed50 | 261 | } |
c349adde | 262 | CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt); |