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b8d4176f SH |
1 | /* |
2 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | #include <linux/mm.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/clkdev.h> | |
4d9d18a5 | 14 | #include <linux/clk-provider.h> |
b8d4176f SH |
15 | #include <linux/of.h> |
16 | #include <linux/err.h> | |
17 | ||
b8d4176f SH |
18 | #include "crm-regs-imx5.h" |
19 | #include "clk.h" | |
e3372474 | 20 | #include "common.h" |
50f2de61 | 21 | #include "hardware.h" |
b8d4176f SH |
22 | |
23 | /* Low-power Audio Playback Mode clock */ | |
24 | static const char *lp_apm_sel[] = { "osc", }; | |
25 | ||
26 | /* This is used multiple times */ | |
27 | static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", }; | |
28 | static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", }; | |
29 | static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", }; | |
30 | static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", }; | |
31 | static const char *per_root_sel[] = { "per_podf", "ipg", }; | |
32 | static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", }; | |
33 | static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", }; | |
13b3a07a SG |
34 | static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", }; |
35 | static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", }; | |
36 | static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", }; | |
37 | static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", }; | |
38 | static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", }; | |
b8d4176f SH |
39 | static const char *emi_slow_sel[] = { "main_bus", "ahb", }; |
40 | static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", }; | |
41 | static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", }; | |
51f66191 | 42 | static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", }; |
b8d4176f SH |
43 | static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", }; |
44 | static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", }; | |
51f66191 | 45 | static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", }; |
b8d4176f SH |
46 | static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", }; |
47 | static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", }; | |
48 | static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", }; | |
3f487bed | 49 | static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", }; |
b8d4176f | 50 | static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; |
8ecb167f PZ |
51 | static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" }; |
52 | static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" }; | |
b8d4176f | 53 | static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; |
a745f039 | 54 | static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", }; |
04b41e84 MF |
55 | static const char *mx53_cko1_sel[] = { |
56 | "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw", | |
57 | "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy", | |
58 | "di_pred", "dummy", "dummy", "ahb", | |
59 | "ipg", "per_root", "ckil", "dummy",}; | |
60 | static const char *mx53_cko2_sel[] = { | |
61 | "dummy"/* dptc_core */, "dummy"/* dptc_perich */, | |
62 | "dummy", "esdhc_a_podf", | |
63 | "usboh3_podf", "dummy"/* wrck_clk_root */, | |
64 | "ecspi_podf", "dummy"/* pll1_ref_clk */, | |
65 | "esdhc_b_podf", "dummy"/* ddr_clk_root */, | |
66 | "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */, | |
67 | "vpu_sel", "ipu_sel", | |
68 | "osc", "ckih1", | |
69 | "dummy", "esdhc_c_sel", | |
70 | "ssi1_root_podf", "ssi2_root_podf", | |
71 | "dummy", "dummy", | |
72 | "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */, | |
73 | "dummy"/* tve_out */, "usb_phy_sel", | |
74 | "tve_sel", "lp_apm", | |
75 | "uart_root", "dummy"/* spdif0_clk_root */, | |
76 | "dummy", "dummy", }; | |
beb2d1c1 PZ |
77 | static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", }; |
78 | static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", }; | |
79 | static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", }; | |
80 | static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", }; | |
81 | static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; | |
82 | ||
b8d4176f SH |
83 | |
84 | enum imx5_clks { | |
85 | dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred, | |
86 | uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s, | |
87 | emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred, | |
d24de495 | 88 | usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di_unused, |
b8d4176f SH |
89 | tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate, |
90 | uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate, | |
91 | gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate, | |
0f3557c3 | 92 | gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate, |
b8d4176f SH |
93 | esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate, |
94 | ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate, | |
95 | ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s, | |
96 | ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate, | |
97 | vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate, | |
98 | uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate, | |
99 | esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate, | |
100 | mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate, | |
101 | ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div, | |
102 | ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm, | |
103 | periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2, | |
104 | tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf, | |
105 | esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate, | |
106 | usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw, | |
107 | pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw, | |
108 | ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate, | |
109 | usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root, | |
13b3a07a SG |
110 | ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel, |
111 | ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred, | |
112 | ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred, | |
113 | ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate, | |
114 | ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, | |
d1e9e0ea | 115 | epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, |
a745f039 | 116 | can_sel, can1_serial_gate, can1_ipg_gate, |
8ecb167f | 117 | owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate, |
04b41e84 MF |
118 | cko1_sel, cko1_podf, cko1, |
119 | cko2_sel, cko2_podf, cko2, | |
beb2d1c1 PZ |
120 | srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel, |
121 | spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf, | |
122 | spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate, | |
ea257a03 | 123 | ocram, clk_max |
b8d4176f SH |
124 | }; |
125 | ||
126 | static struct clk *clk[clk_max]; | |
f40f38d1 | 127 | static struct clk_onecell_data clk_data; |
b8d4176f SH |
128 | |
129 | static void __init mx5_clocks_common_init(unsigned long rate_ckil, | |
130 | unsigned long rate_osc, unsigned long rate_ckih1, | |
131 | unsigned long rate_ckih2) | |
132 | { | |
133 | int i; | |
134 | ||
135 | clk[dummy] = imx_clk_fixed("dummy", 0); | |
75f83d06 MF |
136 | clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil); |
137 | clk[osc] = imx_obtain_fixed_clock("osc", rate_osc); | |
138 | clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1); | |
139 | clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2); | |
b8d4176f SH |
140 | |
141 | clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, | |
142 | lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); | |
143 | clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, | |
144 | periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); | |
145 | clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, | |
146 | main_bus_sel, ARRAY_SIZE(main_bus_sel)); | |
c040be00 | 147 | clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, |
b8d4176f SH |
148 | per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); |
149 | clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); | |
150 | clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); | |
151 | clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); | |
c040be00 | 152 | clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1, |
b8d4176f SH |
153 | per_root_sel, ARRAY_SIZE(per_root_sel)); |
154 | clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); | |
155 | clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); | |
156 | clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24); | |
157 | clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26); | |
158 | clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0); | |
159 | clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2); | |
160 | clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4); | |
161 | clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0); | |
162 | clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2); | |
163 | clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3); | |
164 | clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3); | |
165 | clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2, | |
166 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
167 | clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3); | |
168 | clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3); | |
169 | ||
170 | clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2, | |
171 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
172 | clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2, | |
173 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
174 | clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3); | |
175 | clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3); | |
176 | clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3); | |
177 | clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3); | |
178 | clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel)); | |
179 | clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel)); | |
180 | ||
181 | clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1, | |
182 | emi_slow_sel, ARRAY_SIZE(emi_slow_sel)); | |
183 | clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3); | |
184 | clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3); | |
185 | clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2, | |
186 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
187 | clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3); | |
188 | clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6); | |
189 | clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2, | |
190 | standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); | |
191 | clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3); | |
192 | clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2); | |
193 | clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3); | |
194 | clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3); | |
195 | clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1, | |
196 | usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str)); | |
197 | clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3); | |
198 | clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3); | |
b8d4176f SH |
199 | clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); |
200 | clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); | |
201 | clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8); | |
202 | clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10); | |
203 | clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12); | |
204 | clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14); | |
205 | clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); | |
206 | clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); | |
207 | clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); | |
b8d4176f | 208 | clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); |
796b72cc | 209 | clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12); |
b8d4176f | 210 | clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); |
796b72cc | 211 | clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16); |
0f3557c3 AS |
212 | clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); |
213 | clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20); | |
b8d4176f SH |
214 | clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); |
215 | clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); | |
216 | clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); | |
217 | clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0); | |
218 | clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4); | |
219 | clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8); | |
220 | clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12); | |
221 | clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16); | |
222 | clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20); | |
223 | clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24); | |
224 | clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18); | |
225 | clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20); | |
226 | clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22); | |
227 | clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24); | |
228 | clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26); | |
229 | clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30); | |
230 | clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14); | |
231 | clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16); | |
232 | clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel)); | |
233 | clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10); | |
234 | clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); | |
235 | clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); | |
236 | clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); | |
8ecb167f PZ |
237 | clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel)); |
238 | clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel)); | |
239 | clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2); | |
240 | clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4); | |
241 | clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14); | |
b8d4176f SH |
242 | clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel)); |
243 | clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6); | |
244 | clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8); | |
245 | clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8); | |
246 | clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10); | |
247 | clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12); | |
248 | clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14); | |
249 | clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24); | |
250 | ||
13b3a07a SG |
251 | clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels)); |
252 | clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); | |
253 | clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); | |
254 | clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels)); | |
255 | clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); | |
256 | clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); | |
257 | clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels)); | |
258 | clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels)); | |
259 | clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3); | |
260 | clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6); | |
261 | clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3); | |
262 | clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6); | |
263 | clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3); | |
264 | clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6); | |
265 | clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3); | |
266 | clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6); | |
267 | clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18); | |
268 | clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22); | |
269 | clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); | |
270 | clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); | |
271 | clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); | |
d1e9e0ea AS |
272 | clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); |
273 | clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4); | |
274 | clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); | |
275 | clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); | |
f1550a1c | 276 | clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); |
5d530bb0 SH |
277 | clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28); |
278 | clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); | |
beb2d1c1 PZ |
279 | clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel)); |
280 | clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3); | |
281 | clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6); | |
282 | clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1, | |
283 | spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT); | |
284 | clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); | |
285 | clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); | |
13b3a07a | 286 | |
b8d4176f SH |
287 | for (i = 0; i < ARRAY_SIZE(clk); i++) |
288 | if (IS_ERR(clk[i])) | |
289 | pr_err("i.MX5 clk %d: register failed with %ld\n", | |
290 | i, PTR_ERR(clk[i])); | |
f1550a1c | 291 | |
0f3557c3 | 292 | clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0"); |
b8d4176f SH |
293 | clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0"); |
294 | clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0"); | |
295 | clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); | |
296 | clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1"); | |
297 | clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1"); | |
298 | clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2"); | |
299 | clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2"); | |
300 | clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3"); | |
301 | clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3"); | |
302 | clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4"); | |
303 | clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4"); | |
304 | clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0"); | |
305 | clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0"); | |
306 | clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1"); | |
307 | clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1"); | |
e0c29dce | 308 | clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2"); |
b8d4176f SH |
309 | clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0"); |
310 | clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1"); | |
5bdfba29 SG |
311 | clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); |
312 | clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); | |
b8d4176f SH |
313 | clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0"); |
314 | clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0"); | |
315 | clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0"); | |
316 | clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1"); | |
317 | clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1"); | |
318 | clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1"); | |
319 | clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2"); | |
320 | clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2"); | |
321 | clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2"); | |
61c4b560 PC |
322 | clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51"); |
323 | clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51"); | |
324 | clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51"); | |
4d62435f | 325 | clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand"); |
b8d4176f SH |
326 | clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); |
327 | clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); | |
328 | clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2"); | |
329 | clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); | |
3d10a887 | 330 | clk_register_clkdev(clk[cpu_podf], NULL, "cpu0"); |
b8d4176f SH |
331 | clk_register_clkdev(clk[iim_gate], "iim", NULL); |
332 | clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0"); | |
333 | clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1"); | |
334 | clk_register_clkdev(clk[dummy], NULL, "imx-keypad"); | |
b8d4176f | 335 | clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0"); |
aa96a18d | 336 | clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL); |
d1e9e0ea AS |
337 | clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0"); |
338 | clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0"); | |
339 | clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1"); | |
340 | clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1"); | |
b8d4176f SH |
341 | |
342 | /* Set SDHC parents to be PLL2 */ | |
343 | clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]); | |
344 | clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]); | |
345 | ||
346 | /* move usb phy clk to 24MHz */ | |
347 | clk_set_parent(clk[usb_phy_sel], clk[osc]); | |
348 | ||
349 | clk_prepare_enable(clk[gpc_dvfs]); | |
350 | clk_prepare_enable(clk[ahb_max]); /* esdhc3 */ | |
351 | clk_prepare_enable(clk[aips_tz1]); | |
352 | clk_prepare_enable(clk[aips_tz2]); /* fec */ | |
353 | clk_prepare_enable(clk[spba]); | |
354 | clk_prepare_enable(clk[emi_fast_gate]); /* fec */ | |
68b0562d | 355 | clk_prepare_enable(clk[emi_slow_gate]); /* eim */ |
9a2d4825 SH |
356 | clk_prepare_enable(clk[mipi_hsc1_gate]); |
357 | clk_prepare_enable(clk[mipi_hsc2_gate]); | |
358 | clk_prepare_enable(clk[mipi_esc_gate]); | |
359 | clk_prepare_enable(clk[mipi_hsp_gate]); | |
b8d4176f SH |
360 | clk_prepare_enable(clk[tmax1]); |
361 | clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */ | |
362 | clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */ | |
363 | } | |
364 | ||
365 | int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, | |
366 | unsigned long rate_ckih1, unsigned long rate_ckih2) | |
367 | { | |
368 | int i; | |
69155fd6 | 369 | u32 val; |
f40f38d1 | 370 | struct device_node *np; |
b8d4176f SH |
371 | |
372 | clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); | |
373 | clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE); | |
374 | clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE); | |
375 | clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, | |
376 | mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel)); | |
377 | clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, | |
378 | mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel)); | |
80f72d2d PZ |
379 | clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, |
380 | mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT); | |
3f487bed PZ |
381 | clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, |
382 | mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel)); | |
b8d4176f SH |
383 | clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30); |
384 | clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3); | |
385 | clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); | |
386 | clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6); | |
387 | clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10); | |
388 | clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); | |
389 | clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0); | |
390 | clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22); | |
391 | clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6); | |
392 | clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); | |
393 | clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); | |
394 | clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); | |
beb2d1c1 PZ |
395 | clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, |
396 | mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel)); | |
397 | clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2, | |
398 | spdif_sel, ARRAY_SIZE(spdif_sel)); | |
5d5248a6 | 399 | clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); |
beb2d1c1 PZ |
400 | clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6); |
401 | clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1, | |
402 | mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); | |
403 | clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); | |
b8d4176f SH |
404 | |
405 | for (i = 0; i < ARRAY_SIZE(clk); i++) | |
406 | if (IS_ERR(clk[i])) | |
407 | pr_err("i.MX51 clk %d: register failed with %ld\n", | |
408 | i, PTR_ERR(clk[i])); | |
409 | ||
f40f38d1 FE |
410 | np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm"); |
411 | clk_data.clks = clk; | |
412 | clk_data.clk_num = ARRAY_SIZE(clk); | |
413 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
414 | ||
b8d4176f SH |
415 | mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); |
416 | ||
5bdfba29 | 417 | clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2"); |
b8d4176f SH |
418 | clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL); |
419 | clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0"); | |
420 | clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); | |
b8d4176f SH |
421 | clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0"); |
422 | clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0"); | |
423 | clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0"); | |
424 | clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0"); | |
425 | clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1"); | |
426 | clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1"); | |
427 | clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1"); | |
428 | clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2"); | |
429 | clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2"); | |
430 | clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2"); | |
431 | clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3"); | |
432 | clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3"); | |
433 | clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3"); | |
434 | ||
435 | /* set the usboh3 parent to pll2_sw */ | |
436 | clk_set_parent(clk[usboh3_sel], clk[pll2_sw]); | |
437 | ||
438 | /* set SDHC root clock to 166.25MHZ*/ | |
439 | clk_set_rate(clk[esdhc_a_podf], 166250000); | |
440 | clk_set_rate(clk[esdhc_b_podf], 166250000); | |
441 | ||
442 | /* System timer */ | |
2cfb4518 | 443 | mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT); |
b8d4176f SH |
444 | |
445 | clk_prepare_enable(clk[iim_gate]); | |
446 | imx_print_silicon_rev("i.MX51", mx51_revision()); | |
447 | clk_disable_unprepare(clk[iim_gate]); | |
69155fd6 SH |
448 | |
449 | /* | |
450 | * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no | |
451 | * longer supported. Set to one for better power saving. | |
452 | * | |
453 | * The effect of not setting these bits is that MIPI clocks can't be | |
454 | * enabled without the IPU clock being enabled aswell. | |
455 | */ | |
456 | val = readl(MXC_CCM_CCDR); | |
457 | val |= 1 << 18; | |
458 | writel(val, MXC_CCM_CCDR); | |
459 | ||
460 | val = readl(MXC_CCM_CLPCR); | |
461 | val |= 1 << 23; | |
462 | writel(val, MXC_CCM_CLPCR); | |
b8d4176f SH |
463 | |
464 | return 0; | |
465 | } | |
466 | ||
4d9d18a5 SH |
467 | static void __init mx51_clocks_init_dt(struct device_node *np) |
468 | { | |
469 | mx51_clocks_init(0, 0, 0, 0); | |
470 | } | |
471 | CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt); | |
472 | ||
473 | static void __init mx53_clocks_init(struct device_node *np) | |
b8d4176f SH |
474 | { |
475 | int i; | |
476 | unsigned long r; | |
477 | ||
478 | clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); | |
479 | clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); | |
480 | clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); | |
481 | clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE); | |
482 | ||
b8d4176f | 483 | clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); |
cc7b6339 PZ |
484 | clk[ldb_di1_div] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0); |
485 | clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1, | |
486 | mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT); | |
b8d4176f | 487 | clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3); |
b8d4176f | 488 | clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); |
cc7b6339 PZ |
489 | clk[ldb_di0_div] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0); |
490 | clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1, | |
491 | mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT); | |
b8d4176f SH |
492 | clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); |
493 | clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); | |
494 | clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, | |
495 | mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel)); | |
496 | clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, | |
497 | mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel)); | |
f550e701 PZ |
498 | clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, |
499 | mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT); | |
b8d4176f SH |
500 | clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); |
501 | clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3); | |
502 | clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); | |
503 | clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); | |
504 | clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); | |
505 | clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); | |
506 | clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); | |
507 | clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); | |
a745f039 SH |
508 | clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2, |
509 | mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); | |
510 | clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); | |
511 | clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); | |
ea257a03 | 512 | clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2); |
a745f039 SH |
513 | clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); |
514 | clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); | |
b8d4176f | 515 | clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); |
c9a74f55 | 516 | clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2); |
b8d4176f | 517 | |
04b41e84 MF |
518 | clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, |
519 | mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); | |
520 | clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); | |
521 | clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); | |
522 | ||
523 | clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, | |
524 | mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); | |
525 | clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); | |
526 | clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); | |
beb2d1c1 PZ |
527 | clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, |
528 | mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); | |
04b41e84 | 529 | |
b8d4176f SH |
530 | for (i = 0; i < ARRAY_SIZE(clk); i++) |
531 | if (IS_ERR(clk[i])) | |
532 | pr_err("i.MX53 clk %d: register failed with %ld\n", | |
533 | i, PTR_ERR(clk[i])); | |
534 | ||
f40f38d1 FE |
535 | clk_data.clks = clk; |
536 | clk_data.clk_num = ARRAY_SIZE(clk); | |
537 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
538 | ||
4d9d18a5 | 539 | mx5_clocks_common_init(0, 0, 0, 0); |
b8d4176f SH |
540 | |
541 | clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0"); | |
5bdfba29 | 542 | clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); |
b8d4176f | 543 | clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0"); |
b8d4176f SH |
544 | clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0"); |
545 | clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0"); | |
546 | clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0"); | |
547 | clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0"); | |
548 | clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1"); | |
549 | clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1"); | |
550 | clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1"); | |
551 | clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2"); | |
552 | clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2"); | |
553 | clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2"); | |
554 | clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3"); | |
555 | clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3"); | |
556 | clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3"); | |
557 | ||
558 | /* set SDHC root clock to 200MHZ*/ | |
559 | clk_set_rate(clk[esdhc_a_podf], 200000000); | |
560 | clk_set_rate(clk[esdhc_b_podf], 200000000); | |
561 | ||
562 | /* System timer */ | |
2cfb4518 | 563 | mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT); |
b8d4176f SH |
564 | |
565 | clk_prepare_enable(clk[iim_gate]); | |
566 | imx_print_silicon_rev("i.MX53", mx53_revision()); | |
567 | clk_disable_unprepare(clk[iim_gate]); | |
568 | ||
569 | r = clk_round_rate(clk[usboh3_per_gate], 54000000); | |
570 | clk_set_rate(clk[usboh3_per_gate], r); | |
b8d4176f | 571 | } |
4d9d18a5 | 572 | CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); |