Commit | Line | Data |
---|---|---|
52c543f9 | 1 | /* |
df595746 | 2 | * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. |
52c543f9 QJ |
3 | */ |
4 | ||
5 | /* | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_ARCH_MXC_COMMON_H__ | |
12 | #define __ASM_ARCH_MXC_COMMON_H__ | |
13 | ||
7b6d864b RH |
14 | #include <linux/reboot.h> |
15 | ||
d48866fe | 16 | struct irq_data; |
282b13d0 | 17 | struct platform_device; |
009e63f8 | 18 | struct pt_regs; |
30c730f8 | 19 | struct clk; |
876292d6 | 20 | struct device_node; |
a1f1c7ef | 21 | enum mxc_cpu_pwr_mode; |
e57e4ab5 | 22 | struct of_device_id; |
282b13d0 | 23 | |
803648db SG |
24 | void mx1_map_io(void); |
25 | void mx21_map_io(void); | |
26 | void mx25_map_io(void); | |
27 | void mx27_map_io(void); | |
28 | void mx31_map_io(void); | |
29 | void mx35_map_io(void); | |
803648db SG |
30 | void imx1_init_early(void); |
31 | void imx21_init_early(void); | |
32 | void imx25_init_early(void); | |
33 | void imx27_init_early(void); | |
34 | void imx31_init_early(void); | |
35 | void imx35_init_early(void); | |
803648db | 36 | void mxc_init_irq(void __iomem *); |
fffa0512 | 37 | void tzic_init_irq(void); |
803648db SG |
38 | void mx1_init_irq(void); |
39 | void mx21_init_irq(void); | |
40 | void mx25_init_irq(void); | |
41 | void mx27_init_irq(void); | |
42 | void mx31_init_irq(void); | |
43 | void mx35_init_irq(void); | |
803648db SG |
44 | void imx1_soc_init(void); |
45 | void imx21_soc_init(void); | |
46 | void imx25_soc_init(void); | |
47 | void imx27_soc_init(void); | |
48 | void imx31_soc_init(void); | |
49 | void imx35_soc_init(void); | |
803648db SG |
50 | void epit_timer_init(void __iomem *base, int irq); |
51 | void mxc_timer_init(void __iomem *, int); | |
52 | int mx1_clocks_init(unsigned long fref); | |
53 | int mx21_clocks_init(unsigned long lref, unsigned long fref); | |
54 | int mx25_clocks_init(void); | |
55 | int mx27_clocks_init(unsigned long fref); | |
56 | int mx31_clocks_init(unsigned long fref); | |
57 | int mx35_clocks_init(void); | |
803648db SG |
58 | int mx31_clocks_init_dt(void); |
59 | struct platform_device *mxc_register_gpio(char *name, int id, | |
b78d8e59 | 60 | resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); |
803648db SG |
61 | void mxc_set_cpu_type(unsigned int type); |
62 | void mxc_restart(enum reboot_mode, const char *); | |
63 | void mxc_arch_reset_init(void __iomem *); | |
64 | void mxc_arch_reset_init_dt(void); | |
364b28a5 | 65 | int mx51_revision(void); |
803648db SG |
66 | int mx53_revision(void); |
67 | void imx_set_aips(void __iomem *); | |
e57e4ab5 | 68 | void imx_aips_allow_unprivileged_access(const char *compat); |
803648db | 69 | int mxc_device_init(void); |
bfefdff8 SG |
70 | void imx_set_soc_revision(unsigned int rev); |
71 | unsigned int imx_get_soc_revision(void); | |
f1c6f314 | 72 | void imx_init_revision_from_anatop(void); |
a2887546 | 73 | struct device *imx_soc_device_init(void); |
73d2b4cd | 74 | |
41e7daf2 SG |
75 | enum mxc_cpu_pwr_mode { |
76 | WAIT_CLOCKED, /* wfi only */ | |
77 | WAIT_UNCLOCKED, /* WAIT */ | |
78 | WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ | |
79 | STOP_POWER_ON, /* just STOP */ | |
80 | STOP_POWER_OFF, /* STOP + SRPG */ | |
81 | }; | |
82 | ||
3ac804e3 FE |
83 | enum mx3_cpu_pwr_mode { |
84 | MX3_RUN, | |
85 | MX3_WAIT, | |
86 | MX3_DOZE, | |
87 | MX3_SLEEP, | |
88 | }; | |
89 | ||
803648db SG |
90 | void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); |
91 | void imx_print_silicon_rev(const char *cpu, int srev); | |
b6de943b | 92 | |
803648db SG |
93 | void imx_enable_cpu(int cpu, bool enable); |
94 | void imx_set_cpu_jump(int cpu, void *jump_addr); | |
95 | u32 imx_get_cpu_arg(int cpu); | |
96 | void imx_set_cpu_arg(int cpu, u32 arg); | |
69c31b7a | 97 | #ifdef CONFIG_SMP |
803648db SG |
98 | void v7_secondary_startup(void); |
99 | void imx_scu_map_io(void); | |
100 | void imx_smp_prepare(void); | |
101 | void imx_scu_standby_enable(void); | |
13eed989 SG |
102 | #else |
103 | static inline void imx_scu_map_io(void) {} | |
a1f1c7ef | 104 | static inline void imx_smp_prepare(void) {} |
e5f9dec8 | 105 | static inline void imx_scu_standby_enable(void) {} |
69c31b7a | 106 | #endif |
803648db | 107 | void imx_src_init(void); |
803648db | 108 | void imx_gpc_init(void); |
80c0ecdc | 109 | void imx_gpc_pre_suspend(bool arm_power_off); |
803648db SG |
110 | void imx_gpc_post_resume(void); |
111 | void imx_gpc_mask_all(void); | |
112 | void imx_gpc_restore_all(void); | |
d48866fe SG |
113 | void imx_gpc_irq_mask(struct irq_data *d); |
114 | void imx_gpc_irq_unmask(struct irq_data *d); | |
803648db SG |
115 | void imx_anatop_init(void); |
116 | void imx_anatop_pre_suspend(void); | |
117 | void imx_anatop_post_resume(void); | |
118 | int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); | |
dfea953a | 119 | void imx6q_set_int_mem_clk_lpm(bool enable); |
751f7e99 | 120 | void imx6sl_set_wait_clk(bool enter); |
803648db SG |
121 | |
122 | void imx_cpu_die(unsigned int cpu); | |
123 | int imx_cpu_kill(unsigned int cpu); | |
e4f2d979 | 124 | |
c356bdb4 SG |
125 | #ifdef CONFIG_SUSPEND |
126 | void v7_cpu_resume(void); | |
df595746 | 127 | void imx6_suspend(void __iomem *ocram_vbase); |
c356bdb4 SG |
128 | #else |
129 | static inline void v7_cpu_resume(void) {} | |
130 | static inline void imx6_suspend(void __iomem *ocram_vbase) {} | |
131 | #endif | |
132 | ||
803648db | 133 | void imx6q_pm_init(void); |
df595746 AH |
134 | void imx6dl_pm_init(void); |
135 | void imx6sl_pm_init(void); | |
ff843d62 | 136 | void imx6sx_pm_init(void); |
9e8147bb | 137 | void imx6q_pm_set_ccm_base(void __iomem *base); |
df595746 | 138 | |
28a9f3b0 | 139 | #ifdef CONFIG_PM |
36b66c3f SG |
140 | void imx51_pm_init(void); |
141 | void imx53_pm_init(void); | |
4ef5e387 | 142 | void imx5_pm_set_ccm_base(void __iomem *base); |
46ec1b26 | 143 | #else |
36b66c3f SG |
144 | static inline void imx51_pm_init(void) {} |
145 | static inline void imx53_pm_init(void) {} | |
4ef5e387 | 146 | static inline void imx5_pm_set_ccm_base(void __iomem *base) {} |
46ec1b26 EM |
147 | #endif |
148 | ||
8321b758 | 149 | #ifdef CONFIG_NEON |
803648db | 150 | int mx51_neon_fixup(void); |
8321b758 SG |
151 | #else |
152 | static inline int mx51_neon_fixup(void) { return 0; } | |
153 | #endif | |
154 | ||
e6a07569 | 155 | #ifdef CONFIG_CACHE_L2X0 |
803648db | 156 | void imx_init_l2cache(void); |
e6a07569 SG |
157 | #else |
158 | static inline void imx_init_l2cache(void) {} | |
159 | #endif | |
160 | ||
e4f2d979 MZ |
161 | extern struct smp_operations imx_smp_ops; |
162 | ||
52c543f9 | 163 | #endif |