ARM: imx6: Warn when an old DT is detected
[deliverable/linux.git] / arch / arm / mach-imx / common.h
CommitLineData
52c543f9 1/*
df595746 2 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
52c543f9
QJ
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__
13
7b6d864b
RH
14#include <linux/reboot.h>
15
d48866fe 16struct irq_data;
282b13d0 17struct platform_device;
009e63f8 18struct pt_regs;
30c730f8 19struct clk;
876292d6 20struct device_node;
a1f1c7ef 21enum mxc_cpu_pwr_mode;
e57e4ab5 22struct of_device_id;
282b13d0 23
803648db
SG
24void mx1_map_io(void);
25void mx21_map_io(void);
803648db
SG
26void mx27_map_io(void);
27void mx31_map_io(void);
28void mx35_map_io(void);
803648db
SG
29void imx1_init_early(void);
30void imx21_init_early(void);
803648db
SG
31void imx27_init_early(void);
32void imx31_init_early(void);
33void imx35_init_early(void);
803648db 34void mxc_init_irq(void __iomem *);
fffa0512 35void tzic_init_irq(void);
803648db
SG
36void mx1_init_irq(void);
37void mx21_init_irq(void);
803648db
SG
38void mx27_init_irq(void);
39void mx31_init_irq(void);
40void mx35_init_irq(void);
803648db
SG
41void imx1_soc_init(void);
42void imx21_soc_init(void);
803648db
SG
43void imx27_soc_init(void);
44void imx31_soc_init(void);
45void imx35_soc_init(void);
803648db
SG
46void epit_timer_init(void __iomem *base, int irq);
47void mxc_timer_init(void __iomem *, int);
48int mx1_clocks_init(unsigned long fref);
49int mx21_clocks_init(unsigned long lref, unsigned long fref);
803648db
SG
50int mx27_clocks_init(unsigned long fref);
51int mx31_clocks_init(unsigned long fref);
52int mx35_clocks_init(void);
803648db
SG
53int mx31_clocks_init_dt(void);
54struct platform_device *mxc_register_gpio(char *name, int id,
b78d8e59 55 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
803648db
SG
56void mxc_set_cpu_type(unsigned int type);
57void mxc_restart(enum reboot_mode, const char *);
58void mxc_arch_reset_init(void __iomem *);
364b28a5 59int mx51_revision(void);
803648db
SG
60int mx53_revision(void);
61void imx_set_aips(void __iomem *);
e57e4ab5 62void imx_aips_allow_unprivileged_access(const char *compat);
803648db 63int mxc_device_init(void);
bfefdff8
SG
64void imx_set_soc_revision(unsigned int rev);
65unsigned int imx_get_soc_revision(void);
f1c6f314 66void imx_init_revision_from_anatop(void);
a2887546 67struct device *imx_soc_device_init(void);
05136f08 68void imx6_enable_rbc(bool enable);
14517564 69void imx_gpc_check_dt(void);
05136f08
AH
70void imx_gpc_set_arm_power_in_lpm(bool power_off);
71void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
72void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
73d2b4cd 73
41e7daf2
SG
74enum mxc_cpu_pwr_mode {
75 WAIT_CLOCKED, /* wfi only */
76 WAIT_UNCLOCKED, /* WAIT */
77 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
78 STOP_POWER_ON, /* just STOP */
79 STOP_POWER_OFF, /* STOP + SRPG */
80};
81
3ac804e3
FE
82enum mx3_cpu_pwr_mode {
83 MX3_RUN,
84 MX3_WAIT,
85 MX3_DOZE,
86 MX3_SLEEP,
87};
88
803648db
SG
89void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
90void imx_print_silicon_rev(const char *cpu, int srev);
b6de943b 91
803648db
SG
92void imx_enable_cpu(int cpu, bool enable);
93void imx_set_cpu_jump(int cpu, void *jump_addr);
94u32 imx_get_cpu_arg(int cpu);
95void imx_set_cpu_arg(int cpu, u32 arg);
69c31b7a 96#ifdef CONFIG_SMP
803648db
SG
97void v7_secondary_startup(void);
98void imx_scu_map_io(void);
99void imx_smp_prepare(void);
13eed989
SG
100#else
101static inline void imx_scu_map_io(void) {}
a1f1c7ef 102static inline void imx_smp_prepare(void) {}
69c31b7a 103#endif
803648db 104void imx_src_init(void);
80c0ecdc 105void imx_gpc_pre_suspend(bool arm_power_off);
803648db
SG
106void imx_gpc_post_resume(void);
107void imx_gpc_mask_all(void);
108void imx_gpc_restore_all(void);
65bb688a
MZ
109void imx_gpc_hwirq_mask(unsigned int hwirq);
110void imx_gpc_hwirq_unmask(unsigned int hwirq);
803648db
SG
111void imx_anatop_init(void);
112void imx_anatop_pre_suspend(void);
113void imx_anatop_post_resume(void);
114int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
dfea953a 115void imx6q_set_int_mem_clk_lpm(bool enable);
751f7e99 116void imx6sl_set_wait_clk(bool enter);
ec336b28 117int imx_mmdc_get_ddr_type(void);
803648db
SG
118
119void imx_cpu_die(unsigned int cpu);
120int imx_cpu_kill(unsigned int cpu);
e4f2d979 121
c356bdb4
SG
122#ifdef CONFIG_SUSPEND
123void v7_cpu_resume(void);
df595746 124void imx6_suspend(void __iomem *ocram_vbase);
c356bdb4
SG
125#else
126static inline void v7_cpu_resume(void) {}
127static inline void imx6_suspend(void __iomem *ocram_vbase) {}
128#endif
129
803648db 130void imx6q_pm_init(void);
df595746
AH
131void imx6dl_pm_init(void);
132void imx6sl_pm_init(void);
ff843d62 133void imx6sx_pm_init(void);
9e8147bb 134void imx6q_pm_set_ccm_base(void __iomem *base);
df595746 135
28a9f3b0 136#ifdef CONFIG_PM
36b66c3f
SG
137void imx51_pm_init(void);
138void imx53_pm_init(void);
4ef5e387 139void imx5_pm_set_ccm_base(void __iomem *base);
46ec1b26 140#else
36b66c3f
SG
141static inline void imx51_pm_init(void) {}
142static inline void imx53_pm_init(void) {}
4ef5e387 143static inline void imx5_pm_set_ccm_base(void __iomem *base) {}
46ec1b26
EM
144#endif
145
8321b758 146#ifdef CONFIG_NEON
803648db 147int mx51_neon_fixup(void);
8321b758
SG
148#else
149static inline int mx51_neon_fixup(void) { return 0; }
150#endif
151
e6a07569 152#ifdef CONFIG_CACHE_L2X0
803648db 153void imx_init_l2cache(void);
e6a07569
SG
154#else
155static inline void imx_init_l2cache(void) {}
156#endif
157
e4f2d979 158extern struct smp_operations imx_smp_ops;
4e3fea4a 159extern struct smp_operations ls1021a_smp_ops;
e4f2d979 160
52c543f9 161#endif
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