ARM: imx: drop extern with function prototypes in common.h
[deliverable/linux.git] / arch / arm / mach-imx / common.h
CommitLineData
52c543f9 1/*
e95dddb3 2 * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
52c543f9
QJ
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__
13
7b6d864b
RH
14#include <linux/reboot.h>
15
282b13d0 16struct platform_device;
009e63f8 17struct pt_regs;
30c730f8 18struct clk;
a1f1c7ef 19enum mxc_cpu_pwr_mode;
282b13d0 20
803648db
SG
21void mx1_map_io(void);
22void mx21_map_io(void);
23void mx25_map_io(void);
24void mx27_map_io(void);
25void mx31_map_io(void);
26void mx35_map_io(void);
27void mx51_map_io(void);
28void mx53_map_io(void);
29void imx1_init_early(void);
30void imx21_init_early(void);
31void imx25_init_early(void);
32void imx27_init_early(void);
33void imx31_init_early(void);
34void imx35_init_early(void);
35void imx51_init_early(void);
36void imx53_init_early(void);
37void mxc_init_irq(void __iomem *);
38void tzic_init_irq(void __iomem *);
39void mx1_init_irq(void);
40void mx21_init_irq(void);
41void mx25_init_irq(void);
42void mx27_init_irq(void);
43void mx31_init_irq(void);
44void mx35_init_irq(void);
45void mx51_init_irq(void);
46void mx53_init_irq(void);
47void imx1_soc_init(void);
48void imx21_soc_init(void);
49void imx25_soc_init(void);
50void imx27_soc_init(void);
51void imx31_soc_init(void);
52void imx35_soc_init(void);
53void imx51_soc_init(void);
54void imx51_init_late(void);
55void imx53_init_late(void);
56void epit_timer_init(void __iomem *base, int irq);
57void mxc_timer_init(void __iomem *, int);
58int mx1_clocks_init(unsigned long fref);
59int mx21_clocks_init(unsigned long lref, unsigned long fref);
60int mx25_clocks_init(void);
61int mx27_clocks_init(unsigned long fref);
62int mx31_clocks_init(unsigned long fref);
63int mx35_clocks_init(void);
64int mx51_clocks_init(unsigned long ckil, unsigned long osc,
a329b48c 65 unsigned long ckih1, unsigned long ckih2);
803648db
SG
66int mx25_clocks_init_dt(void);
67int mx27_clocks_init_dt(void);
68int mx31_clocks_init_dt(void);
69struct platform_device *mxc_register_gpio(char *name, int id,
b78d8e59 70 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
803648db
SG
71void mxc_set_cpu_type(unsigned int type);
72void mxc_restart(enum reboot_mode, const char *);
73void mxc_arch_reset_init(void __iomem *);
74void mxc_arch_reset_init_dt(void);
75int mx53_revision(void);
76void imx_set_aips(void __iomem *);
77int mxc_device_init(void);
bfefdff8
SG
78void imx_set_soc_revision(unsigned int rev);
79unsigned int imx_get_soc_revision(void);
f1c6f314 80void imx_init_revision_from_anatop(void);
a2887546 81struct device *imx_soc_device_init(void);
73d2b4cd 82
41e7daf2
SG
83enum mxc_cpu_pwr_mode {
84 WAIT_CLOCKED, /* wfi only */
85 WAIT_UNCLOCKED, /* WAIT */
86 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
87 STOP_POWER_ON, /* just STOP */
88 STOP_POWER_OFF, /* STOP + SRPG */
89};
90
3ac804e3
FE
91enum mx3_cpu_pwr_mode {
92 MX3_RUN,
93 MX3_WAIT,
94 MX3_DOZE,
95 MX3_SLEEP,
96};
97
803648db
SG
98void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
99void imx_print_silicon_rev(const char *cpu, int srev);
b6de943b
SH
100
101void avic_handle_irq(struct pt_regs *);
58a92600 102void tzic_handle_irq(struct pt_regs *);
b6de943b
SH
103
104#define imx1_handle_irq avic_handle_irq
105#define imx21_handle_irq avic_handle_irq
106#define imx25_handle_irq avic_handle_irq
107#define imx27_handle_irq avic_handle_irq
108#define imx31_handle_irq avic_handle_irq
109#define imx35_handle_irq avic_handle_irq
58a92600
SH
110#define imx51_handle_irq tzic_handle_irq
111#define imx53_handle_irq tzic_handle_irq
b6de943b 112
803648db
SG
113void imx_enable_cpu(int cpu, bool enable);
114void imx_set_cpu_jump(int cpu, void *jump_addr);
115u32 imx_get_cpu_arg(int cpu);
116void imx_set_cpu_arg(int cpu, u32 arg);
117void v7_cpu_resume(void);
69c31b7a 118#ifdef CONFIG_SMP
803648db
SG
119void v7_secondary_startup(void);
120void imx_scu_map_io(void);
121void imx_smp_prepare(void);
122void imx_scu_standby_enable(void);
13eed989
SG
123#else
124static inline void imx_scu_map_io(void) {}
a1f1c7ef 125static inline void imx_smp_prepare(void) {}
e5f9dec8 126static inline void imx_scu_standby_enable(void) {}
69c31b7a 127#endif
803648db 128void imx_src_init(void);
87a84b69 129#ifdef CONFIG_HAVE_IMX_SRC
803648db 130void imx_src_prepare_restart(void);
87a84b69
SG
131#else
132static inline void imx_src_prepare_restart(void) {}
133#endif
803648db
SG
134void imx_gpc_init(void);
135void imx_gpc_pre_suspend(void);
136void imx_gpc_post_resume(void);
137void imx_gpc_mask_all(void);
138void imx_gpc_restore_all(void);
139void imx_anatop_init(void);
140void imx_anatop_pre_suspend(void);
141void imx_anatop_post_resume(void);
142int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
143void imx6q_set_chicken_bit(void);
144
145void imx_cpu_die(unsigned int cpu);
146int imx_cpu_kill(unsigned int cpu);
e4f2d979 147
46ec1b26 148#ifdef CONFIG_PM
803648db
SG
149void imx6q_pm_init(void);
150void imx5_pm_init(void);
46ec1b26
EM
151#else
152static inline void imx6q_pm_init(void) {}
547dd1e0 153static inline void imx5_pm_init(void) {}
46ec1b26
EM
154#endif
155
8321b758 156#ifdef CONFIG_NEON
803648db 157int mx51_neon_fixup(void);
8321b758
SG
158#else
159static inline int mx51_neon_fixup(void) { return 0; }
160#endif
161
e6a07569 162#ifdef CONFIG_CACHE_L2X0
803648db 163void imx_init_l2cache(void);
e6a07569
SG
164#else
165static inline void imx_init_l2cache(void) {}
166#endif
167
e4f2d979
MZ
168extern struct smp_operations imx_smp_ops;
169
52c543f9 170#endif
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