ARM: i.MX27 clk: Add 26 MHz oscillator circuit clock gate
[deliverable/linux.git] / arch / arm / mach-imx / common.h
CommitLineData
52c543f9 1/*
df595746 2 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
52c543f9
QJ
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__
13
7b6d864b
RH
14#include <linux/reboot.h>
15
d48866fe 16struct irq_data;
282b13d0 17struct platform_device;
009e63f8 18struct pt_regs;
30c730f8 19struct clk;
876292d6 20struct device_node;
a1f1c7ef 21enum mxc_cpu_pwr_mode;
282b13d0 22
803648db
SG
23void mx1_map_io(void);
24void mx21_map_io(void);
25void mx25_map_io(void);
26void mx27_map_io(void);
27void mx31_map_io(void);
28void mx35_map_io(void);
803648db
SG
29void imx1_init_early(void);
30void imx21_init_early(void);
31void imx25_init_early(void);
32void imx27_init_early(void);
33void imx31_init_early(void);
34void imx35_init_early(void);
803648db 35void mxc_init_irq(void __iomem *);
fffa0512 36void tzic_init_irq(void);
803648db
SG
37void mx1_init_irq(void);
38void mx21_init_irq(void);
39void mx25_init_irq(void);
40void mx27_init_irq(void);
41void mx31_init_irq(void);
42void mx35_init_irq(void);
803648db
SG
43void imx1_soc_init(void);
44void imx21_soc_init(void);
45void imx25_soc_init(void);
46void imx27_soc_init(void);
47void imx31_soc_init(void);
48void imx35_soc_init(void);
803648db
SG
49void epit_timer_init(void __iomem *base, int irq);
50void mxc_timer_init(void __iomem *, int);
876292d6 51void mxc_timer_init_dt(struct device_node *);
803648db
SG
52int mx1_clocks_init(unsigned long fref);
53int mx21_clocks_init(unsigned long lref, unsigned long fref);
54int mx25_clocks_init(void);
55int mx27_clocks_init(unsigned long fref);
56int mx31_clocks_init(unsigned long fref);
57int mx35_clocks_init(void);
803648db
SG
58int mx31_clocks_init_dt(void);
59struct platform_device *mxc_register_gpio(char *name, int id,
b78d8e59 60 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
803648db
SG
61void mxc_set_cpu_type(unsigned int type);
62void mxc_restart(enum reboot_mode, const char *);
63void mxc_arch_reset_init(void __iomem *);
64void mxc_arch_reset_init_dt(void);
364b28a5 65int mx51_revision(void);
803648db
SG
66int mx53_revision(void);
67void imx_set_aips(void __iomem *);
68int mxc_device_init(void);
bfefdff8
SG
69void imx_set_soc_revision(unsigned int rev);
70unsigned int imx_get_soc_revision(void);
f1c6f314 71void imx_init_revision_from_anatop(void);
a2887546 72struct device *imx_soc_device_init(void);
73d2b4cd 73
41e7daf2
SG
74enum mxc_cpu_pwr_mode {
75 WAIT_CLOCKED, /* wfi only */
76 WAIT_UNCLOCKED, /* WAIT */
77 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
78 STOP_POWER_ON, /* just STOP */
79 STOP_POWER_OFF, /* STOP + SRPG */
80};
81
3ac804e3
FE
82enum mx3_cpu_pwr_mode {
83 MX3_RUN,
84 MX3_WAIT,
85 MX3_DOZE,
86 MX3_SLEEP,
87};
88
803648db
SG
89void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
90void imx_print_silicon_rev(const char *cpu, int srev);
b6de943b 91
803648db
SG
92void imx_enable_cpu(int cpu, bool enable);
93void imx_set_cpu_jump(int cpu, void *jump_addr);
94u32 imx_get_cpu_arg(int cpu);
95void imx_set_cpu_arg(int cpu, u32 arg);
69c31b7a 96#ifdef CONFIG_SMP
803648db
SG
97void v7_secondary_startup(void);
98void imx_scu_map_io(void);
99void imx_smp_prepare(void);
100void imx_scu_standby_enable(void);
13eed989
SG
101#else
102static inline void imx_scu_map_io(void) {}
a1f1c7ef 103static inline void imx_smp_prepare(void) {}
e5f9dec8 104static inline void imx_scu_standby_enable(void) {}
69c31b7a 105#endif
803648db 106void imx_src_init(void);
803648db 107void imx_gpc_init(void);
80c0ecdc 108void imx_gpc_pre_suspend(bool arm_power_off);
803648db
SG
109void imx_gpc_post_resume(void);
110void imx_gpc_mask_all(void);
111void imx_gpc_restore_all(void);
d48866fe
SG
112void imx_gpc_irq_mask(struct irq_data *d);
113void imx_gpc_irq_unmask(struct irq_data *d);
803648db
SG
114void imx_anatop_init(void);
115void imx_anatop_pre_suspend(void);
116void imx_anatop_post_resume(void);
117int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
dfea953a 118void imx6q_set_int_mem_clk_lpm(bool enable);
751f7e99 119void imx6sl_set_wait_clk(bool enter);
803648db
SG
120
121void imx_cpu_die(unsigned int cpu);
122int imx_cpu_kill(unsigned int cpu);
e4f2d979 123
c356bdb4
SG
124#ifdef CONFIG_SUSPEND
125void v7_cpu_resume(void);
df595746 126void imx6_suspend(void __iomem *ocram_vbase);
c356bdb4
SG
127#else
128static inline void v7_cpu_resume(void) {}
129static inline void imx6_suspend(void __iomem *ocram_vbase) {}
130#endif
131
803648db 132void imx6q_pm_init(void);
df595746
AH
133void imx6dl_pm_init(void);
134void imx6sl_pm_init(void);
ff843d62 135void imx6sx_pm_init(void);
9e8147bb 136void imx6q_pm_set_ccm_base(void __iomem *base);
df595746 137
28a9f3b0 138#ifdef CONFIG_PM
36b66c3f
SG
139void imx51_pm_init(void);
140void imx53_pm_init(void);
4ef5e387 141void imx5_pm_set_ccm_base(void __iomem *base);
46ec1b26 142#else
36b66c3f
SG
143static inline void imx51_pm_init(void) {}
144static inline void imx53_pm_init(void) {}
4ef5e387 145static inline void imx5_pm_set_ccm_base(void __iomem *base) {}
46ec1b26
EM
146#endif
147
8321b758 148#ifdef CONFIG_NEON
803648db 149int mx51_neon_fixup(void);
8321b758
SG
150#else
151static inline int mx51_neon_fixup(void) { return 0; }
152#endif
153
e6a07569 154#ifdef CONFIG_CACHE_L2X0
803648db 155void imx_init_l2cache(void);
e6a07569
SG
156#else
157static inline void imx_init_l2cache(void) {}
158#endif
159
e4f2d979
MZ
160extern struct smp_operations imx_smp_ops;
161
52c543f9 162#endif
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