Commit | Line | Data |
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a329b48c | 1 | /* |
b66ff7a2 | 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
a329b48c AK |
3 | * |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | * | |
11 | * This file contains the CPU initialization code. | |
12 | */ | |
13 | ||
14 | #include <linux/types.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
5443856c | 17 | #include <linux/module.h> |
ca06679d | 18 | #include <linux/io.h> |
ee18a715 SG |
19 | #include <linux/of.h> |
20 | #include <linux/of_address.h> | |
a329b48c | 21 | |
50f2de61 | 22 | #include "hardware.h" |
22567796 | 23 | #include "common.h" |
50f2de61 | 24 | |
c52c9835 | 25 | static int mx5_cpu_rev = -1; |
5443856c | 26 | |
9ab4650f | 27 | #define IIM_SREV 0x24 |
5443856c | 28 | |
ee18a715 SG |
29 | static u32 imx5_read_srev_reg(const char *compat) |
30 | { | |
31 | void __iomem *iim_base; | |
32 | struct device_node *np; | |
33 | u32 srev; | |
34 | ||
35 | np = of_find_compatible_node(NULL, NULL, compat); | |
36 | iim_base = of_iomap(np, 0); | |
37 | WARN_ON(!iim_base); | |
38 | ||
39 | srev = readl(iim_base + IIM_SREV) & 0xff; | |
40 | ||
41 | iounmap(iim_base); | |
42 | ||
43 | return srev; | |
44 | } | |
45 | ||
9ab4650f | 46 | static int get_mx51_srev(void) |
5443856c | 47 | { |
ee18a715 | 48 | u32 rev = imx5_read_srev_reg("fsl,imx51-iim"); |
5443856c | 49 | |
c52c9835 JL |
50 | switch (rev) { |
51 | case 0x0: | |
9ab4650f | 52 | return IMX_CHIP_REVISION_2_0; |
c52c9835 | 53 | case 0x10: |
9ab4650f | 54 | return IMX_CHIP_REVISION_3_0; |
c52c9835 JL |
55 | default: |
56 | return IMX_CHIP_REVISION_UNKNOWN; | |
57 | } | |
5443856c SH |
58 | } |
59 | ||
60 | /* | |
61 | * Returns: | |
62 | * the silicon revision of the cpu | |
5443856c SH |
63 | */ |
64 | int mx51_revision(void) | |
65 | { | |
c52c9835 JL |
66 | if (mx5_cpu_rev == -1) |
67 | mx5_cpu_rev = get_mx51_srev(); | |
5443856c | 68 | |
c52c9835 | 69 | return mx5_cpu_rev; |
5443856c SH |
70 | } |
71 | EXPORT_SYMBOL(mx51_revision); | |
72 | ||
33d7c5c1 AK |
73 | #ifdef CONFIG_NEON |
74 | ||
75 | /* | |
76 | * All versions of the silicon before Rev. 3 have broken NEON implementations. | |
77 | * Dependent on link order - so the assumption is that vfp_init is called | |
78 | * before us. | |
79 | */ | |
8321b758 | 80 | int __init mx51_neon_fixup(void) |
33d7c5c1 | 81 | { |
ca06679d FE |
82 | if (mx51_revision() < IMX_CHIP_REVISION_3_0 && |
83 | (elf_hwcap & HWCAP_NEON)) { | |
33d7c5c1 AK |
84 | elf_hwcap &= ~HWCAP_NEON; |
85 | pr_info("Turning off NEON support, detected broken NEON implementation\n"); | |
86 | } | |
87 | return 0; | |
88 | } | |
89 | ||
33d7c5c1 AK |
90 | #endif |
91 | ||
9ab4650f DN |
92 | static int get_mx53_srev(void) |
93 | { | |
ee18a715 | 94 | u32 rev = imx5_read_srev_reg("fsl,imx53-iim"); |
9ab4650f | 95 | |
503e1639 RZ |
96 | switch (rev) { |
97 | case 0x0: | |
9ab4650f | 98 | return IMX_CHIP_REVISION_1_0; |
503e1639 | 99 | case 0x2: |
9ab4650f | 100 | return IMX_CHIP_REVISION_2_0; |
503e1639 RZ |
101 | case 0x3: |
102 | return IMX_CHIP_REVISION_2_1; | |
103 | default: | |
104 | return IMX_CHIP_REVISION_UNKNOWN; | |
105 | } | |
9ab4650f DN |
106 | } |
107 | ||
b66ff7a2 DN |
108 | /* |
109 | * Returns: | |
110 | * the silicon revision of the cpu | |
b66ff7a2 DN |
111 | */ |
112 | int mx53_revision(void) | |
113 | { | |
c52c9835 JL |
114 | if (mx5_cpu_rev == -1) |
115 | mx5_cpu_rev = get_mx53_srev(); | |
b66ff7a2 | 116 | |
c52c9835 | 117 | return mx5_cpu_rev; |
b66ff7a2 DN |
118 | } |
119 | EXPORT_SYMBOL(mx53_revision); |