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9daaf31a SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
14 | #include <linux/irqdomain.h> | |
15 | #include <linux/of_irq.h> | |
16 | #include <linux/of_platform.h> | |
17 | #include <asm/mach/arch.h> | |
18 | #include <asm/mach/time.h> | |
19 | #include <mach/common.h> | |
20 | #include <mach/mx51.h> | |
21 | ||
22 | /* | |
23 | * Lookup table for attaching a specific name and platform_data pointer to | |
24 | * devices as they get created by of_platform_populate(). Ideally this table | |
25 | * would not exist, but the current clock implementation depends on some devices | |
26 | * having a specific name. | |
27 | */ | |
28 | static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = { | |
29 | OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL), | |
30 | OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL), | |
31 | OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL), | |
32 | OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL), | |
33 | OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL), | |
34 | OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL), | |
35 | OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL), | |
36 | OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL), | |
37 | OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL), | |
38 | OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL), | |
39 | OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL), | |
40 | OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx-i2c.0", NULL), | |
41 | OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx-i2c.1", NULL), | |
42 | OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL), | |
43 | OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL), | |
44 | { /* sentinel */ } | |
45 | }; | |
46 | ||
2a3267a4 | 47 | static int __init imx51_tzic_add_irq_domain(struct device_node *np, |
9daaf31a SG |
48 | struct device_node *interrupt_parent) |
49 | { | |
6b783f7c | 50 | irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL); |
2a3267a4 | 51 | return 0; |
9daaf31a SG |
52 | } |
53 | ||
2a3267a4 | 54 | static int __init imx51_gpio_add_irq_domain(struct device_node *np, |
9daaf31a SG |
55 | struct device_node *interrupt_parent) |
56 | { | |
04aafd71 | 57 | static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; |
9daaf31a | 58 | |
04aafd71 | 59 | gpio_irq_base -= 32; |
6b783f7c | 60 | irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL); |
2a3267a4 SG |
61 | |
62 | return 0; | |
9daaf31a SG |
63 | } |
64 | ||
65 | static const struct of_device_id imx51_irq_match[] __initconst = { | |
66 | { .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, }, | |
67 | { .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, }, | |
68 | { /* sentinel */ } | |
69 | }; | |
70 | ||
71 | static const struct of_device_id imx51_iomuxc_of_match[] __initconst = { | |
72 | { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, }, | |
73 | { /* sentinel */ } | |
74 | }; | |
75 | ||
76 | static void __init imx51_dt_init(void) | |
77 | { | |
78 | struct device_node *node; | |
79 | const struct of_device_id *of_id; | |
80 | void (*func)(void); | |
81 | ||
82 | of_irq_init(imx51_irq_match); | |
83 | ||
84 | node = of_find_matching_node(NULL, imx51_iomuxc_of_match); | |
85 | if (node) { | |
86 | of_id = of_match_node(imx51_iomuxc_of_match, node); | |
87 | func = of_id->data; | |
88 | func(); | |
89 | of_node_put(node); | |
90 | } | |
91 | ||
92 | of_platform_populate(NULL, of_default_bus_match_table, | |
93 | imx51_auxdata_lookup, NULL); | |
94 | } | |
95 | ||
96 | static void __init imx51_timer_init(void) | |
97 | { | |
98 | mx51_clocks_init_dt(); | |
99 | } | |
100 | ||
101 | static struct sys_timer imx51_timer = { | |
102 | .init = imx51_timer_init, | |
103 | }; | |
104 | ||
105 | static const char *imx51_dt_board_compat[] __initdata = { | |
106 | "fsl,imx51-babbage", | |
3f8976d9 | 107 | "fsl,imx51", |
9daaf31a SG |
108 | NULL |
109 | }; | |
110 | ||
111 | DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)") | |
112 | .map_io = mx51_map_io, | |
113 | .init_early = imx51_init_early, | |
114 | .init_irq = mx51_init_irq, | |
115 | .handle_irq = imx51_handle_irq, | |
116 | .timer = &imx51_timer, | |
117 | .init_machine = imx51_dt_init, | |
118 | .dt_compat = imx51_dt_board_compat, | |
65ea7884 | 119 | .restart = mxc_restart, |
9daaf31a | 120 | MACHINE_END |