[deliverable/linux.git] / arch / arm / mach-imx / mach-imx6q.c

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/cpuidle.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
#include <linux/regmap.h>
#include <linux/micrel_phy.h>
#include <linux/mfd/syscon.h>
#include <asm/cpuidle.h>
#include <asm/smp_twd.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/system_misc.h>

#include "common.h"
#include "cpuidle.h"
#include "hardware.h"

#define IMX6Q_ANALOG_DIGPROG	0x260

static int imx6q_revision(void)
{
	struct device_node *np;
	void __iomem *base;
	static u32 rev;

	if (!rev) {
		np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
		if (!np)
			return IMX_CHIP_REVISION_UNKNOWN;
		base = of_iomap(np, 0);
		if (!base) {
			of_node_put(np);
			return IMX_CHIP_REVISION_UNKNOWN;
		}
		rev =  readl_relaxed(base + IMX6Q_ANALOG_DIGPROG);
		iounmap(base);
		of_node_put(np);
	}

	switch (rev & 0xff) {
	case 0:
		return IMX_CHIP_REVISION_1_0;
	case 1:
		return IMX_CHIP_REVISION_1_1;
	case 2:
		return IMX_CHIP_REVISION_1_2;
	default:
		return IMX_CHIP_REVISION_UNKNOWN;
	}
}

void imx6q_restart(char mode, const char *cmd)
{
	struct device_node *np;
	void __iomem *wdog_base;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	wdog_base = of_iomap(np, 0);
	if (!wdog_base)
		goto soft;

	imx_src_prepare_restart();

	/* enable wdog */
	writew_relaxed(1 << 2, wdog_base);
	/* write twice to ensure the request will not get ignored */
	writew_relaxed(1 << 2, wdog_base);

	/* wait for reset to assert ... */
	mdelay(500);

	pr_err("Watchdog reset failed to assert reset\n");

	/* delay to allow the serial port to show the message */
	mdelay(50);

soft:
	/* we'll take a jump through zero as a poor second */
	soft_restart(0);
}

/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
static int ksz9021rn_phy_fixup(struct phy_device *phydev)
{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
		/* min rx data delay */
		phy_write(phydev, 0x0b, 0x8105);
		phy_write(phydev, 0x0c, 0x0000);

		/* max rx/tx clock delay, min rx/tx control delay */
		phy_write(phydev, 0x0b, 0x8104);
		phy_write(phydev, 0x0c, 0xf0f0);
		phy_write(phydev, 0x0b, 0x104);
	}

	return 0;
}

static void __init imx6q_sabrelite_cko1_setup(void)
{
	struct clk *cko1_sel, *ahb, *cko1;
	unsigned long rate;

	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	ahb = clk_get_sys(NULL, "ahb");
	cko1 = clk_get_sys(NULL, "cko1");
	if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
		pr_err("cko1 setup failed!\n");
		goto put_clk;
	}
	clk_set_parent(cko1_sel, ahb);
	rate = clk_round_rate(cko1, 16000000);
	clk_set_rate(cko1, rate);
put_clk:
	if (!IS_ERR(cko1_sel))
		clk_put(cko1_sel);
	if (!IS_ERR(ahb))
		clk_put(ahb);
	if (!IS_ERR(cko1))
		clk_put(cko1);
}

static void __init imx6q_sabrelite_init(void)
{
	if (IS_BUILTIN(CONFIG_PHYLIB))
		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
				ksz9021rn_phy_fixup);
	imx6q_sabrelite_cko1_setup();
}

static void __init imx6q_1588_init(void)
{
	struct regmap *gpr;

	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr))
		regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
	else
		pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");

}
static void __init imx6q_usb_init(void)
{
	struct regmap *anatop;

#define HW_ANADIG_USB1_CHRG_DETECT		0x000001b0
#define HW_ANADIG_USB2_CHRG_DETECT		0x00000210

#define BM_ANADIG_USB_CHRG_DETECT_EN_B		0x00100000
#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B	0x00080000

	anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
	if (!IS_ERR(anatop)) {
		/*
		 * The external charger detector needs to be disabled,
		 * or the signal at DP will be poor
		 */
		regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
				BM_ANADIG_USB_CHRG_DETECT_EN_B
				| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
		regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
				BM_ANADIG_USB_CHRG_DETECT_EN_B |
				BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
	} else {
		pr_warn("failed to find fsl,imx6q-anatop regmap\n");
	}
}

static void __init imx6q_init_machine(void)
{
	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
		imx6q_sabrelite_init();

	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);

	imx6q_pm_init();
	imx6q_usb_init();
	imx6q_1588_init();
}

static struct cpuidle_driver imx6q_cpuidle_driver = {
	.name			= "imx6q_cpuidle",
	.owner			= THIS_MODULE,
	.en_core_tk_irqen	= 1,
	.states[0]		= ARM_CPUIDLE_WFI_STATE,
	.state_count		= 1,
};

static void __init imx6q_init_late(void)
{
	imx_cpuidle_init(&imx6q_cpuidle_driver);
}

static void __init imx6q_map_io(void)
{
	imx_lluart_map_io();
	imx_scu_map_io();
	imx6q_clock_map_io();
}

static const struct of_device_id imx6q_irq_match[] __initconst = {
	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
	{ /* sentinel */ }
};

static void __init imx6q_init_irq(void)
{
	l2x0_of_init(0, ~0UL);
	imx_src_init();
	imx_gpc_init();
	of_irq_init(imx6q_irq_match);
}

static void __init imx6q_timer_init(void)
{
	mx6q_clocks_init();
	twd_local_timer_of_register();
	imx_print_silicon_rev("i.MX6Q", imx6q_revision());
}

static const char *imx6q_dt_compat[] __initdata = {
	"fsl,imx6q",
	NULL,
};

DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
	.smp		= smp_ops(imx_smp_ops),
	.map_io		= imx6q_map_io,
	.init_irq	= imx6q_init_irq,
	.handle_irq	= imx6q_handle_irq,
	.init_time	= imx6q_timer_init,
	.init_machine	= imx6q_init_machine,
	.init_late      = imx6q_init_late,
	.dt_compat	= imx6q_dt_compat,
	.restart	= imx6q_restart,
MACHINE_END
Commit	Line	Data
13eed989 SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
a258561d RZ	13	#include <linux/clk.h>
a258561d RZ	14	#include <linux/clkdev.h>
b9d18dc3	15	#include <linux/cpuidle.h>
0575fb75	16	#include <linux/delay.h>
b9d18dc3	17	#include <linux/export.h>
13eed989	18	#include <linux/init.h>
0575fb75	19	#include <linux/io.h>
13eed989	20	#include <linux/irq.h>
13eed989	21	#include <linux/of.h>
0575fb75	22	#include <linux/of_address.h>
13eed989 SG	23	#include <linux/of_irq.h>
13eed989 SG	24	#include <linux/of_platform.h>
477fce49	25	#include <linux/phy.h>
baa64151	26	#include <linux/regmap.h>
477fce49	27	#include <linux/micrel_phy.h>
baa64151	28	#include <linux/mfd/syscon.h>
b9d18dc3	29	#include <asm/cpuidle.h>
58458e03	30	#include <asm/smp_twd.h>
13eed989 SG	31	#include <asm/hardware/cache-l2x0.h>
	32	#include <asm/hardware/gic.h>
	33	#include <asm/mach/arch.h>
	34	#include <asm/mach/time.h>
9f97da78	35	#include <asm/system_misc.h>
13eed989	36
e3372474	37	#include "common.h"
e29248c9	38	#include "cpuidle.h"
50f2de61	39	#include "hardware.h"
b9d18dc3	40
b29b3e6f SG	41	#define IMX6Q_ANALOG_DIGPROG 0x260
	42
	43	static int imx6q_revision(void)
	44	{
	45	struct device_node *np;
	46	void __iomem *base;
	47	static u32 rev;
	48
	49	if (!rev) {
	50	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
	51	if (!np)
	52	return IMX_CHIP_REVISION_UNKNOWN;
	53	base = of_iomap(np, 0);
	54	if (!base) {
	55	of_node_put(np);
	56	return IMX_CHIP_REVISION_UNKNOWN;
	57	}
	58	rev = readl_relaxed(base + IMX6Q_ANALOG_DIGPROG);
	59	iounmap(base);
	60	of_node_put(np);
	61	}
	62
	63	switch (rev & 0xff) {
	64	case 0:
	65	return IMX_CHIP_REVISION_1_0;
	66	case 1:
	67	return IMX_CHIP_REVISION_1_1;
	68	case 2:
	69	return IMX_CHIP_REVISION_1_2;
	70	default:
	71	return IMX_CHIP_REVISION_UNKNOWN;
	72	}
	73	}
	74
0575fb75 SG	75	void imx6q_restart(char mode, const char *cmd)
	76	{
	77	struct device_node *np;
	78	void __iomem *wdog_base;
	79
	80	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
	81	wdog_base = of_iomap(np, 0);
	82	if (!wdog_base)
	83	goto soft;
	84
	85	imx_src_prepare_restart();
	86
	87	/* enable wdog */
	88	writew_relaxed(1 << 2, wdog_base);
	89	/* write twice to ensure the request will not get ignored */
	90	writew_relaxed(1 << 2, wdog_base);
	91
	92	/* wait for reset to assert ... */
	93	mdelay(500);
	94
	95	pr_err("Watchdog reset failed to assert reset\n");
	96
	97	/* delay to allow the serial port to show the message */
	98	mdelay(50);
	99
	100	soft:
	101	/* we'll take a jump through zero as a poor second */
	102	soft_restart(0);
	103	}
	104
477fce49 RZ	105	/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
	106	static int ksz9021rn_phy_fixup(struct phy_device *phydev)
	107	{
9f9ba0fd	108	if (IS_BUILTIN(CONFIG_PHYLIB)) {
ef441806 SG	109	/* min rx data delay */
	110	phy_write(phydev, 0x0b, 0x8105);
	111	phy_write(phydev, 0x0c, 0x0000);
477fce49	112
ef441806 SG	113	/* max rx/tx clock delay, min rx/tx control delay */
	114	phy_write(phydev, 0x0b, 0x8104);
	115	phy_write(phydev, 0x0c, 0xf0f0);
	116	phy_write(phydev, 0x0b, 0x104);
	117	}
477fce49 RZ	118
	119	return 0;
	120	}
	121
a258561d RZ	122	static void __init imx6q_sabrelite_cko1_setup(void)
	123	{
	124	struct clk cko1_sel, ahb, *cko1;
	125	unsigned long rate;
	126
	127	cko1_sel = clk_get_sys(NULL, "cko1_sel");
	128	ahb = clk_get_sys(NULL, "ahb");
	129	cko1 = clk_get_sys(NULL, "cko1");
	130	if (IS_ERR(cko1_sel) \|\| IS_ERR(ahb) \|\| IS_ERR(cko1)) {
	131	pr_err("cko1 setup failed!\n");
	132	goto put_clk;
	133	}
	134	clk_set_parent(cko1_sel, ahb);
	135	rate = clk_round_rate(cko1, 16000000);
	136	clk_set_rate(cko1, rate);
a258561d RZ	137	put_clk:
	138	if (!IS_ERR(cko1_sel))
	139	clk_put(cko1_sel);
	140	if (!IS_ERR(ahb))
	141	clk_put(ahb);
	142	if (!IS_ERR(cko1))
	143	clk_put(cko1);
	144	}
	145
071dea50 RZ	146	static void __init imx6q_sabrelite_init(void)
071dea50 RZ	147	{
9f9ba0fd	148	if (IS_BUILTIN(CONFIG_PHYLIB))
ef441806	149	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
071dea50	150	ksz9021rn_phy_fixup);
a258561d	151	imx6q_sabrelite_cko1_setup();
071dea50 RZ	152	}
071dea50 RZ	153
d6e0d9fc FL	154	static void __init imx6q_1588_init(void)
	155	{
	156	struct regmap *gpr;
	157
	158	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	159	if (!IS_ERR(gpr))
	160	regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
	161	else
	162	pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
	163
	164	}
396bf1c2 RZ	165	static void __init imx6q_usb_init(void)
396bf1c2 RZ	166	{
baa64151	167	struct regmap *anatop;
396bf1c2 RZ	168
	169	#define HW_ANADIG_USB1_CHRG_DETECT 0x000001b0
	170	#define HW_ANADIG_USB2_CHRG_DETECT 0x00000210
	171
	172	#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x00100000
	173	#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x00080000
	174
baa64151 DA	175	anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
	176	if (!IS_ERR(anatop)) {
	177	/*
	178	* The external charger detector needs to be disabled,
	179	* or the signal at DP will be poor
	180	*/
	181	regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
	182	BM_ANADIG_USB_CHRG_DETECT_EN_B
	183	\| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
	184	regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
	185	BM_ANADIG_USB_CHRG_DETECT_EN_B \|
	186	BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
	187	} else {
	188	pr_warn("failed to find fsl,imx6q-anatop regmap\n");
	189	}
396bf1c2 RZ	190	}
396bf1c2 RZ	191
13eed989 SG	192	static void __init imx6q_init_machine(void)
13eed989 SG	193	{
477fce49	194	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
071dea50	195	imx6q_sabrelite_init();
477fce49	196
13eed989 SG	197	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
	198
	199	imx6q_pm_init();
396bf1c2	200	imx6q_usb_init();
d6e0d9fc	201	imx6q_1588_init();
13eed989 SG	202	}
13eed989 SG	203
b9d18dc3 RL	204	static struct cpuidle_driver imx6q_cpuidle_driver = {
	205	.name = "imx6q_cpuidle",
	206	.owner = THIS_MODULE,
	207	.en_core_tk_irqen = 1,
	208	.states[0] = ARM_CPUIDLE_WFI_STATE,
	209	.state_count = 1,
	210	};
	211
	212	static void __init imx6q_init_late(void)
	213	{
	214	imx_cpuidle_init(&imx6q_cpuidle_driver);
	215	}
	216
13eed989 SG	217	static void __init imx6q_map_io(void)
	218	{
	219	imx_lluart_map_io();
	220	imx_scu_map_io();
f475058f	221	imx6q_clock_map_io();
13eed989 SG	222	}
13eed989 SG	223
13eed989 SG	224	static const struct of_device_id imx6q_irq_match[] __initconst = {
13eed989 SG	225	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
13eed989 SG	226	{ /* sentinel */ }
	227	};
	228
	229	static void __init imx6q_init_irq(void)
	230	{
	231	l2x0_of_init(0, ~0UL);
	232	imx_src_init();
	233	imx_gpc_init();
	234	of_irq_init(imx6q_irq_match);
	235	}
	236
	237	static void __init imx6q_timer_init(void)
	238	{
	239	mx6q_clocks_init();
58458e03	240	twd_local_timer_of_register();
b29b3e6f	241	imx_print_silicon_rev("i.MX6Q", imx6q_revision());
13eed989 SG	242	}
13eed989 SG	243
13eed989	244	static const char *imx6q_dt_compat[] __initdata = {
3f8976d9	245	"fsl,imx6q",
13eed989 SG	246	NULL,
	247	};
	248
	249	DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
e4f2d979	250	.smp = smp_ops(imx_smp_ops),
13eed989 SG	251	.map_io = imx6q_map_io,
	252	.init_irq = imx6q_init_irq,
	253	.handle_irq = imx6q_handle_irq,
6bb27d73	254	.init_time = imx6q_timer_init,
13eed989	255	.init_machine = imx6q_init_machine,
b9d18dc3	256	.init_late = imx6q_init_late,
13eed989	257	.dt_compat = imx6q_dt_compat,
0575fb75	258	.restart = imx6q_restart,
13eed989	259	MACHINE_END