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aefa1c6e FE |
1 | /* |
2 | * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
d17e1c1a | 3 | * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix |
aefa1c6e FE |
4 | * |
5 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | |
6 | * | |
25af2d9f AG |
7 | * Copyright (C) 2011 Meprolight, Ltd. |
8 | * Alex Gershgorin <alexg@meprolight.com> | |
9 | * | |
10 | * Modified from i.MX31 3-Stack Development System | |
11 | * | |
aefa1c6e FE |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
aefa1c6e FE |
21 | */ |
22 | ||
767c38b2 UKK |
23 | /* |
24 | * This machine is known as: | |
25 | * - i.MX35 3-Stack Development System | |
26 | * - i.MX35 Platform Development Kit (i.MX35 PDK) | |
27 | */ | |
28 | ||
aefa1c6e FE |
29 | #include <linux/types.h> |
30 | #include <linux/init.h> | |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/memory.h> | |
33 | #include <linux/gpio.h> | |
130a0dda | 34 | #include <linux/usb/otg.h> |
aefa1c6e | 35 | |
d17e1c1a MKB |
36 | #include <linux/mtd/physmap.h> |
37 | ||
aefa1c6e FE |
38 | #include <asm/mach-types.h> |
39 | #include <asm/mach/arch.h> | |
40 | #include <asm/mach/time.h> | |
41 | #include <asm/mach/map.h> | |
25af2d9f | 42 | #include <asm/memblock.h> |
aefa1c6e FE |
43 | |
44 | #include <mach/hardware.h> | |
45 | #include <mach/common.h> | |
aefa1c6e | 46 | #include <mach/iomux-mx35.h> |
2c6605de XJ |
47 | #include <mach/irqs.h> |
48 | #include <mach/3ds_debugboard.h> | |
881e09f8 | 49 | #include <video/platform_lcd.h> |
aefa1c6e | 50 | |
25af2d9f AG |
51 | #include <media/soc_camera.h> |
52 | ||
6eafde5f | 53 | #include "devices-imx35.h" |
aefa1c6e | 54 | |
881e09f8 | 55 | #define GPIO_MC9S08DZ60_GPS_ENABLE 0 |
56 | #define GPIO_MC9S08DZ60_HDD_ENABLE 4 | |
57 | #define GPIO_MC9S08DZ60_WIFI_ENABLE 5 | |
58 | #define GPIO_MC9S08DZ60_LCD_ENABLE 6 | |
59 | #define GPIO_MC9S08DZ60_SPEAKER_ENABLE 8 | |
60 | ||
61 | static const struct fb_videomode fb_modedb[] = { | |
62 | { | |
63 | /* 800x480 @ 55 Hz */ | |
64 | .name = "Ceramate-CLAA070VC01", | |
65 | .refresh = 55, | |
66 | .xres = 800, | |
67 | .yres = 480, | |
68 | .pixclock = 40000, | |
69 | .left_margin = 40, | |
70 | .right_margin = 40, | |
71 | .upper_margin = 5, | |
72 | .lower_margin = 5, | |
73 | .hsync_len = 20, | |
74 | .vsync_len = 10, | |
75 | .sync = FB_SYNC_OE_ACT_HIGH, | |
76 | .vmode = FB_VMODE_NONINTERLACED, | |
77 | .flag = 0, | |
78 | }, | |
79 | }; | |
80 | ||
81 | static const struct ipu_platform_data mx3_ipu_data __initconst = { | |
82 | .irq_base = MXC_IPU_IRQ_START, | |
83 | }; | |
84 | ||
85 | static struct mx3fb_platform_data mx3fb_pdata __initdata = { | |
86 | .name = "Ceramate-CLAA070VC01", | |
87 | .mode = fb_modedb, | |
88 | .num_modes = ARRAY_SIZE(fb_modedb), | |
89 | }; | |
90 | ||
91 | static struct i2c_board_info __initdata i2c_devices_3ds[] = { | |
92 | { | |
93 | I2C_BOARD_INFO("mc9s08dz60", 0x69), | |
94 | }, | |
95 | }; | |
96 | ||
97 | static int lcd_power_gpio = -ENXIO; | |
98 | ||
99 | static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip, | |
eb26e877 | 100 | const void *data) |
881e09f8 | 101 | { |
102 | return !strcmp(chip->label, data); | |
103 | } | |
104 | ||
105 | static void mx35_3ds_lcd_set_power( | |
106 | struct plat_lcd_data *pd, unsigned int power) | |
107 | { | |
108 | struct gpio_chip *chip; | |
109 | ||
110 | if (!gpio_is_valid(lcd_power_gpio)) { | |
111 | chip = gpiochip_find( | |
112 | "mc9s08dz60", mc9s08dz60_gpiochip_match); | |
113 | if (chip) { | |
114 | lcd_power_gpio = | |
115 | chip->base + GPIO_MC9S08DZ60_LCD_ENABLE; | |
116 | if (gpio_request(lcd_power_gpio, "lcd_power") < 0) { | |
117 | pr_err("error: gpio already requested!\n"); | |
118 | lcd_power_gpio = -ENXIO; | |
119 | } | |
120 | } else { | |
121 | pr_err("error: didn't find mc9s08dz60 gpio chip\n"); | |
122 | } | |
123 | } | |
124 | ||
125 | if (gpio_is_valid(lcd_power_gpio)) | |
126 | gpio_set_value_cansleep(lcd_power_gpio, power); | |
127 | } | |
128 | ||
129 | static struct plat_lcd_data mx35_3ds_lcd_data = { | |
130 | .set_power = mx35_3ds_lcd_set_power, | |
131 | }; | |
132 | ||
133 | static struct platform_device mx35_3ds_lcd = { | |
134 | .name = "platform-lcd", | |
135 | .dev.platform_data = &mx35_3ds_lcd_data, | |
136 | }; | |
137 | ||
7cf7381f | 138 | #define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 1)) |
2c6605de | 139 | |
6eafde5f | 140 | static const struct imxuart_platform_data uart_pdata __initconst = { |
aefa1c6e FE |
141 | .flags = IMXUART_HAVE_RTSCTS, |
142 | }; | |
143 | ||
d17e1c1a MKB |
144 | static struct physmap_flash_data mx35pdk_flash_data = { |
145 | .width = 2, | |
146 | }; | |
147 | ||
148 | static struct resource mx35pdk_flash_resource = { | |
149 | .start = MX35_CS0_BASE_ADDR, | |
150 | .end = MX35_CS0_BASE_ADDR + SZ_64M - 1, | |
151 | .flags = IORESOURCE_MEM, | |
152 | }; | |
153 | ||
154 | static struct platform_device mx35pdk_flash = { | |
155 | .name = "physmap-flash", | |
156 | .id = 0, | |
157 | .dev = { | |
158 | .platform_data = &mx35pdk_flash_data, | |
159 | }, | |
160 | .resource = &mx35pdk_flash_resource, | |
161 | .num_resources = 1, | |
162 | }; | |
163 | ||
81aa1720 MKB |
164 | static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = { |
165 | .width = 1, | |
166 | .hw_ecc = 1, | |
167 | .flash_bbt = 1, | |
168 | }; | |
169 | ||
aefa1c6e | 170 | static struct platform_device *devices[] __initdata = { |
d17e1c1a | 171 | &mx35pdk_flash, |
aefa1c6e FE |
172 | }; |
173 | ||
8f5260c8 | 174 | static iomux_v3_cfg_t mx35pdk_pads[] = { |
aefa1c6e FE |
175 | /* UART1 */ |
176 | MX35_PAD_CTS1__UART1_CTS, | |
177 | MX35_PAD_RTS1__UART1_RTS, | |
178 | MX35_PAD_TXD1__UART1_TXD_MUX, | |
179 | MX35_PAD_RXD1__UART1_RXD_MUX, | |
180 | /* FEC */ | |
181 | MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, | |
182 | MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, | |
183 | MX35_PAD_FEC_RX_DV__FEC_RX_DV, | |
184 | MX35_PAD_FEC_COL__FEC_COL, | |
185 | MX35_PAD_FEC_RDATA0__FEC_RDATA_0, | |
186 | MX35_PAD_FEC_TDATA0__FEC_TDATA_0, | |
187 | MX35_PAD_FEC_TX_EN__FEC_TX_EN, | |
188 | MX35_PAD_FEC_MDC__FEC_MDC, | |
189 | MX35_PAD_FEC_MDIO__FEC_MDIO, | |
190 | MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, | |
191 | MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, | |
192 | MX35_PAD_FEC_CRS__FEC_CRS, | |
193 | MX35_PAD_FEC_RDATA1__FEC_RDATA_1, | |
194 | MX35_PAD_FEC_TDATA1__FEC_TDATA_1, | |
195 | MX35_PAD_FEC_RDATA2__FEC_RDATA_2, | |
196 | MX35_PAD_FEC_TDATA2__FEC_TDATA_2, | |
197 | MX35_PAD_FEC_RDATA3__FEC_RDATA_3, | |
198 | MX35_PAD_FEC_TDATA3__FEC_TDATA_3, | |
9c2daf15 HH |
199 | /* USBOTG */ |
200 | MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, | |
201 | MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, | |
ab3d8b58 MKB |
202 | /* USBH1 */ |
203 | MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, | |
204 | MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, | |
6207c833 SG |
205 | /* SDCARD */ |
206 | MX35_PAD_SD1_CMD__ESDHC1_CMD, | |
207 | MX35_PAD_SD1_CLK__ESDHC1_CLK, | |
208 | MX35_PAD_SD1_DATA0__ESDHC1_DAT0, | |
209 | MX35_PAD_SD1_DATA1__ESDHC1_DAT1, | |
210 | MX35_PAD_SD1_DATA2__ESDHC1_DAT2, | |
211 | MX35_PAD_SD1_DATA3__ESDHC1_DAT3, | |
352cd9a0 FE |
212 | /* I2C1 */ |
213 | MX35_PAD_I2C1_CLK__I2C1_SCL, | |
214 | MX35_PAD_I2C1_DAT__I2C1_SDA, | |
881e09f8 | 215 | /* Display */ |
216 | MX35_PAD_LD0__IPU_DISPB_DAT_0, | |
217 | MX35_PAD_LD1__IPU_DISPB_DAT_1, | |
218 | MX35_PAD_LD2__IPU_DISPB_DAT_2, | |
219 | MX35_PAD_LD3__IPU_DISPB_DAT_3, | |
220 | MX35_PAD_LD4__IPU_DISPB_DAT_4, | |
221 | MX35_PAD_LD5__IPU_DISPB_DAT_5, | |
222 | MX35_PAD_LD6__IPU_DISPB_DAT_6, | |
223 | MX35_PAD_LD7__IPU_DISPB_DAT_7, | |
224 | MX35_PAD_LD8__IPU_DISPB_DAT_8, | |
225 | MX35_PAD_LD9__IPU_DISPB_DAT_9, | |
226 | MX35_PAD_LD10__IPU_DISPB_DAT_10, | |
227 | MX35_PAD_LD11__IPU_DISPB_DAT_11, | |
228 | MX35_PAD_LD12__IPU_DISPB_DAT_12, | |
229 | MX35_PAD_LD13__IPU_DISPB_DAT_13, | |
230 | MX35_PAD_LD14__IPU_DISPB_DAT_14, | |
231 | MX35_PAD_LD15__IPU_DISPB_DAT_15, | |
232 | MX35_PAD_LD16__IPU_DISPB_DAT_16, | |
233 | MX35_PAD_LD17__IPU_DISPB_DAT_17, | |
234 | MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, | |
235 | MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, | |
236 | MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, | |
237 | MX35_PAD_CONTRAST__IPU_DISPB_CONTR, | |
238 | MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, | |
239 | MX35_PAD_D3_REV__IPU_DISPB_D3_REV, | |
240 | MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, | |
25af2d9f AG |
241 | /* CSI */ |
242 | MX35_PAD_TX1__IPU_CSI_D_6, | |
243 | MX35_PAD_TX0__IPU_CSI_D_7, | |
244 | MX35_PAD_CSI_D8__IPU_CSI_D_8, | |
245 | MX35_PAD_CSI_D9__IPU_CSI_D_9, | |
246 | MX35_PAD_CSI_D10__IPU_CSI_D_10, | |
247 | MX35_PAD_CSI_D11__IPU_CSI_D_11, | |
248 | MX35_PAD_CSI_D12__IPU_CSI_D_12, | |
249 | MX35_PAD_CSI_D13__IPU_CSI_D_13, | |
250 | MX35_PAD_CSI_D14__IPU_CSI_D_14, | |
251 | MX35_PAD_CSI_D15__IPU_CSI_D_15, | |
252 | MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC, | |
253 | MX35_PAD_CSI_MCLK__IPU_CSI_MCLK, | |
254 | MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK, | |
255 | MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC, | |
256 | }; | |
257 | ||
258 | /* | |
259 | * Camera support | |
260 | */ | |
261 | static phys_addr_t mx3_camera_base __initdata; | |
262 | #define MX35_3DS_CAMERA_BUF_SIZE SZ_8M | |
263 | ||
264 | static const struct mx3_camera_pdata mx35_3ds_camera_pdata __initconst = { | |
265 | .flags = MX3_CAMERA_DATAWIDTH_8, | |
266 | .mclk_10khz = 2000, | |
267 | }; | |
268 | ||
269 | static int __init imx35_3ds_init_camera(void) | |
270 | { | |
271 | int dma, ret = -ENOMEM; | |
272 | struct platform_device *pdev = | |
273 | imx35_alloc_mx3_camera(&mx35_3ds_camera_pdata); | |
274 | ||
275 | if (IS_ERR(pdev)) | |
276 | return PTR_ERR(pdev); | |
277 | ||
278 | if (!mx3_camera_base) | |
279 | goto err; | |
280 | ||
281 | dma = dma_declare_coherent_memory(&pdev->dev, | |
282 | mx3_camera_base, mx3_camera_base, | |
283 | MX35_3DS_CAMERA_BUF_SIZE, | |
284 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); | |
285 | ||
286 | if (!(dma & DMA_MEMORY_MAP)) | |
287 | goto err; | |
288 | ||
289 | ret = platform_device_add(pdev); | |
290 | if (ret) | |
291 | err: | |
292 | platform_device_put(pdev); | |
293 | ||
294 | return ret; | |
295 | } | |
296 | ||
297 | static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = { | |
298 | .irq_base = MXC_IPU_IRQ_START, | |
299 | }; | |
300 | ||
301 | static struct i2c_board_info mx35_3ds_i2c_camera = { | |
302 | I2C_BOARD_INFO("ov2640", 0x30), | |
303 | }; | |
304 | ||
305 | static struct soc_camera_link iclink_ov2640 = { | |
306 | .bus_id = 0, | |
307 | .board_info = &mx35_3ds_i2c_camera, | |
308 | .i2c_adapter_id = 0, | |
309 | .power = NULL, | |
310 | }; | |
311 | ||
312 | static struct platform_device mx35_3ds_ov2640 = { | |
313 | .name = "soc-camera-pdrv", | |
314 | .id = 0, | |
315 | .dev = { | |
316 | .platform_data = &iclink_ov2640, | |
317 | }, | |
9c2daf15 HH |
318 | }; |
319 | ||
4bd597b6 SH |
320 | static int mx35_3ds_otg_init(struct platform_device *pdev) |
321 | { | |
322 | return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); | |
323 | } | |
324 | ||
9c2daf15 | 325 | /* OTG config */ |
9e1dde33 | 326 | static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = { |
9c2daf15 HH |
327 | .operating_mode = FSL_USB2_DR_DEVICE, |
328 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, | |
1a46cce8 FE |
329 | .workaround = FLS_USB2_WORKAROUND_ENGCM09152, |
330 | /* | |
331 | * ENGCM09152 also requires a hardware change. | |
332 | * Please check the MX35 Chip Errata document for details. | |
333 | */ | |
aefa1c6e FE |
334 | }; |
335 | ||
130a0dda | 336 | static struct mxc_usbh_platform_data otg_pdata __initdata = { |
4bd597b6 | 337 | .init = mx35_3ds_otg_init, |
130a0dda | 338 | .portsc = MXC_EHCI_MODE_UTMI, |
130a0dda FE |
339 | }; |
340 | ||
4bd597b6 SH |
341 | static int mx35_3ds_usbh_init(struct platform_device *pdev) |
342 | { | |
343 | return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | | |
344 | MXC_EHCI_INTERNAL_PHY); | |
345 | } | |
346 | ||
ab3d8b58 | 347 | /* USB HOST config */ |
2d58de28 | 348 | static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { |
4bd597b6 | 349 | .init = mx35_3ds_usbh_init, |
ab3d8b58 | 350 | .portsc = MXC_EHCI_MODE_SERIAL, |
ab3d8b58 MKB |
351 | }; |
352 | ||
130a0dda FE |
353 | static int otg_mode_host; |
354 | ||
355 | static int __init mx35_3ds_otg_mode(char *options) | |
356 | { | |
357 | if (!strcmp(options, "host")) | |
358 | otg_mode_host = 1; | |
359 | else if (!strcmp(options, "device")) | |
360 | otg_mode_host = 0; | |
361 | else | |
362 | pr_info("otg_mode neither \"host\" nor \"device\". " | |
363 | "Defaulting to device\n"); | |
364 | return 0; | |
365 | } | |
366 | __setup("otg_mode=", mx35_3ds_otg_mode); | |
367 | ||
352cd9a0 FE |
368 | static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = { |
369 | .bitrate = 100000, | |
370 | }; | |
371 | ||
aefa1c6e FE |
372 | /* |
373 | * Board specific initialization. | |
374 | */ | |
e134fb2b | 375 | static void __init mx35_3ds_init(void) |
aefa1c6e | 376 | { |
881e09f8 | 377 | struct platform_device *imx35_fb_pdev; |
378 | ||
b78d8e59 SG |
379 | imx35_soc_init(); |
380 | ||
aefa1c6e FE |
381 | mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); |
382 | ||
6bd96f3c | 383 | imx35_add_fec(NULL); |
c496fa6b | 384 | imx35_add_imx2_wdt(NULL); |
aefa1c6e FE |
385 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
386 | ||
6eafde5f | 387 | imx35_add_imx_uart0(&uart_pdata); |
9c2daf15 | 388 | |
130a0dda FE |
389 | if (otg_mode_host) |
390 | imx35_add_mxc_ehci_otg(&otg_pdata); | |
81aa1720 | 391 | |
2d58de28 | 392 | imx35_add_mxc_ehci_hs(&usb_host_pdata); |
ab3d8b58 | 393 | |
130a0dda FE |
394 | if (!otg_mode_host) |
395 | imx35_add_fsl_usb2_udc(&usb_otg_pdata); | |
396 | ||
81aa1720 | 397 | imx35_add_mxc_nand(&mx35pdk_nand_board_info); |
124bf94a | 398 | imx35_add_sdhci_esdhc_imx(0, NULL); |
2c6605de XJ |
399 | |
400 | if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT)) | |
401 | pr_warn("Init of the debugboard failed, all " | |
402 | "devices on the debugboard are unusable.\n"); | |
352cd9a0 | 403 | imx35_add_imx_i2c0(&mx35_3ds_i2c0_data); |
881e09f8 | 404 | |
405 | i2c_register_board_info( | |
406 | 0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds)); | |
407 | ||
25af2d9f AG |
408 | imx35_add_ipu_core(&mx35_3ds_ipu_data); |
409 | platform_device_register(&mx35_3ds_ov2640); | |
410 | imx35_3ds_init_camera(); | |
411 | ||
881e09f8 | 412 | imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata); |
413 | mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev; | |
414 | platform_device_register(&mx35_3ds_lcd); | |
aefa1c6e FE |
415 | } |
416 | ||
417 | static void __init mx35pdk_timer_init(void) | |
418 | { | |
419 | mx35_clocks_init(); | |
420 | } | |
421 | ||
422 | struct sys_timer mx35pdk_timer = { | |
423 | .init = mx35pdk_timer_init, | |
424 | }; | |
425 | ||
25af2d9f AG |
426 | static void __init mx35_3ds_reserve(void) |
427 | { | |
428 | /* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ | |
429 | mx3_camera_base = arm_memblock_steal(MX35_3DS_CAMERA_BUF_SIZE, | |
430 | MX35_3DS_CAMERA_BUF_SIZE); | |
431 | } | |
432 | ||
aefa1c6e FE |
433 | MACHINE_START(MX35_3DS, "Freescale MX35PDK") |
434 | /* Maintainer: Freescale Semiconductor, Inc */ | |
dc8f1907 | 435 | .atag_offset = 0x100, |
97976e22 UKK |
436 | .map_io = mx35_map_io, |
437 | .init_early = imx35_init_early, | |
438 | .init_irq = mx35_init_irq, | |
ffa2ea3f | 439 | .handle_irq = imx35_handle_irq, |
97976e22 | 440 | .timer = &mx35pdk_timer, |
e134fb2b | 441 | .init_machine = mx35_3ds_init, |
25af2d9f | 442 | .reserve = mx35_3ds_reserve, |
65ea7884 | 443 | .restart = mxc_restart, |
aefa1c6e | 444 | MACHINE_END |