[deliverable/linux.git] / arch / arm / mach-imx / mm-imx3.c

/*
 *  Copyright (C) 1999,2000 Arm Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *    - add MX31 specific definitions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>

#include <asm/pgtable.h>
#include <asm/system_misc.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>

#include <mach/common.h>
#include <mach/devices-common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/irqs.h>

static void imx3_idle(void)
{
	unsigned long reg = 0;

	mx3_cpu_lp_set(MX3_WAIT);

	__asm__ __volatile__(
		/* disable I and D cache */
		"mrc p15, 0, %0, c1, c0, 0\n"
		"bic %0, %0, #0x00001000\n"
		"bic %0, %0, #0x00000004\n"
		"mcr p15, 0, %0, c1, c0, 0\n"
		/* invalidate I cache */
		"mov %0, #0\n"
		"mcr p15, 0, %0, c7, c5, 0\n"
		/* clear and invalidate D cache */
		"mov %0, #0\n"
		"mcr p15, 0, %0, c7, c14, 0\n"
		/* WFI */
		"mov %0, #0\n"
		"mcr p15, 0, %0, c7, c0, 4\n"
		"nop\n" "nop\n" "nop\n" "nop\n"
		"nop\n" "nop\n" "nop\n"
		/* enable I and D cache */
		"mrc p15, 0, %0, c1, c0, 0\n"
		"orr %0, %0, #0x00001000\n"
		"orr %0, %0, #0x00000004\n"
		"mcr p15, 0, %0, c1, c0, 0\n"
		: "=r" (reg));
}

static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
					 unsigned int mtype, void *caller)
{
	if (mtype == MT_DEVICE) {
		/*
		 * Access all peripherals below 0x80000000 as nonshared device
		 * on mx3, but leave l2cc alone.  Otherwise cache corruptions
		 * can occur.
		 */
		if (phys_addr < 0x80000000 &&
				!addr_in_module(phys_addr, MX3x_L2CC))
			mtype = MT_DEVICE_NONSHARED;
	}

	return __arm_ioremap_caller(phys_addr, size, mtype, caller);
}

void __init imx3_init_l2x0(void)
{
	void __iomem *l2x0_base;
	void __iomem *clkctl_base;

/*
 * First of all, we must repair broken chip settings. There are some
 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
 * Workaraound is to setup the correct register setting prior enabling the
 * L2 cache. This should not hurt already working CPUs, as they are using the
 * same value.
 */
#define L2_MEM_VAL 0x10

	clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
	if (clkctl_base != NULL) {
		writel(0x00000515, clkctl_base + L2_MEM_VAL);
		iounmap(clkctl_base);
	} else {
		pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
	}

	l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
	if (IS_ERR(l2x0_base)) {
		printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
				PTR_ERR(l2x0_base));
		return;
	}

	l2x0_init(l2x0_base, 0x00030024, 0x00000000);
}

#ifdef CONFIG_SOC_IMX31
static struct map_desc mx31_io_desc[] __initdata = {
	imx_map_entry(MX31, X_MEMC, MT_DEVICE),
	imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
	imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
	imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
	imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
};

/*
 * This function initializes the memory map. It is called during the
 * system startup to create static physical to virtual memory mappings
 * for the IO modules.
 */
void __init mx31_map_io(void)
{
	iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
}

void __init imx31_init_early(void)
{
	mxc_set_cpu_type(MXC_CPU_MX31);
	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
	arch_ioremap_caller = imx3_ioremap_caller;
	arm_pm_idle = imx3_idle;
}

void __init mx31_init_irq(void)
{
	mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
}

static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
	.per_2_per_addr = 1677,
};

static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
	.ap_2_ap_addr = 423,
	.ap_2_bp_addr = 829,
	.bp_2_ap_addr = 1029,
};

static struct sdma_platform_data imx31_sdma_pdata __initdata = {
	.fw_name = "sdma-imx31-to2.bin",
	.script_addrs = &imx31_to2_sdma_script,
};

static const struct resource imx31_audmux_res[] __initconst = {
	DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
};

void __init imx31_soc_init(void)
{
	int to_version = mx31_revision() >> 4;

	imx3_init_l2x0();

	mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
	mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
	mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);

	if (to_version == 1) {
		strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
			strlen(imx31_sdma_pdata.fw_name));
		imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
	}

	imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);

	imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
	imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));

	platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
					ARRAY_SIZE(imx31_audmux_res));
}
#endif /* ifdef CONFIG_SOC_IMX31 */

#ifdef CONFIG_SOC_IMX35
static struct map_desc mx35_io_desc[] __initdata = {
	imx_map_entry(MX35, X_MEMC, MT_DEVICE),
	imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
	imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
	imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
	imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
};

void __init mx35_map_io(void)
{
	iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
}

void __init imx35_init_early(void)
{
	mxc_set_cpu_type(MXC_CPU_MX35);
	mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
	mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
	arm_pm_idle = imx3_idle;
	arch_ioremap_caller = imx3_ioremap_caller;
}

void __init mx35_init_irq(void)
{
	mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
}

static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
	.ap_2_ap_addr = 642,
	.uart_2_mcu_addr = 817,
	.mcu_2_app_addr = 747,
	.uartsh_2_mcu_addr = 1183,
	.per_2_shp_addr = 1033,
	.mcu_2_shp_addr = 961,
	.ata_2_mcu_addr = 1333,
	.mcu_2_ata_addr = 1252,
	.app_2_mcu_addr = 683,
	.shp_2_per_addr = 1111,
	.shp_2_mcu_addr = 892,
};

static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
	.ap_2_ap_addr = 729,
	.uart_2_mcu_addr = 904,
	.per_2_app_addr = 1597,
	.mcu_2_app_addr = 834,
	.uartsh_2_mcu_addr = 1270,
	.per_2_shp_addr = 1120,
	.mcu_2_shp_addr = 1048,
	.ata_2_mcu_addr = 1429,
	.mcu_2_ata_addr = 1339,
	.app_2_per_addr = 1531,
	.app_2_mcu_addr = 770,
	.shp_2_per_addr = 1198,
	.shp_2_mcu_addr = 979,
};

static struct sdma_platform_data imx35_sdma_pdata __initdata = {
	.fw_name = "sdma-imx35-to2.bin",
	.script_addrs = &imx35_to2_sdma_script,
};

static const struct resource imx35_audmux_res[] __initconst = {
	DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
};

void __init imx35_soc_init(void)
{
	int to_version = mx35_revision() >> 4;

	imx3_init_l2x0();

	/* i.mx35 has the i.mx31 type gpio */
	mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
	mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
	mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);

	if (to_version == 1) {
		strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
			strlen(imx35_sdma_pdata.fw_name));
		imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
	}

	imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);

	/* Setup AIPS registers */
	imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
	imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));

	/* i.mx35 has the i.mx31 type audmux */
	platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
					ARRAY_SIZE(imx35_audmux_res));
}
#endif /* ifdef CONFIG_SOC_IMX35 */
Commit	Line	Data
27ad4bf7 UKK	1	/*
	2	* Copyright (C) 1999,2000 Arm Limited
	3	* Copyright (C) 2000 Deep Blue Solutions Ltd
	4	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	5	* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	6	* - add MX31 specific definitions
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*/
	18
	19	#include <linux/mm.h>
	20	#include <linux/init.h>
	21	#include <linux/err.h>
	22
	23	#include <asm/pgtable.h>
86dfe446	24	#include <asm/system_misc.h>
ddd5f51b	25	#include <asm/hardware/cache-l2x0.h>
27ad4bf7 UKK	26	#include <asm/mach/map.h>
	27
	28	#include <mach/common.h>
36223604	29	#include <mach/devices-common.h>
27ad4bf7 UKK	30	#include <mach/hardware.h>
27ad4bf7 UKK	31	#include <mach/iomux-v3.h>
27ad4bf7 UKK	32	#include <mach/irqs.h>
27ad4bf7 UKK	33
41e7daf2 SG	34	static void imx3_idle(void)
	35	{
	36	unsigned long reg = 0;
8c6d8319	37
3ac804e3 FE	38	mx3_cpu_lp_set(MX3_WAIT);
3ac804e3 FE	39
4a3ea244 NP	40	__asm__ __volatile__(
	41	/* disable I and D cache */
	42	"mrc p15, 0, %0, c1, c0, 0\n"
	43	"bic %0, %0, #0x00001000\n"
	44	"bic %0, %0, #0x00000004\n"
	45	"mcr p15, 0, %0, c1, c0, 0\n"
	46	/* invalidate I cache */
	47	"mov %0, #0\n"
	48	"mcr p15, 0, %0, c7, c5, 0\n"
	49	/* clear and invalidate D cache */
	50	"mov %0, #0\n"
	51	"mcr p15, 0, %0, c7, c14, 0\n"
	52	/* WFI */
	53	"mov %0, #0\n"
	54	"mcr p15, 0, %0, c7, c0, 4\n"
	55	"nop\n" "nop\n" "nop\n" "nop\n"
	56	"nop\n" "nop\n" "nop\n"
	57	/* enable I and D cache */
	58	"mrc p15, 0, %0, c1, c0, 0\n"
	59	"orr %0, %0, #0x00001000\n"
	60	"orr %0, %0, #0x00000004\n"
	61	"mcr p15, 0, %0, c1, c0, 0\n"
	62	: "=r" (reg));
41e7daf2 SG	63	}
41e7daf2 SG	64
c177aa98 RH	65	static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
c177aa98 RH	66	unsigned int mtype, void *caller)
f548897f SG	67	{
	68	if (mtype == MT_DEVICE) {
	69	/*
	70	* Access all peripherals below 0x80000000 as nonshared device
	71	* on mx3, but leave l2cc alone. Otherwise cache corruptions
	72	* can occur.
	73	*/
	74	if (phys_addr < 0x80000000 &&
	75	!addr_in_module(phys_addr, MX3x_L2CC))
	76	mtype = MT_DEVICE_NONSHARED;
	77	}
	78
c177aa98	79	return __arm_ioremap_caller(phys_addr, size, mtype, caller);
f548897f SG	80	}
f548897f SG	81
9418ba30	82	void __init imx3_init_l2x0(void)
ddd5f51b SG	83	{
	84	void __iomem *l2x0_base;
	85	void __iomem *clkctl_base;
	86
	87	/*
	88	* First of all, we must repair broken chip settings. There are some
	89	* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
	90	* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
	91	* Workaraound is to setup the correct register setting prior enabling the
	92	* L2 cache. This should not hurt already working CPUs, as they are using the
	93	* same value.
	94	*/
	95	#define L2_MEM_VAL 0x10
	96
	97	clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
	98	if (clkctl_base != NULL) {
	99	writel(0x00000515, clkctl_base + L2_MEM_VAL);
	100	iounmap(clkctl_base);
	101	} else {
	102	pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
	103	}
	104
	105	l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
	106	if (IS_ERR(l2x0_base)) {
	107	printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
	108	PTR_ERR(l2x0_base));
	109	return;
	110	}
	111
	112	l2x0_init(l2x0_base, 0x00030024, 0x00000000);
	113	}
	114
87514fce	115	#ifdef CONFIG_SOC_IMX31
27ad4bf7 UKK	116	static struct map_desc mx31_io_desc[] __initdata = {
	117	imx_map_entry(MX31, X_MEMC, MT_DEVICE),
	118	imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
	119	imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
	120	imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
	121	imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
	122	};
	123
	124	/*
	125	* This function initializes the memory map. It is called during the
	126	* system startup to create static physical to virtual memory mappings
	127	* for the IO modules.
	128	*/
	129	void __init mx31_map_io(void)
	130	{
	131	iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
	132	}
	133
	134	void __init imx31_init_early(void)
	135	{
	136	mxc_set_cpu_type(MXC_CPU_MX31);
	137	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
c177aa98	138	arch_ioremap_caller = imx3_ioremap_caller;
4a3ea244	139	arm_pm_idle = imx3_idle;
27ad4bf7 UKK	140	}
27ad4bf7 UKK	141
27ad4bf7 UKK	142	void __init mx31_init_irq(void)
	143	{
	144	mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
b78d8e59 SG	145	}
b78d8e59 SG	146
36223604 SG	147	static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
	148	.per_2_per_addr = 1677,
	149	};
	150
	151	static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
	152	.ap_2_ap_addr = 423,
	153	.ap_2_bp_addr = 829,
	154	.bp_2_ap_addr = 1029,
	155	};
	156
	157	static struct sdma_platform_data imx31_sdma_pdata __initdata = {
2e534b21	158	.fw_name = "sdma-imx31-to2.bin",
36223604 SG	159	.script_addrs = &imx31_to2_sdma_script,
	160	};
	161
3bc34a61 RZ	162	static const struct resource imx31_audmux_res[] __initconst = {
	163	DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
	164	};
	165
b78d8e59 SG	166	void __init imx31_soc_init(void)
b78d8e59 SG	167	{
36223604 SG	168	int to_version = mx31_revision() >> 4;
36223604 SG	169
ddd5f51b SG	170	imx3_init_l2x0();
ddd5f51b SG	171
e7fc6ae7 SG	172	mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
	173	mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
	174	mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
36223604	175
2e534b21 SG	176	if (to_version == 1) {
	177	strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
	178	strlen(imx31_sdma_pdata.fw_name));
36223604	179	imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
2e534b21 SG	180	}
2e534b21 SG	181
62550cd7	182	imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
bb07d751 FE	183
	184	imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
	185	imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
281b0539	186
3bc34a61 RZ	187	platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
3bc34a61 RZ	188	ARRAY_SIZE(imx31_audmux_res));
27ad4bf7	189	}
87514fce UKK	190	#endif /* ifdef CONFIG_SOC_IMX31 */
	191
	192	#ifdef CONFIG_SOC_IMX35
	193	static struct map_desc mx35_io_desc[] __initdata = {
	194	imx_map_entry(MX35, X_MEMC, MT_DEVICE),
	195	imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
	196	imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
	197	imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
	198	imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
	199	};
	200
	201	void __init mx35_map_io(void)
	202	{
	203	iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
	204	}
	205
	206	void __init imx35_init_early(void)
	207	{
	208	mxc_set_cpu_type(MXC_CPU_MX35);
	209	mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
	210	mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
4a3ea244	211	arm_pm_idle = imx3_idle;
c177aa98	212	arch_ioremap_caller = imx3_ioremap_caller;
87514fce UKK	213	}
	214
	215	void __init mx35_init_irq(void)
	216	{
	217	mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
	218	}
f1263de2 SG	219
	220	static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
	221	.ap_2_ap_addr = 642,
	222	.uart_2_mcu_addr = 817,
	223	.mcu_2_app_addr = 747,
	224	.uartsh_2_mcu_addr = 1183,
	225	.per_2_shp_addr = 1033,
	226	.mcu_2_shp_addr = 961,
	227	.ata_2_mcu_addr = 1333,
	228	.mcu_2_ata_addr = 1252,
	229	.app_2_mcu_addr = 683,
	230	.shp_2_per_addr = 1111,
	231	.shp_2_mcu_addr = 892,
	232	};
	233
	234	static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
	235	.ap_2_ap_addr = 729,
	236	.uart_2_mcu_addr = 904,
	237	.per_2_app_addr = 1597,
	238	.mcu_2_app_addr = 834,
	239	.uartsh_2_mcu_addr = 1270,
	240	.per_2_shp_addr = 1120,
	241	.mcu_2_shp_addr = 1048,
	242	.ata_2_mcu_addr = 1429,
	243	.mcu_2_ata_addr = 1339,
	244	.app_2_per_addr = 1531,
	245	.app_2_mcu_addr = 770,
	246	.shp_2_per_addr = 1198,
	247	.shp_2_mcu_addr = 979,
	248	};
	249
	250	static struct sdma_platform_data imx35_sdma_pdata __initdata = {
	251	.fw_name = "sdma-imx35-to2.bin",
	252	.script_addrs = &imx35_to2_sdma_script,
	253	};
	254
3bc34a61 RZ	255	static const struct resource imx35_audmux_res[] __initconst = {
	256	DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
	257	};
	258
f1263de2 SG	259	void __init imx35_soc_init(void)
	260	{
	261	int to_version = mx35_revision() >> 4;
	262
ddd5f51b SG	263	imx3_init_l2x0();
ddd5f51b SG	264
f1263de2 SG	265	/* i.mx35 has the i.mx31 type gpio */
	266	mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
	267	mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
	268	mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
	269
	270	if (to_version == 1) {
	271	strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
	272	strlen(imx35_sdma_pdata.fw_name));
	273	imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
	274	}
	275
	276	imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
38bb3630 FE	277
	278	/* Setup AIPS registers */
	279	imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
	280	imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
281b0539	281
3bc34a61 RZ	282	/* i.mx35 has the i.mx31 type audmux */
	283	platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
	284	ARRAY_SIZE(imx35_audmux_res));
f1263de2	285	}
87514fce	286	#endif /* ifdef CONFIG_SOC_IMX35 */