projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f31405cc JB |
1 | /* |
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
| 4 | * | |
| 260a1fd2 HS |
5 | * This contains i.MX27-specific hardware definitions. For those |
| 6 | * hardware pieces that are common between i.MX21 and i.MX27, have a | |
| 7 | * look at mx2x.h. | |
| 8 | * | |
| f31405cc JB |
9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License | |
| 11 | * as published by the Free Software Foundation; either version 2 | |
| 12 | * of the License, or (at your option) any later version. | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
| 21 | * MA 02110-1301, USA. | |
| 22 | */ | |
| 23 | ||
| 3cdd5441 UKK |
24 | #ifndef __MACH_MX27_H__ |
| 25 | #define __MACH_MX27_H__ | |
| f31405cc | 26 | |
| 2ae959f4 | 27 | #define MX27_AIPI_BASE_ADDR 0x10000000 |
| 2ae959f4 UKK |
28 | #define MX27_AIPI_SIZE SZ_1M |
| 29 | #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) | |
| 30 | #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) | |
| 31 | #define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000) | |
| 32 | #define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000) | |
| 33 | #define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000) | |
| 34 | #define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000) | |
| 35 | #define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000) | |
| 36 | #define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000) | |
| 37 | #define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000) | |
| 38 | #define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000) | |
| 39 | #define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000) | |
| 40 | #define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000) | |
| 41 | #define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000) | |
| 42 | #define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000) | |
| 43 | #define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) | |
| 44 | #define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) | |
| 45 | #define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) | |
| c6987159 | 46 | #define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) |
| 2ae959f4 UKK |
47 | #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) |
| 48 | #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) | |
| 49 | #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) | |
| d485c7e7 UKK |
50 | #define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) |
| 51 | #define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) | |
| 52 | #define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) | |
| 53 | #define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) | |
| 54 | #define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) | |
| 55 | #define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) | |
| 2ae959f4 UKK |
56 | #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) |
| 57 | #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) | |
| 58 | #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) | |
| 986e5f08 WS |
59 | #define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) |
| 60 | #define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) | |
| 2ae959f4 UKK |
61 | #define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) |
| 62 | #define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) | |
| 63 | #define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) | |
| 64 | #define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000) | |
| 65 | #define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000) | |
| 66 | #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) | |
| 67 | #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) | |
| 68 | #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) | |
| 2eb42d5c UKK |
69 | #define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) |
| 70 | #define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) | |
| 71 | #define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) | |
| 72 | #define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) | |
| 2ae959f4 | 73 | #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) |
| b2997cb1 UKK |
74 | #define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) |
| 75 | #define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) | |
| 2ae959f4 UKK |
76 | #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) |
| 77 | #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) | |
| 78 | #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) | |
| 79 | #define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000) | |
| 80 | #define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000) | |
| 81 | #define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000) | |
| 82 | #define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000) | |
| 83 | #define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000) | |
| 84 | #define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000) | |
| 85 | #define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000) | |
| 86 | ||
| 87 | #define MX27_AVIC_BASE_ADDR 0x10040000 | |
| f31405cc | 88 | |
| 260a1fd2 | 89 | /* ROM patch */ |
| 26b10e74 | 90 | #define MX27_ROMP_BASE_ADDR 0x10041000 |
| f31405cc | 91 | |
| 2ae959f4 | 92 | #define MX27_SAHB1_BASE_ADDR 0x80000000 |
| 2ae959f4 UKK |
93 | #define MX27_SAHB1_SIZE SZ_1M |
| 94 | #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) | |
| 95 | #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) | |
| f31405cc | 96 | |
| f31405cc | 97 | /* Memory regions and CS */ |
| 26b10e74 UKK |
98 | #define MX27_SDRAM_BASE_ADDR 0xa0000000 |
| 99 | #define MX27_CSD1_BASE_ADDR 0xb0000000 | |
| f31405cc | 100 | |
| 26b10e74 UKK |
101 | #define MX27_CS0_BASE_ADDR 0xc0000000 |
| 102 | #define MX27_CS1_BASE_ADDR 0xc8000000 | |
| 103 | #define MX27_CS2_BASE_ADDR 0xd0000000 | |
| 104 | #define MX27_CS3_BASE_ADDR 0xd2000000 | |
| 105 | #define MX27_CS4_BASE_ADDR 0xd4000000 | |
| 106 | #define MX27_CS5_BASE_ADDR 0xd6000000 | |
| f31405cc | 107 | |
| 260a1fd2 | 108 | /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ |
| 26b10e74 | 109 | #define MX27_X_MEMC_BASE_ADDR 0xd8000000 |
| 26b10e74 UKK |
110 | #define MX27_X_MEMC_SIZE SZ_1M |
| 111 | #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) | |
| 112 | #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) | |
| 113 | #define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000) | |
| 114 | #define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) | |
| 115 | #define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) | |
| f31405cc | 116 | |
| a8dfb646 UKK |
117 | #define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10) |
| 118 | #define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs)) | |
| 119 | #define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) | |
| 120 | #define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) | |
| 121 | ||
| 26b10e74 | 122 | #define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 |
| f73a42f7 UKK |
123 | |
| 124 | /* IRAM */ | |
| 26b10e74 | 125 | #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ |
| f73a42f7 | 126 | |
| a9963148 | 127 | #define MX27_IO_P2V(x) IMX_IO_P2V(x) |
| f5d7a13b | 128 | #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) |
| bc9ea6c7 | 129 | |
| 260a1fd2 | 130 | /* fixed interrupt numbers */ |
| 8842a9e2 SG |
131 | #include <asm/irq.h> |
| 132 | #define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1) | |
| 133 | #define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2) | |
| 134 | #define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3) | |
| 135 | #define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4) | |
| 136 | #define MX27_INT_RTIC (NR_IRQS_LEGACY + 5) | |
| 137 | #define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6) | |
| 0d5ca6d9 | 138 | #define MX27_INT_MSHC (NR_IRQS_LEGACY + 7) |
| 8842a9e2 SG |
139 | #define MX27_INT_GPIO (NR_IRQS_LEGACY + 8) |
| 140 | #define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9) | |
| 141 | #define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10) | |
| 142 | #define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11) | |
| 143 | #define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12) | |
| 144 | #define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13) | |
| 145 | #define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14) | |
| 146 | #define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15) | |
| 147 | #define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16) | |
| 148 | #define MX27_INT_UART4 (NR_IRQS_LEGACY + 17) | |
| 149 | #define MX27_INT_UART3 (NR_IRQS_LEGACY + 18) | |
| 150 | #define MX27_INT_UART2 (NR_IRQS_LEGACY + 19) | |
| 151 | #define MX27_INT_UART1 (NR_IRQS_LEGACY + 20) | |
| 152 | #define MX27_INT_KPP (NR_IRQS_LEGACY + 21) | |
| 153 | #define MX27_INT_RTC (NR_IRQS_LEGACY + 22) | |
| 154 | #define MX27_INT_PWM (NR_IRQS_LEGACY + 23) | |
| 155 | #define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24) | |
| 156 | #define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25) | |
| 157 | #define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26) | |
| 158 | #define MX27_INT_WDOG (NR_IRQS_LEGACY + 27) | |
| 159 | #define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28) | |
| 160 | #define MX27_INT_NFC (NR_IRQS_LEGACY + 29) | |
| 161 | #define MX27_INT_ATA (NR_IRQS_LEGACY + 30) | |
| 162 | #define MX27_INT_CSI (NR_IRQS_LEGACY + 31) | |
| 163 | #define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32) | |
| 164 | #define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33) | |
| 165 | #define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34) | |
| 166 | #define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35) | |
| 167 | #define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36) | |
| 168 | #define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37) | |
| 169 | #define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38) | |
| 170 | #define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39) | |
| 171 | #define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40) | |
| 172 | #define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41) | |
| 173 | #define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42) | |
| 174 | #define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43) | |
| 175 | #define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44) | |
| 176 | #define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45) | |
| 177 | #define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46) | |
| 178 | #define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47) | |
| 179 | #define MX27_INT_UART6 (NR_IRQS_LEGACY + 48) | |
| 180 | #define MX27_INT_UART5 (NR_IRQS_LEGACY + 49) | |
| 181 | #define MX27_INT_FEC (NR_IRQS_LEGACY + 50) | |
| 182 | #define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51) | |
| 183 | #define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52) | |
| 184 | #define MX27_INT_VPU (NR_IRQS_LEGACY + 53) | |
| 185 | #define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54) | |
| 186 | #define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55) | |
| 187 | #define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56) | |
| 188 | #define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57) | |
| 189 | #define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58) | |
| 190 | #define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59) | |
| 191 | #define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60) | |
| 192 | #define MX27_INT_LCDC (NR_IRQS_LEGACY + 61) | |
| 193 | #define MX27_INT_IIM (NR_IRQS_LEGACY + 62) | |
| 194 | #define MX27_INT_CCM (NR_IRQS_LEGACY + 63) | |
| f31405cc JB |
195 | |
| 196 | /* fixed DMA request numbers */ | |
| 2ae959f4 UKK |
197 | #define MX27_DMA_REQ_CSPI3_RX 1 |
| 198 | #define MX27_DMA_REQ_CSPI3_TX 2 | |
| 199 | #define MX27_DMA_REQ_EXT 3 | |
| 26b10e74 | 200 | #define MX27_DMA_REQ_MSHC 4 |
| 2ae959f4 UKK |
201 | #define MX27_DMA_REQ_SDHC2 6 |
| 202 | #define MX27_DMA_REQ_SDHC1 7 | |
| 203 | #define MX27_DMA_REQ_SSI2_RX0 8 | |
| 204 | #define MX27_DMA_REQ_SSI2_TX0 9 | |
| 205 | #define MX27_DMA_REQ_SSI2_RX1 10 | |
| 206 | #define MX27_DMA_REQ_SSI2_TX1 11 | |
| 207 | #define MX27_DMA_REQ_SSI1_RX0 12 | |
| 208 | #define MX27_DMA_REQ_SSI1_TX0 13 | |
| 209 | #define MX27_DMA_REQ_SSI1_RX1 14 | |
| 210 | #define MX27_DMA_REQ_SSI1_TX1 15 | |
| 211 | #define MX27_DMA_REQ_CSPI2_RX 16 | |
| 212 | #define MX27_DMA_REQ_CSPI2_TX 17 | |
| 213 | #define MX27_DMA_REQ_CSPI1_RX 18 | |
| 214 | #define MX27_DMA_REQ_CSPI1_TX 19 | |
| 215 | #define MX27_DMA_REQ_UART4_RX 20 | |
| 216 | #define MX27_DMA_REQ_UART4_TX 21 | |
| 217 | #define MX27_DMA_REQ_UART3_RX 22 | |
| 218 | #define MX27_DMA_REQ_UART3_TX 23 | |
| 219 | #define MX27_DMA_REQ_UART2_RX 24 | |
| 220 | #define MX27_DMA_REQ_UART2_TX 25 | |
| 221 | #define MX27_DMA_REQ_UART1_RX 26 | |
| 222 | #define MX27_DMA_REQ_UART1_TX 27 | |
| 26b10e74 UKK |
223 | #define MX27_DMA_REQ_ATA_TX 28 |
| 224 | #define MX27_DMA_REQ_ATA_RCV 29 | |
| 2ae959f4 UKK |
225 | #define MX27_DMA_REQ_CSI_STAT 30 |
| 226 | #define MX27_DMA_REQ_CSI_RX 31 | |
| 26b10e74 UKK |
227 | #define MX27_DMA_REQ_UART5_TX 32 |
| 228 | #define MX27_DMA_REQ_UART5_RX 33 | |
| 229 | #define MX27_DMA_REQ_UART6_TX 34 | |
| 230 | #define MX27_DMA_REQ_UART6_RX 35 | |
| 231 | #define MX27_DMA_REQ_SDHC3 36 | |
| 232 | #define MX27_DMA_REQ_NFC 37 | |
| f31405cc | 233 | |
| 3cdd5441 | 234 | #endif /* ifndef __MACH_MX27_H__ */ |