[deliverable/linux.git] / arch / arm / mach-imx / src.c

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/reset-controller.h>
#include <linux/smp.h>
#include <asm/smp_plat.h>
#include "common.h"

#define SRC_SCR				0x000
#define SRC_GPR1			0x020
#define BP_SRC_SCR_WARM_RESET_ENABLE	0
#define BP_SRC_SCR_SW_GPU_RST		1
#define BP_SRC_SCR_SW_VPU_RST		2
#define BP_SRC_SCR_SW_IPU1_RST		3
#define BP_SRC_SCR_SW_OPEN_VG_RST	4
#define BP_SRC_SCR_SW_IPU2_RST		12
#define BP_SRC_SCR_CORE1_RST		14
#define BP_SRC_SCR_CORE1_ENABLE		22

static void __iomem *src_base;
static DEFINE_SPINLOCK(scr_lock);

static const int sw_reset_bits[5] = {
	BP_SRC_SCR_SW_GPU_RST,
	BP_SRC_SCR_SW_VPU_RST,
	BP_SRC_SCR_SW_IPU1_RST,
	BP_SRC_SCR_SW_OPEN_VG_RST,
	BP_SRC_SCR_SW_IPU2_RST
};

static int imx_src_reset_module(struct reset_controller_dev *rcdev,
		unsigned long sw_reset_idx)
{
	unsigned long timeout;
	unsigned long flags;
	int bit;
	u32 val;

	if (!src_base)
		return -ENODEV;

	if (sw_reset_idx >= ARRAY_SIZE(sw_reset_bits))
		return -EINVAL;

	bit = 1 << sw_reset_bits[sw_reset_idx];

	spin_lock_irqsave(&scr_lock, flags);
	val = readl_relaxed(src_base + SRC_SCR);
	val |= bit;
	writel_relaxed(val, src_base + SRC_SCR);
	spin_unlock_irqrestore(&scr_lock, flags);

	timeout = jiffies + msecs_to_jiffies(1000);
	while (readl(src_base + SRC_SCR) & bit) {
		if (time_after(jiffies, timeout))
			return -ETIME;
		cpu_relax();
	}

	return 0;
}

static const struct reset_control_ops imx_src_ops = {
	.reset = imx_src_reset_module,
};

static struct reset_controller_dev imx_reset_controller = {
	.ops = &imx_src_ops,
	.nr_resets = ARRAY_SIZE(sw_reset_bits),
};

void imx_enable_cpu(int cpu, bool enable)
{
	u32 mask, val;

	cpu = cpu_logical_map(cpu);
	mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
	spin_lock(&scr_lock);
	val = readl_relaxed(src_base + SRC_SCR);
	val = enable ? val | mask : val & ~mask;
	val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
	writel_relaxed(val, src_base + SRC_SCR);
	spin_unlock(&scr_lock);
}

void imx_set_cpu_jump(int cpu, void *jump_addr)
{
	cpu = cpu_logical_map(cpu);
	writel_relaxed(virt_to_phys(jump_addr),
		       src_base + SRC_GPR1 + cpu * 8);
}

u32 imx_get_cpu_arg(int cpu)
{
	cpu = cpu_logical_map(cpu);
	return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
}

void imx_set_cpu_arg(int cpu, u32 arg)
{
	cpu = cpu_logical_map(cpu);
	writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
}

void __init imx_src_init(void)
{
	struct device_node *np;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src");
	if (!np)
		return;
	src_base = of_iomap(np, 0);
	WARN_ON(!src_base);

	imx_reset_controller.of_node = np;
	if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
		reset_controller_register(&imx_reset_controller);

	/*
	 * force warm reset sources to generate cold reset
	 * for a more reliable restart
	 */
	spin_lock(&scr_lock);
	val = readl_relaxed(src_base + SRC_SCR);
	val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
	writel_relaxed(val, src_base + SRC_SCR);
	spin_unlock(&scr_lock);
}
Commit	Line	Data
9fbbe689 SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/io.h>
	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
02985b94	17	#include <linux/reset-controller.h>
eaa142ca	18	#include <linux/smp.h>
eb50439b	19	#include <asm/smp_plat.h>
09898576	20	#include "common.h"
9fbbe689 SG	21
	22	#define SRC_SCR 0x000
	23	#define SRC_GPR1 0x020
0575fb75	24	#define BP_SRC_SCR_WARM_RESET_ENABLE 0
02985b94 PZ	25	#define BP_SRC_SCR_SW_GPU_RST 1
	26	#define BP_SRC_SCR_SW_VPU_RST 2
	27	#define BP_SRC_SCR_SW_IPU1_RST 3
	28	#define BP_SRC_SCR_SW_OPEN_VG_RST 4
	29	#define BP_SRC_SCR_SW_IPU2_RST 12
9fbbe689 SG	30	#define BP_SRC_SCR_CORE1_RST 14
	31	#define BP_SRC_SCR_CORE1_ENABLE 22
	32
	33	static void __iomem *src_base;
02985b94 PZ	34	static DEFINE_SPINLOCK(scr_lock);
	35
	36	static const int sw_reset_bits[5] = {
	37	BP_SRC_SCR_SW_GPU_RST,
	38	BP_SRC_SCR_SW_VPU_RST,
	39	BP_SRC_SCR_SW_IPU1_RST,
	40	BP_SRC_SCR_SW_OPEN_VG_RST,
	41	BP_SRC_SCR_SW_IPU2_RST
	42	};
	43
	44	static int imx_src_reset_module(struct reset_controller_dev *rcdev,
	45	unsigned long sw_reset_idx)
	46	{
	47	unsigned long timeout;
	48	unsigned long flags;
	49	int bit;
	50	u32 val;
	51
	52	if (!src_base)
	53	return -ENODEV;
	54
	55	if (sw_reset_idx >= ARRAY_SIZE(sw_reset_bits))
	56	return -EINVAL;
	57
	58	bit = 1 << sw_reset_bits[sw_reset_idx];
	59
	60	spin_lock_irqsave(&scr_lock, flags);
	61	val = readl_relaxed(src_base + SRC_SCR);
	62	val \|= bit;
	63	writel_relaxed(val, src_base + SRC_SCR);
	64	spin_unlock_irqrestore(&scr_lock, flags);
	65
	66	timeout = jiffies + msecs_to_jiffies(1000);
	67	while (readl(src_base + SRC_SCR) & bit) {
	68	if (time_after(jiffies, timeout))
	69	return -ETIME;
	70	cpu_relax();
	71	}
	72
	73	return 0;
	74	}
	75
d2443b2e	76	static const struct reset_control_ops imx_src_ops = {
02985b94 PZ	77	.reset = imx_src_reset_module,
	78	};
	79
	80	static struct reset_controller_dev imx_reset_controller = {
	81	.ops = &imx_src_ops,
	82	.nr_resets = ARRAY_SIZE(sw_reset_bits),
	83	};
9fbbe689 SG	84
	85	void imx_enable_cpu(int cpu, bool enable)
	86	{
	87	u32 mask, val;
	88
eaa142ca	89	cpu = cpu_logical_map(cpu);
9fbbe689	90	mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
02985b94	91	spin_lock(&scr_lock);
9fbbe689 SG	92	val = readl_relaxed(src_base + SRC_SCR);
9fbbe689 SG	93	val = enable ? val \| mask : val & ~mask;
6050d181	94	val \|= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
9fbbe689	95	writel_relaxed(val, src_base + SRC_SCR);
02985b94	96	spin_unlock(&scr_lock);
9fbbe689 SG	97	}
	98
	99	void imx_set_cpu_jump(int cpu, void *jump_addr)
	100	{
eaa142ca	101	cpu = cpu_logical_map(cpu);
0a60cb14	102	writel_relaxed(virt_to_phys(jump_addr),
9fbbe689 SG	103	src_base + SRC_GPR1 + cpu * 8);
	104	}
	105
2f3edfd7 SG	106	u32 imx_get_cpu_arg(int cpu)
	107	{
	108	cpu = cpu_logical_map(cpu);
	109	return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
	110	}
	111
	112	void imx_set_cpu_arg(int cpu, u32 arg)
	113	{
	114	cpu = cpu_logical_map(cpu);
	115	writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
	116	}
	117
9fbbe689 SG	118	void __init imx_src_init(void)
	119	{
	120	struct device_node *np;
0575fb75	121	u32 val;
9fbbe689	122
bd3d924d PZ	123	np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src");
	124	if (!np)
	125	return;
9fbbe689 SG	126	src_base = of_iomap(np, 0);
9fbbe689 SG	127	WARN_ON(!src_base);
0575fb75	128
02985b94	129	imx_reset_controller.of_node = np;
5c5f0421 AB	130	if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
5c5f0421 AB	131	reset_controller_register(&imx_reset_controller);
02985b94	132
0575fb75 SG	133	/*
	134	* force warm reset sources to generate cold reset
	135	* for a more reliable restart
	136	*/
02985b94	137	spin_lock(&scr_lock);
0575fb75 SG	138	val = readl_relaxed(src_base + SRC_SCR);
	139	val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
	140	writel_relaxed(val, src_base + SRC_SCR);
02985b94	141	spin_unlock(&scr_lock);
9fbbe689	142	}