projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| c852ac80 | 2 | * arch/arm/mach-iop32x/irq.c |
| 1da177e4 | 3 | * |
| 3f7e5815 | 4 | * Generic IOP32X IRQ handling functionality |
| 1da177e4 LT |
5 | * |
| 6 | * Author: Rory Bolt <rorybolt@pacbell.net> | |
| 7 | * Copyright (C) 2002 Rory Bolt | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License version 2 as | |
| 11 | * published by the Free Software Foundation. | |
| 1da177e4 | 12 | */ |
| c852ac80 | 13 | |
| 1da177e4 LT |
14 | #include <linux/init.h> |
| 15 | #include <linux/interrupt.h> | |
| 16 | #include <linux/list.h> | |
| 1da177e4 LT |
17 | #include <asm/mach/irq.h> |
| 18 | #include <asm/irq.h> | |
| 19 | #include <asm/hardware.h> | |
| 1da177e4 LT |
20 | #include <asm/mach-types.h> |
| 21 | ||
| c852ac80 | 22 | static u32 iop32x_mask; |
| 1da177e4 LT |
23 | |
| 24 | static inline void intctl_write(u32 val) | |
| 25 | { | |
| 38ce73eb | 26 | iop3xx_cp6_enable(); |
| c852ac80 | 27 | asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); |
| 38ce73eb | 28 | iop3xx_cp6_disable(); |
| 1da177e4 LT |
29 | } |
| 30 | ||
| 31 | static inline void intstr_write(u32 val) | |
| 32 | { | |
| 38ce73eb | 33 | iop3xx_cp6_enable(); |
| c852ac80 | 34 | asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); |
| 38ce73eb | 35 | iop3xx_cp6_disable(); |
| 1da177e4 LT |
36 | } |
| 37 | ||
| 38 | static void | |
| c852ac80 | 39 | iop32x_irq_mask(unsigned int irq) |
| 1da177e4 | 40 | { |
| c852ac80 LB |
41 | iop32x_mask &= ~(1 << irq); |
| 42 | intctl_write(iop32x_mask); | |
| 1da177e4 LT |
43 | } |
| 44 | ||
| 45 | static void | |
| c852ac80 | 46 | iop32x_irq_unmask(unsigned int irq) |
| 1da177e4 | 47 | { |
| c852ac80 LB |
48 | iop32x_mask |= 1 << irq; |
| 49 | intctl_write(iop32x_mask); | |
| 1da177e4 LT |
50 | } |
| 51 | ||
| 38c677cb | 52 | struct irq_chip ext_chip = { |
| c852ac80 LB |
53 | .name = "IOP32x", |
| 54 | .ack = iop32x_irq_mask, | |
| 55 | .mask = iop32x_irq_mask, | |
| 56 | .unmask = iop32x_irq_unmask, | |
| 1da177e4 LT |
57 | }; |
| 58 | ||
| c852ac80 | 59 | void __init iop32x_init_irq(void) |
| 1da177e4 | 60 | { |
| c852ac80 | 61 | int i; |
| 1da177e4 | 62 | |
| 588ef769 DW |
63 | iop_init_cp6_handler(); |
| 64 | ||
| c852ac80 LB |
65 | intctl_write(0); |
| 66 | intstr_write(0); | |
| 0c92e830 LB |
67 | if (machine_is_glantank() || |
| 68 | machine_is_iq80321() || | |
| e60d07b6 LB |
69 | machine_is_iq31244() || |
| 70 | machine_is_n2100()) | |
| 7e9740b1 | 71 | *IOP3XX_PCIIRSR = 0x0f; |
| 1da177e4 | 72 | |
| c852ac80 | 73 | for (i = 0; i < NR_IRQS; i++) { |
| 1da177e4 | 74 | set_irq_chip(i, &ext_chip); |
| 10dd5ce2 | 75 | set_irq_handler(i, handle_level_irq); |
| 1da177e4 | 76 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
| 1da177e4 LT |
77 | } |
| 78 | } |